JPS63106221U - - Google Patents
Info
- Publication number
- JPS63106221U JPS63106221U JP19915386U JP19915386U JPS63106221U JP S63106221 U JPS63106221 U JP S63106221U JP 19915386 U JP19915386 U JP 19915386U JP 19915386 U JP19915386 U JP 19915386U JP S63106221 U JPS63106221 U JP S63106221U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- circuit
- flop
- flip
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図の各部の信号を示すタイム・チ
ヤート、第３図及び第４図は従来の装置を示すブ
ロツク図である。
１及び２はＲＣ時定数回路を構成する抵抗器及
びキヤパシタ、３はダイオード、４はＮＯＴゲー
ト、５はカウンタ、６ａ及び６ｂはＲＳフリツプ
・フロツプを構成するＮＯＲゲート、８はマイク
ロ・プロセツサ、３０はヒステリシス特性を持つ
ゲート素子、４０はアナログ回路を示す。なお、
図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a time chart showing signals of various parts in FIG. 1, and FIGS. 3 and 4 are block diagrams showing conventional devices. 1 and 2 are resistors and capacitors forming an RC time constant circuit, 3 is a diode, 4 is a NOT gate, 5 is a counter, 6a and 6b are NOR gates forming an RS flip-flop, 8 is a microprocessor, 30 Reference numeral 40 indicates a gate element having hysteresis characteristics, and 40 indicates an analog circuit. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
回路において、キヤリー出力を有し、上記ＲＣ回
路によつてリセツトされるカウンタ、及び、上記
ＲＣ回路によつてセツトされ、上記キヤリー出力
によつてリセツトされるＲＳフリツプ・フロツプ
を備え、上記ＲＳフリツプ・フロツプの出口をパ
ワー・オン・リセツト信号とすることを特徴とす
る情報処理装置のリセツト回路。 A power-on reset circuit using an RC time constant circuit includes a counter that has a carry output and is reset by the RC circuit, and a counter that is set by the RC circuit and reset by the carry output. 1. A reset circuit for an information processing device, comprising an RS flip-flop, and an output of the RS flip-flop as a power-on reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19915386U JPS63106221U (en) | 1986-12-26 | 1986-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19915386U JPS63106221U (en) | 1986-12-26 | 1986-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63106221U true JPS63106221U (en) | 1988-07-09 |
Family
ID=31160510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19915386U Pending JPS63106221U (en) | 1986-12-26 | 1986-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63106221U (en) |
-
1986
- 1986-12-26 JP JP19915386U patent/JPS63106221U/ja active Pending
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