JPS631058A - Photosensor - Google Patents

Photosensor

Info

Publication number
JPS631058A
JPS631058A JP61144265A JP14426586A JPS631058A JP S631058 A JPS631058 A JP S631058A JP 61144265 A JP61144265 A JP 61144265A JP 14426586 A JP14426586 A JP 14426586A JP S631058 A JPS631058 A JP S631058A
Authority
JP
Japan
Prior art keywords
polycrystalline
layer
signal processing
processing circuit
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61144265A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
久雄 林
Takeshi Matsushita
松下 孟史
Toshiichi Maekawa
敏一 前川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP61144265A priority Critical patent/JPS631058A/en
Publication of JPS631058A publication Critical patent/JPS631058A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To obtain a large-sized image sensor having high preformance by forming a photodetection element and a signal processing circuit to a polycrystalline semiconductor layer. CONSTITUTION:Polycrystalline semiconductor layers 12, 15 are shaped onto an insulator substrate 11, and a photodetection element 23 and a signal processing circuit 27 are formed to each semiconductor layer 12, 15. Accordingly, electrical characteristics such as the speed of response are improved, and monolithic integration is enabled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、光検出素子とこの光検出素子から出力される
信号を処理するための信号処理回路とを有する光センサ
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optical sensor having a photodetecting element and a signal processing circuit for processing a signal output from the photodetecting element.

〔発明の概要〕[Summary of the invention]

本発明は、上記の様な光センサにおいて、絶縁物基板上
に多結晶半導体層に形成し、この多結晶半導体層に光検
出素子と信号処理回路とを形成することによって、高性
能で且つ大型のイメージセンサを低コストで提供するこ
とができる様にしたものである。
The present invention provides a high-performance and large-sized optical sensor by forming a polycrystalline semiconductor layer on an insulating substrate, and forming a photodetecting element and a signal processing circuit on this polycrystalline semiconductor layer. This image sensor can be provided at low cost.

〔従来の技術〕[Conventional technology]

近年、ファクシミリや複写機等の各種光学機器において
、集光等を行うための光学系を簡略化して光学機器の小
型化や低コスト化を図るために、大型のイメージセンサ
が求められている。
2. Description of the Related Art In recent years, large-sized image sensors have been required in various optical devices such as facsimiles and copying machines in order to simplify optical systems for condensing light, etc., and thereby reduce the size and cost of the optical devices.

しかし、大口径の半導体ウェハの製造が容易でないため
に、半導体基板内に大型のイメージセンサを作成するの
は容易でない。
However, since it is not easy to manufacture large-diameter semiconductor wafers, it is not easy to create a large-sized image sensor within a semiconductor substrate.

このために、大口径化の容易な絶縁物基板上に薄膜半導
体を形成し、この薄膜半導体に大型のイメージセンサを
作成する試みがなされている。そしてこの様な薄膜半導
体として、a −3i : tlやCd。
For this reason, attempts have been made to form a thin film semiconductor on an insulating substrate whose diameter can be easily increased, and to create a large image sensor using this thin film semiconductor. Examples of such thin film semiconductors include a-3i: tl and Cd.

Se等のカルコゲン半導体が用いられている。A chalcogen semiconductor such as Se is used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上記の何れの薄膜半導体を用いた場合も、光検
出素子の応答速度が遅く、所望の性能を得ることが難し
い。
However, when any of the above thin film semiconductors is used, the response speed of the photodetecting element is slow, making it difficult to obtain desired performance.

また、光検出素子から出力される信号を処理するための
信号処理回路をも上記の薄膜半導体に形成してモノリシ
ックに集積化しようとすると、やはりこの信号処理回路
の処理速度が遅い。このために、信号処理回路用の別個
の部品を絶縁物基板に組み込んでハイブリッドに集積化
せざるを得ないが、この場合は実装コストが高い。
Furthermore, if a signal processing circuit for processing the signal output from the photodetecting element is also formed on the thin film semiconductor and monolithically integrated, the processing speed of this signal processing circuit is still slow. For this reason, it is necessary to incorporate separate components for the signal processing circuit into an insulating substrate for hybrid integration, but in this case the implementation cost is high.

〔問題点を解決するための手段〕[Means for solving problems]

本発明による光センサでは、絶縁物基板11上に多結晶
半導体層12.15が形成されており、この多結晶半導
体層12.15に光検出素子23と信号処理回路27と
が形成されている。
In the optical sensor according to the present invention, a polycrystalline semiconductor layer 12.15 is formed on an insulating substrate 11, and a photodetection element 23 and a signal processing circuit 27 are formed on this polycrystalline semiconductor layer 12.15. .

〔作用〕[Effect]

本発明による光センサでは、光検出素子23と信号処理
回路27とが共に多結晶半導体層12.15に形成され
ているので、応答速度等の電気的特性が良(、しかもモ
ノリシックな集積化が可能である。
In the optical sensor according to the present invention, since both the photodetecting element 23 and the signal processing circuit 27 are formed in the polycrystalline semiconductor layer 12.15, electrical characteristics such as response speed are good (and monolithic integration is possible). It is possible.

また、光検出素子23と信号処理回路27とが形成され
ている多結晶半導体層12.15が絶縁物基板11上に
形成されているので、大型化が容易である。
Further, since the polycrystalline semiconductor layer 12.15 on which the photodetector element 23 and the signal processing circuit 27 are formed is formed on the insulator substrate 11, it is easy to increase the size.

〔実施例〕〔Example〕

以下、PIN−PDを光検出素子とする薄膜イメージセ
ンサに適用した本発明の一実施例を第1図及び第2図を
参照しながら説明する。
Hereinafter, an embodiment of the present invention applied to a thin film image sensor using a PIN-PD as a photodetecting element will be described with reference to FIGS. 1 and 2.

第1図が本実施例を示しているが、まずその製造工程を
第2図に基いて説明する。本実施例を製造するためには
、まず減圧CVDによって、第2A図に示す様にSiO
□iO□1上に厚さ800人程度の多結晶Si層12を
成長させる。
Although FIG. 1 shows this embodiment, its manufacturing process will first be explained based on FIG. 2. In order to manufacture this example, first, SiO
A polycrystalline Si layer 12 with a thickness of about 800 layers is grown on □iO□1.

そして、Si’°イオンを多結晶St層12に注入する
ことによってこの多結晶Si層12を一旦非晶譬化と、
その後、600℃程度の温度で熱処理を行う。するとこ
の熱処理によって、非晶質化していた多結晶5iJli
12が再び多結晶化するが、この時点の多結晶Si層1
2は、結晶性が良く従って電気的特性が良い。
Then, by implanting Si'° ions into the polycrystalline St layer 12, the polycrystalline Si layer 12 is once made amorphous.
Thereafter, heat treatment is performed at a temperature of about 600°C. Then, due to this heat treatment, the polycrystalline 5iJli, which had become amorphous,
12 becomes polycrystalline again, but the polycrystalline Si layer 1 at this point
No. 2 has good crystallinity and therefore good electrical characteristics.

次に、第2B図に示す様に、CVDによって多結晶Si
層12上に5i02層13を成長させ、更にこのSiO
□層工3のうちでPIN−PDを形成すべき領域に開口
14を形成する。
Next, as shown in FIG. 2B, polycrystalline Si is formed by CVD.
A 5i02 layer 13 is grown on the layer 12, and this SiO2 layer 13 is grown on the layer 12.
□An opening 14 is formed in a region of the layered work 3 where a PIN-PD is to be formed.

次に、SiH4または5illzC1zとIIcI と
の混合ガスを用いて高温下で、第2C図に示す様に開口
14にのみ選択的に多結晶St層15をエピタキシャル
成長させる。
Next, a polycrystalline St layer 15 is epitaxially grown selectively only in the opening 14 as shown in FIG. 2C at a high temperature using a mixed gas of SiH4 or 5illzC1z and IIcI.

多結晶Si層15はエピタキシャル成長によって形成さ
れているので、多結晶5tJli515と多結晶Si層
12との間には界面がない。多結晶Si層15と12と
の合計のjアさは、検出すべき光の波長に基いて選定さ
れるが、2.0μm程度は必要である。
Since the polycrystalline Si layer 15 is formed by epitaxial growth, there is no interface between the polycrystalline 5tJli 515 and the polycrystalline Si layer 12. The total thickness of the polycrystalline Si layers 15 and 12 is selected based on the wavelength of the light to be detected, but approximately 2.0 μm is required.

次に、第2D図に示す様に、SiO□層13全13し、
更に多結晶Si層12を選択的にエツチングすることに
よって、PIN−PDを形成すべき領域及び信号処理用
のCMO5を形成すべき領域以外の領域に素子間分離領
域16を形成する。なおこの素間分11iI領域16は
、第2A図に示した多結晶Si層12の形成工程で形成
しておいてもよい。
Next, as shown in FIG. 2D, the entire SiO□ layer 13 is formed,
Furthermore, by selectively etching the polycrystalline Si layer 12, element isolation regions 16 are formed in regions other than the region where the PIN-PD is to be formed and the region where the CMO 5 for signal processing is to be formed. Note that this elemental portion 11iI region 16 may be formed in the step of forming the polycrystalline Si layer 12 shown in FIG. 2A.

次に、第2E図に示す様に、上記のCMO3のゲート絶
縁膜17a、17bと多結晶Siがら成るゲート電極1
8a、18bとを形成する。
Next, as shown in FIG. 2E, a gate electrode 1 made of the above CMO3 gate insulating films 17a and 17b and polycrystalline Si is formed.
8a and 18b are formed.

次に、第2F図に示す様に、多結晶Si層15とゲート
電118bとの間の領域以外の領域をマスク21で覆う
。そしてこの状態で、5価元素のイオンを注入する。
Next, as shown in FIG. 2F, regions other than the region between the polycrystalline Si layer 15 and the gate electrode 118b are covered with a mask 21. Then, as shown in FIG. In this state, ions of a pentavalent element are implanted.

次に、マスク21を除去した後に、第2G図に示す様に
、第2F図の工程でイオン注入を行った領域と多結晶S
i層15の近傍とをマスク22で覆う。そしてこの状態
で、3価元素のイオンを注入する。なお、第2F図の工
程と第20UAの工程とは、何れが先であってもよい。
Next, after removing the mask 21, as shown in FIG. 2G, the region where ions were implanted in the step of FIG. 2F and the polycrystalline S
The vicinity of the i-layer 15 is covered with a mask 22. In this state, ions of a trivalent element are implanted. Note that either the process in FIG. 2F or the process in 20UA may occur first.

この様にして、第2H図に示す様に、Pl!1−PD2
3のP影領域24、I影領域25及びN影領域26とC
MO327のソース・ドレイン領域28a、28b及び
チャネル領域29a、29bとが形成される。
In this way, as shown in Figure 2H, Pl! 1-PD2
3 P shadow area 24, I shadow area 25, N shadow area 26 and C
Source/drain regions 28a, 28b and channel regions 29a, 29b of MO 327 are formed.

なお、この第2H図から明らかな様に、PIN−PD2
3のP影領域24とI影領域25との境界面23a、及
びN影領域26とI影領域25との境界面23bの何れ
もが、多結晶Si層12に形成されており、これらの境
界面23a、23bの面積は非常に小さい。
Furthermore, as is clear from this Fig. 2H, PIN-PD2
Both the boundary surface 23a between the P shadow region 24 and the I shadow region 25 and the boundary surface 23b between the N shadow region 26 and the I shadow region 25 in No. 3 are formed in the polycrystalline Si layer 12. The areas of the boundary surfaces 23a and 23b are very small.

次いで、この第2H図に示す様にマスク22を除去し、
第1図に示す様に5in2やPSG等から成り厚さが5
000人程度である層間絶縁膜31とやはり厚さが50
00人程度であるA1電極32とを形成すれば、本実施
例の薄膜イメージセンサが形成される。
Next, as shown in FIG. 2H, the mask 22 is removed,
As shown in Figure 1, it is made of 5in2, PSG, etc. and has a thickness of 5.
The thickness of the interlayer insulating film 31 is about 50,000.
By forming approximately 00 A1 electrodes 32, the thin film image sensor of this embodiment is formed.

この薄膜イメージセンサ中のPIN−PD23では、I
影領域25のうちで多結晶Si層15とこの多結晶Si
層15の直下の多結晶Si層12とから成り2.0μm
程度の厚さを有している部分で入射光が吸収され、多結
晶5ilW12のみから成りS。
In PIN-PD23 in this thin film image sensor, I
In the shadow region 25, the polycrystalline Si layer 15 and this polycrystalline Si
It consists of a polycrystalline Si layer 12 directly below the layer 15 and has a thickness of 2.0 μm.
The incident light is absorbed by the portion having a thickness of about 100 mL, and is made only of polycrystalline 5ilW12.

O人程度の厚さしか有していない部分では入射光は吸収
されない。
Incident light is not absorbed in a portion having a thickness of only about O.

〔発明の効果〕〔Effect of the invention〕

本発明による光センサでは、応答速度等の電気的特性が
良くしかもモノリシックな集積化が可能であり更にまた
大型化が容易であるので、高性能で且つ大型のイメージ
センサを低コストで提供することができる。
The optical sensor according to the present invention has good electrical characteristics such as response speed, can be monolithically integrated, and can be easily enlarged. Therefore, it is possible to provide a high-performance, large-sized image sensor at low cost. Can be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す側断面図、第2図は一
実施例の製造工程を順次に示す側断面図である。 なお図面に用いた符号において、 11−・・−−−−−−−−−−−−5402基板12
 、 15−−−−−−一多結晶Si層23−・・−・
−・−−−−−−−−−P I N −P D27・・
−−−m−・−・−−−−−CM OSである。
FIG. 1 is a side sectional view showing an embodiment of the present invention, and FIG. 2 is a side sectional view sequentially showing the manufacturing process of the embodiment. In addition, in the symbols used in the drawings, 11-...-----5402 substrate 12
, 15----- polycrystalline Si layer 23--
−・−−−−−−−−P I N -P D27・・
---m-・-・-----CM OS.

Claims (1)

【特許請求の範囲】 光検出素子とこの光検出素子から出力される信号を処理
するための信号処理回路とを有する光センサにおいて、 絶縁物基板上に多結晶半導体層が形成されており、 この多結晶半導体層に前記光検出素子と前記信号処理回
路とが形成されている光センサ。
[Claims] An optical sensor having a photodetecting element and a signal processing circuit for processing a signal output from the photodetecting element, comprising: a polycrystalline semiconductor layer formed on an insulating substrate; An optical sensor in which the photodetecting element and the signal processing circuit are formed in a polycrystalline semiconductor layer.
JP61144265A 1986-06-20 1986-06-20 Photosensor Pending JPS631058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61144265A JPS631058A (en) 1986-06-20 1986-06-20 Photosensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61144265A JPS631058A (en) 1986-06-20 1986-06-20 Photosensor

Publications (1)

Publication Number Publication Date
JPS631058A true JPS631058A (en) 1988-01-06

Family

ID=15358070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61144265A Pending JPS631058A (en) 1986-06-20 1986-06-20 Photosensor

Country Status (1)

Country Link
JP (1) JPS631058A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04329958A (en) * 1990-12-28 1992-11-18 Kawasumi Lab Inc Sterilized wrapping method of medical apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04329958A (en) * 1990-12-28 1992-11-18 Kawasumi Lab Inc Sterilized wrapping method of medical apparatus
JPH0622529B2 (en) * 1990-12-28 1994-03-30 川澄化学工業株式会社 Sterilization packaging method for medical equipment

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