JPS6310554A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To connect A semiconductor integrated circuit to other integrated circuit by setting the difference of the potentials of a set of power sources, supplied to a logic circuit having a short channel field effect transistor to a value that the transistor does not generate a short channel effect to perform a stable high speed operation. CONSTITUTION:A logic circuit to which a set of power source potentials of a combination of potential difference smaller than that of the potential of a set of power sources supplied to an input circuit and an output circuit is supplied is provided. For example, 0V, 5V are supplied as the potential of power sources to an input circuit 1 and an output circuit 3, and the channel lengths of field effect transistors which form the circuits 1, 3 are designed in the same manner as a conventional integrated circuit. 2V, 3V are supplied as the potentials of the power sources to the logic circuit 2, and the channel length of the transistors which form the logic circuit are designed in short channel length to accelerate the operation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit including a logic circuit having complementary field effect transistors as logic components.

[Conventional technology]

Conventionally, all internal circuits of a semiconductor integrated circuit having complementary field effect transistors as logic components are supplied with power from a single power supply at a constant voltage.

3 is a professional diagram of an example of a conventional semiconductor integrated circuit.

This semiconductor integrated circuit includes an input circuit 1. It has a logic circuit 2' and an output circuit 3, and a single power supply voltage of 5 .mu. is applied to all these internal circuits.

FIG. 4 is a circuit diagram showing an example of the logic circuit of FIG. 1.

P channel MO3) transistor Qptt and N channel M
One inverter is configured with the OS transistor Qs++, and similarly (QP12, QN12), (QP13
, QN13) constitute an inverter, and these inverters are connected in cascade in three stages, and a power supply voltage of 5cm is applied to each inverter.

[Problem that the invention seeks to solve]

In recent years, semiconductor integrated circuits have been required to have high speed and high functionality, and to meet this demand, the channel length of field effect transistors has become shorter.

However, as the channel length becomes shorter, a so-called short channel effect appears in the characteristics of field effect transistors.
There is a drawback that operation becomes unstable when operating based on the potential of .

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor S product circuit that has a logic circuit configured using complementary field effect transistors with short channel lengths and operates at high speed and stably.

[Means for solving problems]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having an input circuit, a logic circuit, and an output circuit composed of complementary field effect transistors, in which a potential difference between a pair of power supplies supplied to the input circuit and the output circuit is A logic circuit is provided to which a set of power supply potentials having a small potential difference is supplied.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Input circuit 1. The output circuit 3 has a power supply potential of OV, 5.
V is supplied. The channel lengths of the field effect transistors constituting the input circuit 1 and the output circuit 3 are designed to be the same as those of conventional integrated circuits. The logic circuit 2 is supplied with power supply potentials 2■ and 3■, and the channel length of the field effect transistor constituting this logic circuit is designed to be short in order to increase the speed.

FIG. 2 is a circuit diagram showing an example of the logic circuit shown in FIG. 1.

This logic circuit has three stages of inverters! A circuit connected in series, including P channel Mo5t to transistor Qpz,
QP2. QP3 and N channel MOS transistor QN
1. It is composed of QN21 and QN3. The voltage applied to one inverter, for example, an inverter consisting of QPl and QNI, is 1.sup., and MOS transistors are used in a region where short channel effects do not occur.

〔Effect of the invention〕

As explained above, the present invention sets the potential difference between a pair of power supplies supplied to a logic circuit composed of field effect transistors with short channel lengths to a value such that the field effect transistor does not cause short channel effects. By setting this, stable high-speed operation can be realized, and the input/output circuit can be interconnected with other integrated circuits by using the potential applied to conventional semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the logic circuit shown in FIG. 1, FIG. 3 is a block diagram of an example of a conventional semiconductor integrated circuit, and FIG. 4 is a circuit diagram showing an example of the logic circuit of FIG. 3. FIG. 1...Input circuit, 2.2'...Logic circuit, 3...
Output circuit, 4...input terminal, 5...output terminal, QN
l, QN2゜QN3. QNl, QNl2, QN
13°° N-channel MO3l-transistor, QPl,
QP2. QP3. QpH, QPl2, QPl3
...P channel MO3) transistor.

Claims (1)

[Claims] In a semiconductor integrated circuit having an input circuit, a logic circuit, and an output circuit composed of complementary field effect transistors,
1. A semiconductor integrated circuit comprising a logic circuit to which a set of power supply potentials of a combination having a smaller potential difference than a potential difference between a set of power supply potentials supplied to the input circuit and the output circuit are supplied.