JPS6310554A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6310554A JPS6310554A JP61155570A JP15557086A JPS6310554A JP S6310554 A JPS6310554 A JP S6310554A JP 61155570 A JP61155570 A JP 61155570A JP 15557086 A JP15557086 A JP 15557086A JP S6310554 A JPS6310554 A JP S6310554A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- supplied
- integrated circuit
- logic circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 13
- 230000000295 complement effect Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 8
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に相補型電界効果ト
ランジスタを論理構成素子とする論理回路を含む半導体
集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit including a logic circuit having complementary field effect transistors as logic components.
従来、相補型電界効果トランジスタを論理構成素子とす
る半導体集積回路の内部回路はすべて一定電圧の単一電
源の電力が供給されている。Conventionally, all internal circuits of a semiconductor integrated circuit having complementary field effect transistors as logic components are supplied with power from a single power supply at a constant voltage.
゛第3図は従来の半導体集積回路の一例のプロ・・Iり
図である。3 is a professional diagram of an example of a conventional semiconductor integrated circuit.
この半導体集積回路は、入力回路1.論理回路2′、出
力回路3を有し、これらの内部回路にはすべて5■とい
う単一電源電圧が印加されている。This semiconductor integrated circuit includes an input circuit 1. It has a logic circuit 2' and an output circuit 3, and a single power supply voltage of 5 .mu. is applied to all these internal circuits.
第4図は第1図の論理回路の一例を示す回路図である。FIG. 4 is a circuit diagram showing an example of the logic circuit of FIG. 1.
PチャネルMO3)ランジスタQpttとNチャネルM
OSトランジスタQs++とで一つのインバータを構成
し、同様に(QP12 、 QN12 )、(QP13
、 QN13 )でそれぞれインバータを構成し、こ
れらのインバータが三段縦続接続されて、各インバータ
には5■の電源電圧が印加されている。P channel MO3) transistor Qptt and N channel M
One inverter is configured with the OS transistor Qs++, and similarly (QP12, QN12), (QP13
, QN13) constitute an inverter, and these inverters are connected in cascade in three stages, and a power supply voltage of 5cm is applied to each inverter.
近年、半導体集積回路は、高速、高機能が要求されてお
り、これに対応するため電界効果トランジスタのチャネ
ル長は短かくなっている。In recent years, semiconductor integrated circuits have been required to have high speed and high functionality, and to meet this demand, the channel length of field effect transistors has become shorter.
しかしながら、チャネル長が短かくなると、電界効果ト
ランジスタの特性に、いわゆる短チヤネル効果と呼ばれ
る特性が現れ、従来の半導体集積回路の様に5V、QV
の電位に基いて動作させると動作が不安定になるという
欠点がある。However, as the channel length becomes shorter, a so-called short channel effect appears in the characteristics of field effect transistors.
There is a drawback that operation becomes unstable when operating based on the potential of .
本発明の目的は、チャネル長の短い相補型電界効果トラ
ンジスタを用いて構成された論理回路を有し、高速でし
かも安定な動作をする半導体S積回路を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor S product circuit that has a logic circuit configured using complementary field effect transistors with short channel lengths and operates at high speed and stably.
本発明の半導体集積回路は、相補型電界効果トランジス
タで構成される入力回路と論理回路と出力回路とを有す
る半導体集積回路において、前記入力回路及び出力回路
に供給される電源の一組の電位差より小さい電位差とな
る組合せの一組の電源電位が供給される論理回路を設け
たものである。The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having an input circuit, a logic circuit, and an output circuit composed of complementary field effect transistors, in which a potential difference between a pair of power supplies supplied to the input circuit and the output circuit is A logic circuit is provided to which a set of power supply potentials having a small potential difference is supplied.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
入力回路1.出力回路3には電源の電位とじてOV、5
Vが供給されている。この入力回路1゜出力回路3を構
成している電界効果トランジスタのチャネル長は従来の
集積回路と同じく設計されている。論理回路2には、電
源の電位として2■と3■が供給されており、この論理
回路を構成している電界効果トランジスタのチャネル長
は高速化のためチャネル長を短かく設計している。Input circuit 1. The output circuit 3 has a power supply potential of OV, 5.
V is supplied. The channel lengths of the field effect transistors constituting the input circuit 1 and the output circuit 3 are designed to be the same as those of conventional integrated circuits. The logic circuit 2 is supplied with power supply potentials 2■ and 3■, and the channel length of the field effect transistor constituting this logic circuit is designed to be short in order to increase the speed.
第2図は第1図の論理回路の一例を示す回路図である。FIG. 2 is a circuit diagram showing an example of the logic circuit shown in FIG. 1.
この論理回路は、インバータを三段に!続接続した回路
であって、PチャネルMo5t〜ランジスタQpz、
QP2. QP3とNチャネルMOSトランジスタQN
1. QN21 QN3とで構成されている。一つのイ
ンバータ、例えばQPl、 QNIからなるインバータ
に印加される電圧は1■であり、短チヤネル効果の生じ
ない領域でMOSトランジスタが使用される。This logic circuit has three stages of inverters! A circuit connected in series, including P channel Mo5t to transistor Qpz,
QP2. QP3 and N channel MOS transistor QN
1. It is composed of QN21 and QN3. The voltage applied to one inverter, for example, an inverter consisting of QPl and QNI, is 1.sup., and MOS transistors are used in a region where short channel effects do not occur.
以上説明したように、本発明は、チャネル長の短い電界
効果トランジスタで構成される論理回路に供給する一組
の電源の電位の差を電界効果l・ランジスタが短チヤネ
ル効果を生じないような値に設定することにより、安定
した高速動作が実現でき、且つ入出力回路は従来の半導
体集積回路に適用した電位を使用することにより他の集
積回路との相互接続が可能になるという効果がある。As explained above, the present invention sets the potential difference between a pair of power supplies supplied to a logic circuit composed of field effect transistors with short channel lengths to a value such that the field effect transistor does not cause short channel effects. By setting this, stable high-speed operation can be realized, and the input/output circuit can be interconnected with other integrated circuits by using the potential applied to conventional semiconductor integrated circuits.
第1図は本発明の一実施例を示すブロック図、第2図は
第1図の論理回路の一例を示す回路図、第3図は従来の
半導体集積回路の一例のブロック図、第4図は第3図の
論理回路の一例を示す回路図である。
1・・・入力回路、2.2′・・・論理回路、3・・・
出力回路、4・・・入力端子、5・・・出力端子、QN
l、 QN2゜QN3.QNl、 QNl2 、 QN
13°°NチャネルMO3l−ランジスタ、QPl、
QP2. QP3. QpH,QPl2 、 QPl3
・・・PチャネルMO3)ランジスタ。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the logic circuit shown in FIG. 1, FIG. 3 is a block diagram of an example of a conventional semiconductor integrated circuit, and FIG. 4 is a circuit diagram showing an example of the logic circuit of FIG. 3. FIG. 1...Input circuit, 2.2'...Logic circuit, 3...
Output circuit, 4...input terminal, 5...output terminal, QN
l, QN2゜QN3. QNl, QNl2, QN
13°° N-channel MO3l-transistor, QPl,
QP2. QP3. QpH, QPl2, QPl3
...P channel MO3) transistor.
Claims (1)
理回路と出力回路とを有する半導体集積回路において、
前記入力回路及び出力回路に供給される電源の一組の電
位の電位差より小さい電位差となる組合せの一組の電源
電位が供給される論理回路を具備したことを特徴とする
半導体集積回路。In a semiconductor integrated circuit having an input circuit, a logic circuit, and an output circuit composed of complementary field effect transistors,
1. A semiconductor integrated circuit comprising a logic circuit to which a set of power supply potentials of a combination having a smaller potential difference than a potential difference between a set of power supply potentials supplied to the input circuit and the output circuit are supplied.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61155570A JPS6310554A (en) | 1986-07-01 | 1986-07-01 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61155570A JPS6310554A (en) | 1986-07-01 | 1986-07-01 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6310554A true JPS6310554A (en) | 1988-01-18 |
Family
ID=15608930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61155570A Pending JPS6310554A (en) | 1986-07-01 | 1986-07-01 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6310554A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02146761A (en) * | 1988-11-28 | 1990-06-05 | Nec Corp | Semiconductor integrated circuit |
JPH0343010U (en) * | 1989-09-06 | 1991-04-23 | ||
JPH04151730A (en) * | 1990-10-15 | 1992-05-25 | Mitsubishi Electric Corp | Logic circuit |
JPH04253366A (en) * | 1991-01-29 | 1992-09-09 | Toshiba Corp | Gate array device, input circuit, output circuit, and voltage step down circuit |
-
1986
- 1986-07-01 JP JP61155570A patent/JPS6310554A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02146761A (en) * | 1988-11-28 | 1990-06-05 | Nec Corp | Semiconductor integrated circuit |
JPH0343010U (en) * | 1989-09-06 | 1991-04-23 | ||
JPH04151730A (en) * | 1990-10-15 | 1992-05-25 | Mitsubishi Electric Corp | Logic circuit |
JPH04253366A (en) * | 1991-01-29 | 1992-09-09 | Toshiba Corp | Gate array device, input circuit, output circuit, and voltage step down circuit |
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