JPS63105547A - Data transfer request system - Google Patents
Data transfer request systemInfo
- Publication number
- JPS63105547A JPS63105547A JP61251489A JP25148986A JPS63105547A JP S63105547 A JPS63105547 A JP S63105547A JP 61251489 A JP61251489 A JP 61251489A JP 25148986 A JP25148986 A JP 25148986A JP S63105547 A JPS63105547 A JP S63105547A
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- Prior art keywords
- transmission
- request
- data
- reception
- memory
- Prior art date
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- Granted
Links
- 238000012546 transfer Methods 0.000 title claims description 7
- 230000005540 biological transmission Effects 0.000 claims abstract description 120
- 238000012545 processing Methods 0.000 claims abstract description 56
- 238000004891 communication Methods 0.000 claims abstract description 12
- 230000004044 response Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 14
- 238000000605 extraction Methods 0.000 abstract description 20
- 230000015654 memory Effects 0.000 description 61
- 238000010586 diagram Methods 0.000 description 8
- 239000000284 extract Substances 0.000 description 8
- 238000012544 monitoring process Methods 0.000 description 5
- 238000013075 data extraction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔概要〕
処理装置から伝達される送信データを複数の通信回線に
送出する送信部と、複数の通信回線から到着する受信デ
ータを処理装置に抽出を要求する受信部とを具備する装
置において、送信部が出力する送信データの伝達要求と
、受信部が出力する受信データの抽出要求とを、同一待
行列を経由して処理装置に伝達することにより、処理装
置の簡易化を図る。[Detailed Description of the Invention] [Summary] A transmitting unit that sends out transmission data transmitted from a processing device to a plurality of communication lines, and a receiving unit that requests the processing device to extract received data arriving from the plurality of communication lines. In a device equipped with the above, the processing device can be simplified by transmitting a transmission data transmission request output by the transmission section and a reception data extraction request outputted by the reception section to the processing device via the same queue. We aim to make this possible.
本発明は、通信回線に対してハイレベルデータリンク制
御手順等によりデータを送受信する装置との間で、デー
タを転送する処理装置の簡易化を図るデータ転送要求方
式に関する。The present invention relates to a data transfer request method for simplifying a processing device that transfers data between a device that transmits and receives data to and from a communication line using a high-level data link control procedure or the like.
第３図は従来あるハイレベルデータリンク制御装置の一
例を示す図であり、第４図は第３図における送信データ
と伝達要求との関係を説明する図である。FIG. 3 is a diagram showing an example of a conventional high-level data link control device, and FIG. 4 is a diagram illustrating the relationship between transmission data and transmission requests in FIG. 3.
第３図および第４図において、送信回線５−１乃至５−
ｎに対応じて設けられている送信データメモリ１−１
乃至Ｌ−ｎは、それぞれ先入れ先出しメモリから構成さ
れ、図示されぬ処理装置から伝達される各送信回綿５−
１乃至５−ｎに送出される送信データｓｄを格納する。In FIGS. 3 and 4, transmission lines 5-1 to 5-
Transmission data memory 1-1 provided corresponding to n
. . . L-n are respectively constituted by first-in, first-out memories, and each transmission time 5-n is transmitted from a processing device (not shown).
Stores transmission data sd sent to nodes 1 to 5-n.
送信多重処理回路２は、チャネルカウンタ６から指定さ
れる各送信回線５−１乃至５−ｎに割当てられた各時間
領域に、送信データメモリ１−１乃至１−ｎに格納され
ている送信データｓｄを順次先着順に抽出し、例えば誤
り制御処理、或いはフラグパターンの付加等のハイレベ
ルデークリンク制？ＩＯ手順に基づく処理を施して一旦
ラインメモリ３の各送信回線５−１乃至５−ｎ対応領域
に格納した後、分離回路４を介して対応する送信回線５
−１乃至５−ｎに送出する。The transmission multiplexing circuit 2 transmits the transmission data stored in the transmission data memories 1-1 to 1-n in each time domain assigned to each transmission line 5-1 to 5-n specified by the channel counter 6. Is there a high-level data link system in which sds are sequentially extracted on a first-come, first-served basis, and error control processing is performed or a flag pattern is added? After performing processing based on the IO procedure and temporarily storing it in the area corresponding to each transmission line 5-1 to 5-n of the line memory 3, the corresponding transmission line 5 is stored via the separation circuit 4.
-1 to 5-n.
かかる過程で、゛送信多重処理回路２が送信データメモ
リ１−ｉ（ｉは１乃至ｎの何れか、以下同様）に格納さ
れている送信データｓｄを抽出し終わると、送信多重処
理回路２は前記処理装置に対し、該当する送信データメ
モリ１−ｉに送信データｓｄを伝達することを要求する
伝達要求ｓｑｉを出力し、先入れ先出しメモリから構成
される送信要求メモリ１２に格納する。In this process, ``When the transmission multiple processing circuit 2 finishes extracting the transmission data sd stored in the transmission data memory 1-i (i is any one from 1 to n, the same applies hereinafter), the transmission multiple processing circuit 2 A transmission request sqi requesting the processing device to transmit the transmission data sd to the corresponding transmission data memory 1-i is output, and is stored in the transmission request memory 12 constituted by a first-in, first-out memory.
前記処理装置は、送信要求メモリ１２に格納されている
伝達要求ｓｑｔを先着順に抽出し、該当する送信データ
メモリｌ−ｉに送信データｓｄを、第４図に示される過
程で格納する。The processing device extracts the transmission requests sqt stored in the transmission request memory 12 on a first-come, first-served basis, and stores the transmission data sd in the corresponding transmission data memory l-i in the process shown in FIG.
第４図においては、送信データメモリｌ−ｉが、それぞ
れ送信データｓｄを格納し得る４個のメモリブロック１
ａ乃至１ｄから構成されているものとする。In FIG. 4, the transmission data memory l-i is divided into four memory blocks 1 each capable of storing transmission data sd.
It is assumed that it is composed of a to 1d.
ハイレベルデータリンク制御装置が稼動状態に無い場合
には、送信データメモリｌ−ｉの各メモリブロック１ａ
乃至１ｄには送信データｓｄが格納されず、また送信要
求メモリ１２にも伝達要求ｓｑｉが全く格納されていな
い（第４図■）。If the high-level data link control device is not in operation, each memory block 1a of the transmission data memory l-i
The transmission data sd is not stored in 1d to 1d, and the transmission request sqi is not stored at all in the transmission request memory 12 ((2) in FIG. 4).
かかる状態でハイレベルデータリンク制御装置が稼動を
開始すると、送信多重処理回路２は送信データメモリ１
−ｉの各メモリブロック１ａ乃至１ｄに送信データｓｄ
を格納する伝達要求５ｑｉｌ乃至５ｑｉ４を送信要求メ
モリ１２に格納する（第４図■）。When the high-level data link control device starts operating in such a state, the transmission multiplexing circuit 2 transfers the transmission data memory 1
- Send data sd to each memory block 1a to 1d of i.
The transmission requests 5qil to 5qi4 storing the above are stored in the transmission request memory 12 (FIG. 4).
前記処理装置は、送信要求メモリ１２から伝達要求５ｑ
ｉｌ乃至５ｑｉ４を先着順に抽出し、送信データメモリ
ｌ−ｉの各メモリブ［１ツク１ａ乃至１ｄに、順次送信
データｓｄを格納する（第４図■）。The processing device receives the transmission request 5q from the transmission request memory 12.
il to 5qi4 are extracted on a first-come, first-served basis, and the transmission data sd is sequentially stored in memory blocks 1a to 1d of the transmission data memory l-i (FIG. 4).
送信多重処理回路２は、送信データメモリ１−１の各メ
モリブロック１ａ乃至１ｄに格納されている各送信デー
タｓｄを先着ｌ頃に抽出し、前述の如き処理を施した後
、対応する送信回線５−ｉに送出し、送信済みのメモリ
ブロック１ａ乃至１ｄに送信データｓｄを格納させる為
の伝達要求５ｑｉ５乃至５ｑｉ８を、順次送信要求メモ
リ１２に格納する（第４図■）。The transmission multiplexing circuit 2 extracts each transmission data sd stored in each memory block 1a to 1d of the transmission data memory 1-1 on a first-come-first-served basis, performs the above-mentioned processing, and then extracts each transmission data sd stored in each memory block 1a to 1d of the transmission data memory 1-1. Transmission requests 5qi5 to 5qi8 for storing transmission data sd in transmitted memory blocks 1a to 1d are sequentially stored in transmission request memory 12 (FIG. 4).
一方受信多重処理回路９は、複数の受信口′ａ７−１乃
至７−ｎから到着する受信データを、チャネルカウンタ
６から指定される各受信回線７−１乃至７−ｎに割当て
られた各時間領域に、多重回路８を介して順次受信し、
例えばフラグパターンの除去、或いは誤り制御処理等の
ハイレベルデータリンク制御手順に基づく処理を施して
一旦うインメモリーＯの各受信回線７−１乃至７−ｎ対
応領域に格納した後、順次抽出して受信データメモリ１
１に格納すると共に、各受信データｒｄの受信回線７−
ｉを示す識別情報を含む抽出要求ｒｑｉを出力し、受信
要求メモリー３に格納する。On the other hand, the reception multiplexing circuit 9 processes the reception data arriving from the plurality of reception ports 'a7-1 to 7-n at each time assigned to each reception line 7-1 to 7-n specified by the channel counter 6. sequentially received in the area via the multiplex circuit 8,
For example, after performing processing based on high-level data link control procedures such as flag pattern removal or error control processing, the data is stored in the areas corresponding to each receiving line 7-1 to 7-n in the in-memory O, and then sequentially extracted. Receive data memory 1
1, and the receiving line 7- of each received data rd.
An extraction request rqi including identification information indicating i is output and stored in the reception request memory 3.
前記処理装置は、受信要求メモリー３に格納されている
抽出要求ｒｑｉを先着順に抽出し、受信データメモリー
１から受信データｒｄを抽出する。The processing device extracts the extraction requests rqi stored in the reception request memory 3 on a first-come, first-served basis, and extracts the reception data rd from the reception data memory 1.
以上の説明から明らかな如く、従来あるハ・イレベルデ
ータリンク制御装置においては、送信多重処理回路２が
出力する伝達要求・計は送信要求メモリ１２に格納され
、受信多重処理回路９が出力する抽出要求ｒｑ′は受信
要求メモリー３に格納されていた。As is clear from the above explanation, in the conventional high-level data link control device, the transmission request/total outputted by the transmission multiplexing circuit 2 is stored in the transmission request memory 12, and the transmission request/total outputted by the receiving multiplexing circuit 9 is outputted. The extraction request rq' was stored in the reception request memory 3.
従って前記処理装置は、送信要求メモリ１２と受信要求
メモリ１３とを別個に監視し、各々に格納されている伝
達要求ｓｑｉと抽出要求ｒｑｉとの処理順序を所定の優
先順位別に従って定め、対応する処理を実行する必要が
あった。Therefore, the processing device separately monitors the transmission request memory 12 and the reception request memory 13, determines the processing order of the transmission request sqi and the extraction request rqi stored in each according to a predetermined priority order, and responds accordingly. Processing needed to be done.
第１図は本発明の原理を示す図である。 FIG. 1 is a diagram showing the principle of the present invention.
第１図において、１００は処理装置、２００は通信回線
、３００は処理装置１００から要求に応じて伝達される
送信データを多重処理して複数の通信回線２００に送出
する送信部、４００は複数の通信回線２００から到着す
る受信データを多重処理して処理装置１００に抽出を要
求する受信部である。In FIG. 1, 100 is a processing device, 200 is a communication line, 300 is a transmitting unit that multiplexes transmission data transmitted in response to a request from the processing device 100 and sent to a plurality of communication lines 200, and 400 is a plurality of communication lines 200. This is a receiving unit that multi-processes received data arriving from the communication line 200 and requests extraction to the processing device 100.
５００は、本発明により設けられた要求伝達手段である
。500 is a request transmission means provided according to the present invention.
要求伝達手段５００は、送信部３００が出力する送信デ
ータの伝達要求と、受信部４００が出力する受信データ
の抽出要求とを、同一待行列を経由して処理装置１００
に伝達する。The request transmitting unit 500 transmits a transmission data transmission request outputted by the transmitting unit 300 and a received data extraction request outputted by the receiving unit 400 to the processing device 100 via the same queue.
to communicate.
従って処理装置１００は共通の要求伝達手段５００を監
視するのみで、送信部３００に対する送信データの伝達
要求と、受信部４００に対する受信データの抽出要求と
を、同一待行列に対する先着順で抽出可能となり、伝達
要求および抽出要求の監視点も一元化され、また伝達要
求と抽出要求との処理順序を定める必要も無くなる為、
当該処理装置１００の処理能力が簡易化され、処理負荷
も軽減される。Therefore, by simply monitoring the common request transmission means 500, the processing device 100 can extract transmission data transmission requests to the transmission unit 300 and reception data extraction requests to the reception unit 400 on a first-come, first-served basis for the same queue. , the monitoring points for transfer requests and extraction requests are also unified, and there is no need to determine the processing order for transfer requests and extraction requests.
The processing capacity of the processing device 100 is simplified and the processing load is also reduced.
以下、本発明の一実施例を図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例によるハイレベルデータリン
ク制御装置を示す図である。なお、企図を通じて同一符
号は同一対象物を示す。FIG. 2 is a diagram showing a high-level data link control device according to an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan.
第２図においては、処理装置１００は図示されず、通信
回線２００として送信回線５−１乃至５−ｎと受信回線
７−１乃至７−ｎとが示され、送信部３００として送信
データメモリ１−１乃至１−ｎ、送信多重処理回路２、
ラインメモリ３および分離回路４が示され、受信部４０
０として多重回路８、受信多重処理回路９、ラインメモ
リ１０および受信データメモリ１１が示される。なおチ
ャネルカウンタ６は送信部３００および受信部４００に
共通の装置である。In FIG. 2, the processing device 100 is not shown, and the transmission lines 5-1 to 5-n and the reception lines 7-1 to 7-n are shown as the communication line 200, and the transmission data memory 1 is shown as the transmission section 300. -1 to 1-n, transmission multiplexing circuit 2;
A line memory 3 and a separation circuit 4 are shown, and a receiving section 40
0, a multiplex circuit 8, a reception multiplex processing circuit 9, a line memory 10, and a reception data memory 11 are shown. Note that the channel counter 6 is a device common to the transmitter 300 and the receiver 400.
更に第２図においては、先入れ先出しメモリから構成さ
れる共通要求メモリ１４が、要求伝達手段５００として
設けられている。Further, in FIG. 2, a common request memory 14 consisting of a first-in, first-out memory is provided as a request transmission means 500.
第２図において、図示されぬ処理装置から送信データメ
モリ１−１乃至１−ｎに格納される送信データｓｄは、
前述と同様の過程で、各送信回線５−１乃至５−ｎに送
出される。In FIG. 2, transmission data sd stored in transmission data memories 1-1 to 1-n from a processing device (not shown) is as follows.
The signal is sent to each transmission line 5-1 to 5-n in the same process as described above.
かかる過程で、送信多重処理回路２が送信データメモリ
ｌ−ｉに格納されている送信データｓｄを抽出し終わる
と、送信多重処理回路２は前記処理装置に対し、該当す
る送信データメモリｌ−ｉに送信データｓｄを伝達する
ことを要求する伝達要求ｓｑ＋を、共通要求メモリ１４
に格納する。In this process, when the transmission multiple processing circuit 2 finishes extracting the transmission data sd stored in the transmission data memory l-i, the transmission multiple processing circuit 2 instructs the processing device to extract the transmission data sd stored in the transmission data memory l-i. A transmission request sq+ requesting to transmit transmission data sd to the common request memory 14
Store in.
一方受信多重処理回路９は、複数の受信回線７−１乃至
７−ｎから到着する受信データを、前述と同様の過程で
受信データメモリ１１に格納すると共に、各受信データ
ｒｄの受信回線７−４を示す識別情報を含む抽出要求ｒ
ｑｉを、共通要求メモリ１４に格納する。On the other hand, the reception multiplexing circuit 9 stores the reception data arriving from the plurality of reception lines 7-1 to 7-n in the reception data memory 11 in the same process as described above, and also stores the reception data arriving from the reception lines 7-n for each reception data rd. Extraction request r including identification information indicating 4
qi is stored in the common request memory 14.
従って共通要求メモリ１４には、送信多重処理回路２が
出力する伝達要求ｓｑｉと、受信多重処理回路９が出力
する抽出要求ｒｑｉとが、先着順に格納される。Therefore, the common request memory 14 stores the transmission request sqi output from the transmission multiplexing circuit 2 and the extraction request rqi outputting from the receiving multiplexing circuit 9 on a first-come, first-served basis.
前記処理装置は、共通要求メモリ１４に格納されている
伝達要求ｓｑｉおよび抽出要求ｒｑｉを先着順に抽出し
、伝達要求ｓｑｉが抽出された場合には該当する送信デ
ータメモリｌ−ｉに送信データｓｄを格納し、また抽出
要求ｒｑｉが抽出された場合には受信データメモリ１１
から受信データｒｄを抽出する。The processing device extracts the transmission request sqi and extraction request rqi stored in the common request memory 14 on a first-come-first-served basis, and when the transmission request sqi is extracted, sends the transmission data sd to the corresponding transmission data memory l-i. and when the extraction request rqi is extracted, the reception data memory 11
The received data rd is extracted from.
以上の説明から明らかな如く、本実施例によれば、送信
多重処理回路２が出力する伝達要求ｓｑｉと、受信多重
処理回路９が出力する抽出要求ｒｑｉとが、同一の共通
要求メモリ１４に先着順に格納されている為、前記処理
装置は、共通要求メモリ１４の格納内容を監視するのみ
で、伝達要求ｓｑｉおよび抽出要求ｒｑｉが共通要求メ
モリ１４により定まる順序で抽出可能となり、監視対象
も一元化され、伝達要求ｓｑｉと抽出要求ｒｑｉとの処
理順序を定める必要も無くなる。As is clear from the above description, according to the present embodiment, the transmission request sqi outputted by the transmission multiplexing circuit 2 and the extraction request rqi outputted from the receiving multiplexing circuit 9 arrive at the same common request memory 14 first. Since they are stored sequentially, the processing device can extract the transmission request sqi and the extraction request rqi in the order determined by the common request memory 14 by simply monitoring the contents stored in the common request memory 14, and the monitoring targets are also unified. , there is no need to determine the processing order of the transmission request sqi and the extraction request rqi.
なお、第２図はあく迄本発明の一実施例に過ぎず、例え
ば本発明の対象となる装置はハイレベルデータリンク制
御装置に限定されることは無く、他に幾多の変形が考慮
されるが、何れの場合にも本発明の効果は変わらない。It should be noted that FIG. 2 is merely one embodiment of the present invention; for example, the device to which the present invention is applied is not limited to a high-level data link control device, and many other modifications may be considered. However, the effects of the present invention remain the same in either case.
以上、本発明によれば、前記装置において、処理装置は
共通の要求伝達手段を監視するのみで、送信部に対する
送信データの伝達要求と、受信部からの受信データの抽
出要求とを、同一待行列に対する先着順で抽出可能とな
り、伝達要求および抽出要求の監視点も一元化され、ま
た伝達要求と抽出要求との処理順序を定める必要も無く
なる為、当該処理装置の処理能力が筒易化され、処理負
荷も軽減される。As described above, according to the present invention, in the device, the processing device only monitors the common request transmission means, and sends a transmission data transmission request to the transmission unit and a reception data extraction request from the reception unit in the same wait. It becomes possible to extract requests on a first-come, first-served basis in the matrix, the monitoring points for transmission requests and extraction requests are unified, and there is no need to determine the processing order for transmission requests and extraction requests, so the processing capacity of the processing device is simplified. Processing load is also reduced.
第１図は本発明の原理を示す図、第２図は本発明の一実
施例によるハイレベルデータリンク制御装置を示す図、
第３図は従来あるハイレベルデータリンク制御装置の一
例を示す図、第４図は第３図における送信データと伝達
要求との関係を説明する図である。
図において、１−１乃至１−ｎは送信データメモリ、２
は送信多重処理回路、３はラインメモリ、４は分離回路
、５−１乃至５−ｎは送信回線、６はチャネルカウンタ
、７１−１乃至７−ｎは受信回線、８は多重回路、９は
受信多重処理回路、１゜はラインメモリ、１１は受信デ
ータメモリ、１２は送信要求メモリ、１３は受信要求メ
モリ、１４は共通要求メモリ、１００は処理装置、２０
０は通信回線、３００は送信部、４００は受信部、５０
０は要求伝達手段、を示す。FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a high-level data link control device according to an embodiment of the present invention,
FIG. 3 is a diagram showing an example of a conventional high-level data link control device, and FIG. 4 is a diagram explaining the relationship between transmission data and transmission requests in FIG. 3. In the figure, 1-1 to 1-n are transmission data memories, 2
3 is a line memory, 4 is a separation circuit, 5-1 to 5-n are transmission lines, 6 is a channel counter, 71-1 to 7-n are reception lines, 8 is a multiplex circuit, and 9 is a transmission multiplexing circuit. Reception multiple processing circuit, 1° line memory, 11 reception data memory, 12 transmission request memory, 13 reception request memory, 14 common request memory, 100 processing device, 20
0 is a communication line, 300 is a transmitter, 400 is a receiver, 50
0 indicates a request transmission means.
Claims (1)
ータを多重処理し、複数の通信回線（２００）に送出す
る送信部（３００）と、 前記複数の通信回線（２００）から到着する受信データ
を多重処理し、前記処理装置（１００）に抽出を要求す
る受信部（４００）とを具備する装置において、 前記送信部（３００）が出力する前記送信データの伝達
要求と、前記受信部（４００）が出力する前記受信デー
タの抽出要求とを、同一待行列を経由して前記処理装置
（１００）に伝達する要求伝達手段（５００）を設ける
ことを特徴とするデータ転送要求方式。[Scope of Claims] A transmitting unit (300) that multi-processes transmission data transmitted in response to a request from a processing device (100) and transmits the data to a plurality of communication lines (200); ), the apparatus includes a receiving unit (400) that multi-processes received data arriving from a source and requests the processing device (100) to extract the transmitted data, the transmission request being output from the transmitting unit (300); , a data transfer characterized in that a request transmitting means (500) is provided for transmitting a request for extracting the received data outputted by the receiving section (400) to the processing device (100) via the same queue. Request method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61251489A JPS63105547A (en) | 1986-10-22 | 1986-10-22 | Data transfer request system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61251489A JPS63105547A (en) | 1986-10-22 | 1986-10-22 | Data transfer request system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63105547A true JPS63105547A (en) | 1988-05-10 |
| JPH0515337B2 JPH0515337B2 (en) | 1993-03-01 |
Family
ID=17223562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61251489A Granted JPS63105547A (en) | 1986-10-22 | 1986-10-22 | Data transfer request system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63105547A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02182062A (en) * | 1989-01-09 | 1990-07-16 | Hitachi Ltd | Communication control system and communication adaptor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5199424A (en) * | 1975-02-28 | 1976-09-02 | Oki Electric Ind Co Ltd | |
| JPS59109943A (en) * | 1982-12-15 | 1984-06-25 | Hitachi Ltd | Circuit processing controlling system of communication control device |
-
1986
- 1986-10-22 JP JP61251489A patent/JPS63105547A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5199424A (en) * | 1975-02-28 | 1976-09-02 | Oki Electric Ind Co Ltd | |
| JPS59109943A (en) * | 1982-12-15 | 1984-06-25 | Hitachi Ltd | Circuit processing controlling system of communication control device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02182062A (en) * | 1989-01-09 | 1990-07-16 | Hitachi Ltd | Communication control system and communication adaptor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0515337B2 (en) | 1993-03-01 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |