JPS63104586A - Decoding device for block coded picture signal - Google Patents

Abstract

PURPOSE:To remove all block warps by setting detecting windows for two samples and detecting the presence and absence of the block warps at every detecting window. CONSTITUTION:A vertical block warp detection circuit 5V detects the presence and absence of V direction block warps. The windows for two samples Wi-1 are set at every four samples of a boundary data sequence in a block B1{ai} (i=1-8) and the boundary data sequence in a block B2{bi} (i=1-8), both of which are positioned with a vertical direction block boundary 31V between. If conditions that differential values D1i-1(=ai-1-ai), D2i-1(=bi-1-i), D3i-1(=1 ai-1-bi-1) are equivalent to (D1i-1=D2i-1 0 and 0<D3i-1<=DF, DF: threshold) hold, the V direction warps are judged to be occurring between ai-1 and bi-1, and between ai and bi. Then the windows for two samples are sequentially shifted and the V direction warps are detected. Thus, all the block warps are securely removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to decoding 8 of a block-encoded image signal, which compresses the amount of transmitted data of a digital image signal for each block formed by subdividing one screen.

[Summary of the invention]

In this invention, from the output data from the decoding circuit that decodes the block code, the first sample Mimi 1 + the second sample air, the third sample bi-1 + the fourth sample bi, which are adjacent across the block boundary, are obtained. and from these samples, Dit-+ (= a t-+
al )+D2z−+(= b t−+ −
bi )+D 3 +-+(-l a t-+ -b
= −1l ) is formed, and (Dli−
, =Dz=-+ =O big 0< D 3 t, I ≦D
When the conditions (F, DF: L threshold) are satisfied, it is detected that block distortion has occurred, and the block distortion is removed by a smoothing circuit.

[Conventional technology]

As a highly efficient encoding method for digital image signals, an encoding method is known in which one screen is divided into a large number of blocks and data of a compressed number of bits is transmitted in place of the data of each block. For example, an encoding method is known in which the average value and standard deviation of each block are transmitted. The applicant is
As described in Japanese Patent Application No. 59-266407, a television screen is divided into many blocks,
The dynamic range of each block is divided into a number of level ranges determined by a number of bits smaller than the original number of quantization bits, and a code signal is formed that corresponds to the level range to which the pixel data from which the minimum value in the block has been removed belongs. An efficiency coding device is proposed. Also, patent application No. 59-26986
In the specification of No. 6, a high-efficiency encoding device is proposed that varies the bit length of a code signal in accordance with the dynamic range.

High-efficiency encoding (A
It is abbreviated as DRC. ) is compression in the level direction, so compared to DPCM, subsampling, etc., problems such as error propagation and aliasing distortion do not occur during decoding, and the transient response in the restored image can be improved. Also, variable length encoding is
Compared to fixed length encoding, it has the advantage of being able to obtain a higher compression rate without degrading the quality of the restored image.

FIG. 12A explains variable length ADRC, and represents the video signals and code signals of a plurality of, for example, five consecutive blocks B1-85, one-dimensionally (for example, a common line between blocks) for simplicity. ing. In FIG. 12A, the solid line shows the waveform of the actual video signal, the dashed line shows the minimum value MIN of each block, and the broken line shows the maximum value MAX of each block. The sample after removing the minimum value MIN is converted into a 0.1, 2.3 or 4 bit code signal DT according to the dynamic range DR expressed as (MAX-MIN=DR). In Figure 12A, (B
L: 2 bits I-, B2: 1 bits.

B3: 4 bits, B4: O bits, B5: 3 bits) and the number of bits of the code signal DT are assigned.

If the number of pixels in the horizontal direction of one block is, for example, 4, then on the receiving side, the code signal DT is converted to a representative level, and the minimum value MIN is added to this representative level to produce a restored video as shown in FIG. 12B. I get a signal. In block B4, where the dynamic range DR is extremely small, the code signal DT is not transmitted, and the maximum value MAX and minimum value MIN
'A (MAX +M
The average value represented by I N ) is replaced for all data in the block.

(Problems to be Solved by the Invention) In the above-mentioned variable length ADRC, when there are successive blocks with a small dynamic range DR and different average values, so-called blocks where a mosaic pattern of block sizes can be seen in the restored image. There was a problem that distortion occurred.

Further, as shown in FIG. 13, the block B2 and the blocks B1 and B3 that are adjacent to the upper and right sides of the block B2, respectively.
Block distortion occurs even in a pattern in which blocks B1, B2 and B3 have approximately the same luminance level, and only block B2 has a black line passing through it whose luminance level is significantly different from this luminance level. Such patterns are often seen on weather maps that include isobars. That is, block B2 has a larger dynamic range DR than other blocks B1 and B3, and the number of bits allocated to block B2 is greater than the number of bits allocated to other blocks B1 and B3. Therefore, the difference in quantization level becomes large in the flat portion, and block distortion occurs between blocks B1 and B2 and between blocks B2 and B3, as shown by the arrows.

Furthermore, as shown in Fig. 14, in a pattern where regions of different levels extending diagonally in parallel span multiple blocks, the maximum and minimum values of each block are Because of the difference, multiple block distortions appear on the block boundaries as shown by arrows.

An object of the present invention is to provide a block coding decoding device that can remove all block distortion caused by the causes described above. Another object of the present invention is to provide a decoding device for block-encoded image signals that prevents deterioration such as blurring of objects by removing block distortion.

[Means for solving problems]

In this invention, in a decoding device for a block-encoded image signal that compresses the transmission data amount of a digital image signal for each block formed by subdividing one screen, there is provided a decoding circuit for decoding the block encoding, and a decoding circuit for decoding the block encoding. A circuit separates the first sample ai-1+second sample mi1+third sample bi-1n fourth sample bi adjacent across the block boundary, and the difference value D11- 1(=ai−+ −ai LD2t−+(−
b! −+ bt LD 3 =−+(= I a
t-t b +-+ I) is (Dli-+-D2mu+"O and 0 < D 3 t-t≦DF, DFjL
The block distortion detection circuit detects that block distortion occurs at a block boundary when a condition (threshold value) is satisfied, and a smoothing circuit for removing block distortion is provided.

[Effect]

Four samples a! adjacent across the block boundary! -1
ra! + b! -1+b(, the difference value DI+-,, D2 . between adjacent samples every 2 samples.
-3 is required. A difference value of approximately O between adjacent samples means a flat image pattern.

Further, if the difference value D3+-+ between adjacent blocks is larger than O and less than or equal to the threshold value DF, it is determined that block distortion has occurred between the adjacent blocks. By detecting such block distortion, it is possible to reliably detect block distortion in a pattern such as a black line in a flat background, such as an image of isobars on a weather map. Since block distortion can be detected more reliably, block distortion can also be reliably removed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description is given in the following order.

a. Overall configuration and block distortion removal processing; Detection of block distortion; C; Smoothing of block distortion and detection of object portion; d; Specific configuration of one embodiment; e; Modified example a; Overall configuration and block distortion. Removal processing operation FIG. 1 is a conceptual block diagram of an embodiment of the present invention, in which received data is supplied to an input terminal indicated by 1, and ADRC decoder 2
supplied to The ADRC decoder 2 is a variable length ADRC
Perform decryption.

The received data contains dynamic range information (
DR, MAX, or MIN) and a code signal DT for each pixel in the block. In this embodiment, as shown in FIG. 2, one block consists of (4 lines x 8 pixels), and there are 32 pixels in one block. 0 for each of the 32 pixels of one block,
Either 1.2.3 or 4 bits are assigned. The ADRC decoder 2 is constituted by a ROM, and converts each code signal DT in the received data into a restored level.

Decoded data from ADRC decoder 2 is supplied to block decomposition circuit 3. The block decomposition circuit 3 converts the decoded data in the block order into data in the same order as in television scanning. The data from the block decomposition circuit 3 is enclosed by a dashed line and supplied to the block distortion removal circuit 4. The block distortion removal circuit 4 has a configuration in which a vertical block distortion processing section 4v and a horizontal block distortion processing section 4H are connected in series.

The data from the block decomposition circuit 3 is sent to the vertical block distortion detection circuit 5V of the vertical block distortion processing section 4v.

The output signal of the smoothing circuit 7■ and the original signal, which are supplied to the object part detection circuit 6v and the smoothing circuit 7v, are connected to the selection circuit 8v.
supplied to The selection circuit 8■ is the object part detection circuit 6■
It is controlled by the output signal of the selection circuit 8
It is abbreviated as ) yields a direction-selective smoothed output. This V direction selective smoothing output and the original signal are supplied to the selection circuit 9. The selection circuit 9v is controlled by the detection signal of the vertical block distortion detection circuit 5v, and when block distortion in the {circle around (2)} direction is detected, the selective smoothing output in the {circle around (}) direction is selected by the selection circuit 9■.

0 selection circuit 8 in which the output signal of the selection circuit 9V is supplied to the smoothing circuit 7H of the horizontal block distortion processing section 4H, one input terminal of the selection circuit 8H, and one input terminal of the selection circuit 9H.
H is controlled by the detection signal from the object portion detection circuit 6H, and the selection circuit 9H is controlled by the detection signal from the horizontal block distortion detection circuit 5H. The horizontal block distortion detection circuit 5H and the object part detection circuit 6H receive a horizontal (abbreviated as H) direction selective smoothed output from the 0 selection circuit 8H to which the original signal from the block decomposition circuit 3 is supplied. H
The direction selective smoothing output and signal from the selection circuit 9V is supplied to the selection circuit 9H. Output terminal 1 from selection circuit 9H
0, the final block distortion removal processing output is obtained.

FIG. 3 is a flowchart of distortion removal processing in this embodiment. First, in the object part detection circuit 6V, an object part in the (2) direction is detected (step 11), and it is checked whether the input signal is an object part (step 12). When the input signal is an object part, the original signal is output from the selection circuit 8v (step 13), and when it is not an object part, the original signal is output from the selection circuit 8v (step 13).
The output signal of the smoothing filtering (step 14) performed by the smoothing circuit 7v is selected by the selection circuit 8■. Therefore, a V direction selective smoothing signal is output from the selection circuit 8 (step 15).

In the vertical block distortion detection circuit 5v, it is determined whether there is block distortion in the ■ direction (step 16), and the presence or absence of block distortion in the ■ direction is checked (step 17).

■When there is no directional block distortion, the original signal is the selection circuit 9
(Step 18), and if there is block distortion in the V direction, the selective smoothing signal output in the ■ direction from the selection circuit 8V (Step 19) is selected. Therefore, the selection circuit 9-2 outputs the block distortion removal signal in the direction (2) (step 20).

Next, in the object part detection circuit 6H, the original signal is
A direction object portion is detected (step 21), and it is checked whether it is an H direction object portion (step 22). In the smoothing circuit 7H, smoothing filtering is performed on the direction amount processed signal (step 24). The selection circuit 8H selects the directional quantity processed signal (2) in the case of an object part, and selects the output signal of the smoothing circuit 7H in the case of a non-object part. Therefore, an H direction selective smoothing signal is obtained from the selection circuit 8H (step 25).

The horizontal block distortion detection circuit 5H detects H-direction block distortion and checks the presence or absence of H-direction block distortion in the original signal (steps 26 and 27).

When there is block distortion in the H direction, an H direction selective smoothing signal is output from the selection circuit 9H (step 29), and when there is no block distortion in the H direction, a directional amount processed signal is output from the selection circuit 9H (step 29). 28), Therefore, an output signal from which block distortion in both the ■ direction and the H direction is removed is obtained at the output terminal IO (step 30).

Detection of bi block distortion The detection of block distortion performed by the vertical block distortion detection circuit 51 and the horizontal block distortion detection circuit 5H will be described. As shown in FIG. 4, four blocks B1. B2.
B3. Considering the set B4, horizontal block boundary 3
1H and the vertical block boundary 31V,
Since block distortion occurs, vertical block distortion is detected between pixels indicated by ・ and Δ and between pixels indicated by ○ and ×, and horizontal block distortion is detected between pixels indicated by ・ and O and between pixels indicated by △ and ×. is detected. In addition, the smoothing process is
This is done using a plurality of pixels near each of the block boundaries 31V and 31H.

As shown in FIG. 5A, the boundary data series (ai
) (i-1, 2, 3, . . . 8) and the boundary data series (bi) (1-1, 2, 3, . . . 8) of block B2. As shown in FIG. 5B, ai−+ 1 ai + bi−+ l b
Set a window Wt-+ of 2 samples for every 4 samples of l,
Calculate the difference value below.

Dli−+”ai−+ai D2t−+=b 5−, −bi− D 3+−+ −1ai−+ bi−+ lWhen the above difference value satisfies the following conditions, al−2 and 51
It is determined that V-direction block distortion is occurring between ai and bi.

Dli-+"D2□-1#O and Q < 03!-1
≦DF (Threshold 4fi of level difference between DF Niblocks) 2
The sample windows are sequentially shifted as shown in FIG. 5, and V-direction block distortion is detected for all samples at the block boundaries. ■Professional at direction block boundary 31V
Block distortion at the H-direction block boundary 31H is detected in the same manner as the detection of block distortion. The reason why the threshold value DF is set under the conditions for detecting the presence or absence of block distortion is to prevent a true mosaic pattern from being detected as block distortion.

As mentioned above, according to the block distortion detection method performed on a sample-by-sample basis, distortion caused by patterns with black lines on a flat surface, such as on a weather map, or patterns with multiple diagonal stripes of different levels can be detected. can be reliably detected.

C. Smoothing of Block Distortion and Detection of Object Portion In the smoothing circuits 7v and 7H, smoothing processing is performed in the V direction and the H direction, respectively, by digital low-pass filters. This low-pass filter has a configuration in which a constant coefficient is set according to the sample position from the block boundary, and smoothing is performed using samples near the boundary. It is possible to use a configuration that replaces the data with a moving average of 4 sample widths before and after the data center. In the case of the latter low-pass filter using a moving average,
Since the image may be blurred, when the presence of an object is detected by the object portion detection circuits 6v and 6H, original signals are output from the selection circuits 8v and 8H, respectively, instead of the smoothed output.

FIG. 6 shows data when the l block is viewed in one-dimensional direction as an analog waveform, and Bs is the block size. In FIG. 6, block distortion of the mosaic pattern occurs, and the data changes stepwise. FIG. 6A shows the data when there is an object in the mosaic pattern, while FIG. 6B shows the data when there is no object.

In FIG. 6B, the dashed line is smoothed data using a moving average. This smoothed data and the original data of the object part are switched according to the detection signals from the object part detection circuits 6V and 6H, and the selection circuits 8V and 8H output a selective smoothing signal as shown in FIG. 6C. be done. As shown in FIG. 7, the smoothing process is performed on half-block samples (2 samples in the V direction and 4 samples in the H direction) located on both sides of the block boundary.

Detection of an object portion performed by the object portion detection circuit 6V will be described. As shown in FIG. 8A, consider a data string sandwiching a vertical block boundary 31V. * is a boundary sample of one block Bl, and ■ is a boundary sample of the other block B2. As shown in FIG. 8B, the value of the boundary sample is held at the corresponding sample position of block Bl, and similarly, the value of the boundary sample ■ is held at the corresponding sample position of block B2.

The corresponding samples of the data line shown in FIG. is detected as an object part.

In the case of an object part, the selection circuit 8v selects the original signal from the block decomposition circuit 3, and in the case of a part other than the object part, selects the output signal of the smoothing circuit 7v.

The object portion detection circuit 6H, like the object portion detection circuit 6V, holds the boundary value near the horizontal block boundary 31H and detects the object portion. The selection circuit 8H is controlled by the output signal of the object part detection circuit 6H, and the output signal of the smoothing circuit 7H is selected for the object part, and the output signal of the selection circuit 9v is selected for the parts other than the object part.

The above-mentioned smoothing process does not cause problems such as blurring of the outline of the object even when there is an object at the block boundary, and even in fine patterns such as those shown in FIGS. 9A and 9B, No deterioration occurs due to smoothing processing.

FIG. 9A shows a pattern in which a thin black line runs diagonally across adjacent blocks Bl and B2 with the block boundary 31V in between. According to the block distortion detection method described above,
A two-sample window is sequentially moved to detect block distortion. Even if block distortion occurs between blocks B1 and B2, the difference values between adjacent samples in the black line part are not zero, so block distortion is not detected, and the black line is smoothed. In the pattern shown in FIG. 9B, in which a thicker black line runs diagonally across blocks B1 and B2 compared to FIG. 9A, which does not cause deterioration such as blurring due to Similarly, smoothing processing is not performed on the outline of the black line. However, since the black line is thick, block distortion occurring inside the black line is removed by smoothing.

d. Specific structure of one embodiment FIG. 1O shows a specific structure of one embodiment of the present invention. In FIG. 10, ADRC decoding and block decomposed video data is supplied to an input terminal 40. The input terminal 40 has ■ line memories 41, 42, 43.
, 44, 45 are connected in cascade. line memory 42
Data from the output side and data from its input side are supplied to a vertical block distortion detection circuit 50. line memory 4
The output signals of 2.43 and 44.45 are supplied to the horizontal block distortion detection circuit 60. In the vertical block distortion detection circuit 50, · and △ in FIG.

The data of the ○ and × lines are taken in, and it is checked whether block distortion in the ■ direction has occurred. In the horizontal block distortion detection circuit 60, the occurrence of block distortion in the H direction is
Can be examined in line parallel.

55, 56, 57, and 58 indicate vertical processors, respectively. The vertical processors 55 to 58 have an object part detection circuit 6V.
, smoothing circuit 7V, selection circuit 8V.

The vertical processors 55 to 58 are supplied with a detection signal SV from the vertical block distortion detection circuit 50. 4 vertical processors 55~
58 is provided because the block distortion in the {circle around (2)} direction is performed on four lines sandwiching the block boundary. Vertical processors 55, 56, 57, and 58 are supplied with two output signals and two input signals from line memories 43, 42, and 41 via sample delay circuits 51, 52, and 53, 54, respectively. Further, in the arithmetic circuit 46, the sample delay circuit 5
3 is subtracted and the output signal of the subtraction circuit 46 is provided to the vertical processor 55.56.degree. 57.58.

The horizontal block distortion detection circuit 60 has the same configuration as the vertical block distortion detection circuit 50, and detects the H-direction block distortion of each of the four lines in parallel.

Detection signals SH1 and S from the horizontal block distortion detection circuit 60
H2 is supplied to horizontal processors 67 and 68 via 4-line memories 63 and 64, respectively, and detection signals SH3 and SH4 are
are provided to horizontal processors 65,66. The horizontal processors 65 to 68 perform the processing of the object portion detection circuit 6H, the smoothing circuit 7H, and the selection circuit 8) (, 9H, respectively).

The horizontal processors 65.66 include vertical processors 55.66.
56 output signals are provided to the horizontal processors 67 .
68 are supplied with the output signals of the vertical processors 57 and 58 via four-line memories 47 and 48, respectively. Also,
The horizontal processors 67 and 68 include a sample delay circuit 61.
．． The output signals of the line memories 44 and 45 are supplied through the line memories 44 and 62, respectively. The output signal of the horizontal processor 65 is sent to the register 7 with output control via the 2-line memory 69.
2, and the output signal of the horizontal processor 66 is sent to the register 73 with output control via the 3-line memory 70.
The output signal of the horizontal processor 67 is supplied to the register 74 with output control.
8 output signals are supplied to a register 75 with output control via a line memory 71. These registers 7
An output signal of 2°73.74.75 is taken out to the output terminal 76. 2 line memory 69. 3 line memo U70.
The line memory 71 is used to return data processed in four lines in parallel to data at the original line timing.

The vertical block distortion detection circuit 50 has the configuration shown in FIG. In FIG. 11, the data series (a) of the line above the block boundary 31 (see FIG. 5) is supplied to the input terminal indicated by 81, and the data series (b) of the line below it is supplied to the input terminal indicated by 82. ) is supplied. The sample delay circuit 83 and the comparison circuit 85 convert the data series (a
) is formed, and the sample delay circuit 84 and comparison circuit 86 form the data series (
Adjacent sample difference value D2 of b)! -1 is formed. Further, the output signals of the sample delay circuits 83 and 84 are supplied to a subtraction circuit 87, and an adjacent block difference value D3i-+ is obtained from the subtraction circuit 87.

These difference values are supplied to the ROM 88 as address signals. ROM8B contains (Dl+-+"'D 2 i
A data table is stored for determining whether the following conditions (0 and O<D 3 i-+ ≦DF) are satisfied, and a detection signal regarding V-direction block distortion is read from the ROM 88.OR The gate 89 is supplied with a detection signal read from the ROM 88 and a detection signal obtained by delaying this detection signal by a sample delay circuit 90.OR gate 89 and sample delay circuit 9
0 is provided to hold the detection signal for two samples. A detection signal SV is taken out from the OR gate 89 to an output terminal 91.

e. Modified Example The present invention can be applied not only to variable length ADRC but also to block coding in which the average value and standard deviation of each block are transmitted. Further, the present invention can be applied to removing block distortion from component or composite color video data.

〔Effect of the invention〕

In this invention, a two-sample detection window is set, and block distortion is generated for each detection window. Therefore, according to the present invention, the present invention is not limited to block distortion where adjacent blocks are flat and have level differences, but also patterns where there is a black line within a flat level, diagonal patterns where the levels are different from each other, etc. It is also possible to remove block distortion caused by striped patterns and the like. Further, in the present invention, by removing block distortion, deterioration such as blurring of object parts does not occur. Furthermore, since block distortion is reliably removed, it is possible to increase the compression ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a route diagram used to explain the blocks of this embodiment, FIG. 3 is a flowchart used to explain the operation of this embodiment, and FIG.
5 and 5 are route maps used to explain block distortion detection operations, FIGS. 6 and 7 are route maps used to explain smoothing, and FIG. 8 is route maps used to explain object part detection operations. ,
FIG. 9 is a route diagram used to explain block distortion detection and smoothing processing in the case of a fine pattern model, FIGS. 1O and 11 are block diagrams of an example of the specific configuration of this embodiment, and FIG. The figure is a route map used to explain block encoding to which the present invention can be applied, and FIGS. 13 and 14 are route maps used to explain block distortion generation patterns. Explanation of main symbols in the drawings 1: Received data input terminal, 2: ADRC decoder,
3 niblock decomposition circuit, 4 niblock distortion removal circuit,
4■: Vertical block distortion processing section, 4H: Horizontal block distortion processing section, 5V: Vertical block distortion detection circuit, 5H:
Horizontal block distortion detection circuit, 6V, 6H: Object part detection circuit, 7V. 7H: Smoothing circuit, 8V, 8H, 9V, 9H: Selection circuit. Agent: Patent Attorney Tadashi Sugiura Knowledge: Figure 9, Figure 11

Claims (1)

[Scope of Claims] A decoding device for block-encoded image signals that compresses the amount of transmission data of a digital image signal for each block formed by subdividing one screen, comprising: a decoding circuit that decodes the block encoding; Means for separating the first sample a_i_-_1, the second sample a_i, the third sample b_i_-_1, and the fourth sample b_i that are supplied with the output data from the decoding circuit and are adjacent to each other across the block boundary. and the difference value D1_i_-
_1 (=a_i_-_1-a_i), D2_i_-_1
(=b_i_-_1-b_i), D3_i_-_1(=
|a_i_−_1−b_i_−_1|) is (D1_i_
−_1=D2_i_-_1≒0 and 0<D3_i_-_
block distortion detection means for detecting that block distortion occurs at the block boundary when the condition of 1≦DF, DF: threshold value) is satisfied; and a smoothing means for removing the block distortion. What is claimed is: 1. A decoding device for a block encoded image signal.