JPS63104368A - Semiconductory device - Google Patents
Semiconductory deviceInfo
- Publication number
- JPS63104368A JPS63104368A JP61250502A JP25050286A JPS63104368A JP S63104368 A JPS63104368 A JP S63104368A JP 61250502 A JP61250502 A JP 61250502A JP 25050286 A JP25050286 A JP 25050286A JP S63104368 A JPS63104368 A JP S63104368A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- resistance component
- type substrate
- drain diffusion
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 241001061309 Astragalus hamosus Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、Ｎ型サブストレート上に構成される（ＪｉＯ
８半導体装置に関し、特に入力静電保護回路に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention is constructed on an N-type substrate (JiO
8 regarding semiconductor devices, particularly regarding input electrostatic protection circuits.
従来、ＭＯ８半導体装置は静電気に対して弱い為、その
入力回路には静電保護対策が施されている。しかしなが
ら近年、ＣＭＯＳＬＳＩの需要の拡大並びにアプリケー
ション範囲の拡大に伴ない、さらに高い静電保護対策を
要求される様になってきている。さらに、プロセスのフ
ァイル化に伴ない、ゲート酸化膜厚の減少並びにｐ−ｎ
ジャンクションのシャロー化が進んでおり、静電保護も
雉しくなってきている。Conventionally, since MO8 semiconductor devices are susceptible to static electricity, electrostatic protection measures have been taken for their input circuits. However, in recent years, as the demand for CMOS LSIs and the range of applications have expanded, even higher electrostatic protection measures have been required. Furthermore, with the process filing, the gate oxide film thickness has decreased and the p-n
Junctions are becoming shallower, and electrostatic protection is becoming more difficult.
上述した従来の半導体装置においては、ゲート電極とし
てポリシリコンを使用するプロセスが主流である為、Ｍ
ＯＳゲートとして使用するポリシリコンを抵抗として用
いる事により第４図及び第５図に示す様に、パッド７か
らの配線をポリシリコン配線の抵抗成分を介して、電源
又はグランドに対して逆バイアスされたダイオード１４
．１５に接続した上で内部ゲートの入力へ接続していた
。In the conventional semiconductor devices mentioned above, since the mainstream process is to use polysilicon as the gate electrode, M
By using polysilicon used as an OS gate as a resistor, the wiring from pad 7 can be reverse biased with respect to the power supply or ground through the resistance component of the polysilicon wiring, as shown in Figures 4 and 5. diode 14
．． 15 and then connected to the input of the internal gate.
この方式により、少なくとも静電気による内部ＭＯＳゲ
ートの破壊を保護する事が可能であるが、ポリシリコン
は、フィールド上の〜１μｍ程度の厚い酸化膜上に形成
されている為、放熱効果に乏しく局所的なジーール熱の
発生によシポリシリコン抵抗が溶断してしまうモードや
、Ｐ−Ｎダイオードのジャンクションが浅くなった為Ｋ
、Ｐ−Ｎジャンクションが過電流の為に破壊してしまう
モードの為に、内部ゲート破壊にいたらないまでもデバ
イスは、静電破壊されてしまうという欠点がある。This method can at least protect the internal MOS gate from being destroyed by static electricity, but since polysilicon is formed on a ~1 μm thick oxide film on the field, it has poor heat dissipation effect and may be localized. There is a mode in which the polysilicon resistor melts due to the generation of Geel heat, and the PN diode junction becomes shallow.
, since the P-N junction is destroyed due to overcurrent, the device has the drawback of being damaged by electrostatic discharge even if the internal gate is not destroyed.
本発明の半導体装置は、入力静電保護回路に少なくとも
ｚｓ類の異なる逆方向降伏特性をもつ、Ｎ型サブストレ
ートをカソード電極とするＰ−Ｎダイオードを有してい
る。The semiconductor device of the present invention has an input electrostatic protection circuit including a PN diode having reverse breakdown characteristics different in at least zs classes and having an N-type substrate as a cathode electrode.
ここでパッドに接続される第１のダイオードは、Ｐウェ
ル拡散工程で形成され、そのアノードのＰ型不純物濃度
は低く、かつ接合が深いため高い耐圧を有している。ま
た第１のダイオードのＰ型拡散層の抵抗を介して接続さ
れる第２のダイオードは、ソース・ドレイン拡散工程で
形成される事、Ｐ型不純物濃度は高く、かつ接合も浅い
ため比較的耐圧が低いつ
そして、第２のダイオードが破壊されない様に第１のダ
イオードのＰ型拡散層の抵抗値を決める事により、高い
静電耐圧特性を有するＣＭＯＳ半導体装置を提供するも
のである。The first diode connected to the pad is formed by a P-well diffusion process, and has a low P-type impurity concentration at its anode and a deep junction, so it has a high breakdown voltage. In addition, the second diode, which is connected through the resistance of the P-type diffusion layer of the first diode, has a relatively high breakdown voltage because it is formed in a source/drain diffusion process, has a high P-type impurity concentration, and has a shallow junction. By determining the resistance value of the P-type diffusion layer of the first diode such that the resistance is low and the second diode is not destroyed, a CMOS semiconductor device having high electrostatic breakdown voltage characteristics is provided.
次に本発明洗ついて図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の静電保護回路の一実施例の断面図であ
る。Ｎ型サブストレート１にＰウェル２を拡散する事に
より作られたアノードの濃度が低く、接合の深い第１の
ダイオードとリース・ドレイン拡散３で作られたアノー
ドの濃度が高く、接合の浅い第２のダイオードから構成
されている。FIG. 1 is a sectional view of an embodiment of the electrostatic protection circuit of the present invention. The anode made by diffusing the P-well 2 into the N-type substrate 1 has a low concentration and a deep junction, and the anode made by lease-drain diffusion 3 has a high concentration and a shallow junction. It consists of two diodes.
但し、第１のダイオードも電極にはオーミック性を良く
する為にリースドレイン拡散３を拡散している。ここで
、第１のダイオードと第２のダイオードはアルミ配線６
で結線されている。However, the electrode of the first diode is also diffused with lease-drain diffusion 3 in order to improve ohmic properties. Here, the first diode and the second diode are connected to the aluminum wiring 6.
is connected with.
第２図に本発明の他の実施例の断面図を示す。FIG. 2 shows a sectional view of another embodiment of the invention.
本実施例においては、第１のダイオードと第２のダイオ
ードを１つの素子として作っている。さらに、第１のダ
イオードの全面にリースドレイン拡散を行なう事により
第１のダイオードの抵抗成分を下げている。In this embodiment, the first diode and the second diode are made as one element. Furthermore, the resistance component of the first diode is lowered by performing lease-drain diffusion over the entire surface of the first diode.
第３図に本発明の静電保護回路の等価回路を示す。パッ
ド７から第１のダイオード８に接線され、抵抗成分１０
を介して第２のダイオード９に接続され抵抗成分１１を
介して、内部ゲートに接続されている。FIG. 3 shows an equivalent circuit of the electrostatic protection circuit of the present invention. The pad 7 is tangent to the first diode 8, and the resistance component 10
It is connected to the second diode 9 via the resistor component 11, and to the internal gate via the resistive component 11.
さらに別の実施例として、第２のダイオードと並列にリ
ーチスルーダイオード等を組み合わせる事や、グランド
との間に逆バイレスのＰ−Ｎダイオードを組み合わせる
例などが考えられる。As still another example, a reach-through diode or the like may be combined in parallel with the second diode, or a reverse bias PN diode may be combined between the second diode and the ground.
以上説明した様に本発明は、耐圧の異なる２ケのＰ−Ｎ
ダイオードを用いる事により以下の効果がある。As explained above, the present invention has two P-Ns with different withstand voltages.
Using a diode has the following effects.
１）正電圧サージ（で対しては、第１のダイオードの順
方向電流をサブストレートよシ比僕的低いインピーダン
スで流す事ができる またこの時、第１のダイオードは
接合が深く容易に破壊する事がない。1) For positive voltage surges, the forward current of the first diode can be passed through the substrate with relatively low impedance. Also, at this time, the first diode has a deep junction and is easily destroyed. There's nothing wrong.
２）負電圧の丈−ジに対しては、第１のダイオードは抵
抗成分として作用し、第２のダイオードの降伏電流を！
ｉＪ ８する。事（てよシ、第２のダイオードが電流破
壊する事を防ぐ。2) For the length of negative voltage, the first diode acts as a resistive component and reduces the breakdown current of the second diode!
iJ 8. This prevents the second diode from being destroyed by current.
３）第１のダイオードは特に発熱する事が考えられるが
、ポリシリコンの抵抗と異な）バルクである為、局所的
なジュール熱による破壊の心配が少ないう
このようだして本発明によシ、高い静電耐圧をもつＣＭ
ＯＳ半導体装置を提供しうるう3) The first diode is likely to generate particular heat, but since it is a bulk (unlike a polysilicon resistor), there is less risk of destruction due to local Joule heat, so it is suitable for the present invention. CM with high electrostatic withstand voltage
Provides OS semiconductor devices
第１図は本発明の一実施例の断面図、第２図は本発明の
他の実施例の断面図、第３図は本発明の等価回路図、第
４図、第５図は従来の静電保護回路の等価回路図である
。
ｌ・・・・・・Ｎ型サグストレート、２・・・・・・Ｐ
ウェルであり第１のダイオードのアノードとなる。３・
・・・・・リース・ドレイン拡散（Ｐ型）であり、第２
のダイオードのアノード及び第１のダイオードのコンタ
クト拡散となる。４・・・・・・フィールドロコス、５
・・・・・・ポリシリコンと配線金属との層間膜、６・
・・・・・アルミ等の配線金属、７・・・・・・パッド
、８・・・・・・第１のダイオード、９・・・・・・第
２のダイオード、ｌＯ・・・・・・第１のダイオードの
抵抗成分、１１・・・・・・第２のダイオードの抵抗成
分、１２・・・・・・内部ゲートのＰチャンネルトラン
ジスタ、１３・・・・・・内部ゲートのＮチャンネルト
ランジスタ、１４・・・・・・従来の静電保護素子のＮ
型サブストレートとの間のダイオード、１５・・・・・
・従来の静電保護素子のＰウェルとの間のダイオード。
代理人 弁理士 内 原 ”−゛・（、・、）
牛 ２ 図
牛 ３ 図FIG. 1 is a cross-sectional view of one embodiment of the present invention, FIG. 2 is a cross-sectional view of another embodiment of the present invention, FIG. 3 is an equivalent circuit diagram of the present invention, and FIGS. 4 and 5 are conventional FIG. 3 is an equivalent circuit diagram of an electrostatic protection circuit. l...N type sag straight, 2...P
It is a well and serves as an anode of the first diode. 3.
...Reese-drain diffusion (P type), second
This becomes the anode of the diode and the contact diffusion of the first diode. 4...Field Locos, 5
・・・・・・Interlayer film between polysilicon and wiring metal, 6.
...Wiring metal such as aluminum, 7...Pad, 8...First diode, 9...Second diode, lO...・Resistance component of first diode, 11...Resistance component of second diode, 12...P channel transistor of internal gate, 13...N channel of internal gate Transistor, 14...N of conventional electrostatic protection element
Diode between mold substrate, 15...
・Diode between P-well of conventional electrostatic protection element. Agent Patent Attorney Uchihara ”－゛・（、・、） Ushi 2 Ushi 3 Ushi
Claims (2)
体装置において、その入力回路に少なくとも２個のＮ型
サブストレートをカソード電極とするＰ−Ｎダイオード
を有し、且つパッドに接続される第１のダイオードのア
ノードのＰ型不純物濃度が、第１のダイオードのＰ型拡
散層抵抗成分を介して接続される第２のダイオードのア
ノードのＰ型不純物濃度より低く且つ、第１のダイオー
ドのＰ−Ｎ接合が第２のダイオードのＰ−Ｎ接合よりも
深い事を特徴とする半導体装置。(1) In a CMOS semiconductor device constructed on an N-type substrate, the input circuit has at least two P-N diodes whose cathodes are the N-type substrate, and a first The P-type impurity concentration of the anode of the diode is lower than the P-type impurity concentration of the anode of the second diode connected via the P-type diffusion layer resistance component of the first diode, and A semiconductor device characterized in that the N junction is deeper than the P-N junction of the second diode.
イオードとアノードをソース・ドレイン拡散工程で形成
した第２のダイオードを含む事を特徴とする特許請求の
範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, comprising a first diode whose anode is formed by a P-well diffusion process and a second diode whose anode is formed by a source/drain diffusion process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61250502A JPS63104368A (en) | 1986-10-20 | 1986-10-20 | Semiconductory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61250502A JPS63104368A (en) | 1986-10-20 | 1986-10-20 | Semiconductory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104368A true JPS63104368A (en) | 1988-05-09 |
Family
ID=17208833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61250502A Pending JPS63104368A (en) | 1986-10-20 | 1986-10-20 | Semiconductory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104368A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007335882A (en) * | 1992-09-21 | 2007-12-27 | Siliconix Inc | BiCDMOS STRUCTURE AND MANUFACTURING METHOD THEREOF |
-
1986
- 1986-10-20 JP JP61250502A patent/JPS63104368A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007335882A (en) * | 1992-09-21 | 2007-12-27 | Siliconix Inc | BiCDMOS STRUCTURE AND MANUFACTURING METHOD THEREOF |
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