JPS63104091A - Frequency adjustor - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a phase control device and a sequential blinking device for automatically controlling heat lamps, neon lamps, fluorescent lamps, etc. It relates to a device that automatically increases and decreases.

Conventionally, the clock pulses supplied to automatic control counters have been fixed at a constant frequency. Therefore, when used for advertising and decorative lights, the transition timing is constant, so the change is (11) pure and lacks freshness.

In order to eliminate the above-mentioned drawbacks, the present invention automatically changes the frequency of clock pulses supplied to a control counter to provide a novel phase control device and a sequential blinking device that are rich in variety that has never existed before. It is something to do.

The present invention will be described in detail below with reference to the drawings. 1 is an oscillation circuit, which is composed of three digital IC inverters, a time-limited resistor RT n, and a time-limited conductor fcT.
This is an unstable multivibrator that has been used conventionally, and in order to switch the oscillation frequency into four stages, the time-limited resistor is divided into RTO, RTI, RT2, and RT3, and an analog switch (bidirectional one) is connected to the divided time-limited resistors. )
Each set of ASO1ASI%AS2 and AS3 connected in series is connected in parallel, and the control input of each analog switch is the output QO1Q1, Q2 of the first counter.
, Q3, respectively. 2 is the first counter, and the circuit is configured so that only one output out of four outputs is at the rHJ level, and the clock input CKI is at the RHJ level.
-8 It is connected to the output Q of the latch circuit 6. 3 is a second counter, which is incorporated as a control counter in the automatically controlled phase control device and sequential blinking device, and a BCD counter, binary counter, ring counter, etc. is used, and the clock input CK2 is used for oscillation. circuit 1
connected to the output of

4 is a cycle detection circuit whose input is connected to the output of the second counter 3; 5 is the third counter, preset,
It has carry, up and down functions, ship down human power UD, carry human power CAI, and clear input CL are all connected to vSS, the count operation is fixed to down mode, and clock input CK3 is a cycle detection circuit. The data inputs A%B%C and D are connected to the outputs A and B%C%D of Samir switch 8, respectively.

6 is an R-S latch circuit, and input R is a cycle detection circuit 4
The input S is the carry output CA of the third counter 5.
O, the output Q is connected to the clock input CKl of the first counter 2 and the load input LO of the third counter 5 via the OR gate 7.
are connected to each. X is a start pulse, which is set to RHJ level only at the moment of power-on, and is connected to the clear input CL for the first counter 2, and to the load human power LO for the third counter via the OR gate 7. There is.

Next, the operation of an embodiment of the present invention will be explained.

When the power is turned on, the output of the first counter 2 is set to QO by the start pulse X, and the output of the third counter 5 is set to the value rn set by the Samir switch 8.

In the oscillation circuit 1, since the output of the first counter 2 is set to QO, the analog switch ASO is turned on.
A pulse having a frequency depending on the time constant of the time limit resistor RTO and the time limit capacitor CT is outputted and supplied to the second counter 3 as a clock pulse. The cycle detection circuit 4 outputs a pulse every time the second counter completes one cycle of counting operation.
It is supplied to the third counter 5 as a clock pulse. The third counter 5 receives the numerical value rn set by the Samir switch 8.
When the count is down from J to "0", the carry output CAO is inverted from r I (J level to "L" level, operates the R-S latch circuit 6, and outputs the load manual input LO via OR gate 7. is inverted from the "L" level to the "I(" level), the output value "0" instantaneously matches the value rnJ set by the Samir switch 8, and the down count is repeated. The clock input CKI of the counter 2 is supplied with a pulse generated every time one cycle of the third counter 5 is completed, so that the counting operation continues. Compatible analog switch AS
n is turned on, time-limiting resistor RTn and time-limiting capacitor CT
It outputs a pulse with a frequency depending on the time constant of , and automatically switches the frequency of the clock pulse supplied to the clock input CK2 of the second counter 3 in sequence.

FIG. 2 shows an example of another counter that has the same function as the third counter 5 in FIG. 1, and 9 is a Jinson counter or ring counter with a clear function.
Only the count state to be decoded is set to "H" level, and all others are set to "L" level. Clock input CK is connected to the output of cycle detection circuit 4. Start pulse X is connected to clear input CL via OR gate 10. The output QO is connected to the clock input CKI of the first counter 2. 11 is a rotary switch, and terminals 1.2.3.4.5.6.7 are the outputs of counter 9 Q1, Q2, Q3, Q4, Q5, Q6, Q7.
are connected to each.

12 is an R-8 latch circuit, the input R is connected to the clock input CK of the counter 9, the input S is connected to the common terminal P of the rotary switch 11, and the output Q is connected to the clear input CL of the counter 9 via the OR gate 10. has been done.

In the case of the third counter 5 shown in Fig. 1, data input was controlled by the Samir switch 8 to set the range of counts per cycle, but in the case of the third counter 5 shown in Fig. 2, data input was controlled by the Samir switch 8. By selecting the output Qn (n+0) of the counter 9 with the rotary switch 11 and feeding it back to the clear input CL via the R-8 latch circuit 12 and the OR gate 10, the count per 1-9-cycle is calculated. Setting the range of numbers. Third counter 5
The role of 9 is the second counter (automatic control counter)
When sequentially switching the clock pulses of different frequencies supplied to the second counter 3, the Samir switch 8 or the rotary switch 11 is used to set the number of cycles after which the second counter 3 is switched. It is to command.

What is shown in FIGS. 3 and 4 both show other examples of the oscillation circuit 1 shown in FIG. ) 13, which is a conventionally used oscillation circuit. What is shown in FIG. 3 is a time-limited resistor group in which each set of divided time-limited resistors RTO1RTI, RT2, RT3 and analog switches ASO1ASI, AS2, A3B connected in series are connected in parallel.
By sequentially controlling the control input of each analog switch ASn with the output of the first counter 2, the amount of charge flowing into the positive rising time capacitor CT is controlled, the time constant is changed, and the oscillation frequency is changed stepwise. To,
Moreover, it increases and decreases automatically. In the case shown in FIG. 4, the resistance value of the time resistor RT is made small, the amount of charge flowing into the positive maximum rising time capacitor fCT is maximized, and the divided time resistors RTO%RTI, RT2, RT3, By connecting each set of series-connected analog switches ASO1ASI, AS2, and A3B in parallel with a time-limited capacitor CT, and sequentially controlling the control input of each analog switch ASN with the output of the first counter 2, a time-limited resistor can be created. By changing the amount of charge flowing through RT to the negative pole and sequentially limiting the amount of charge flowing into the time capacitor CT, changing the time constant, the oscillation frequency can be adjusted as shown in Figure 3. It increases and decreases automatically in a stepwise manner.

In Figures 3 and 4, an oscillation circuit using a unijunction transistor (UJT) as a switching element was explained, but it is also possible to use other programmable unijunction transistors (PUT), PnPn switching elements, etc. A conventional oscillation circuit may also be used.

The analog switch ASn used in the oscillation circuit in FIG. 1 of the embodiment has reversed polarity, so it is necessary to use a bidirectional one, but the analog switch used in the oscillation circuit shown in FIGS. Since the polarity of A3n is fixed without being reversed, it may be unidirectional, and a general transistor can be used alone.

Although the embodiment has been described with reference to a frequency change in four stages, the number of stages may be increased or decreased depending on the application.

In the US invention, the circuit is configured to automatically and sequentially switch and increase/decrease the frequency of the clock pulses supplied to the control counter in the phase control device and the sequential blinking device. The timing of changing the illuminance of the light source (incandescent lamp, neon lamp, fluorescent lamp, etc.) or the timing of transitioning to blinking changes, so it produces innovative advertising and decorative effects that have never been seen before, and is highly practical. It is rich.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1. FIG. 2 is a circuit diagram of another counter that operates in the same way as the third counter 5 in FIG. Circuit diagram of another oscillation circuit that operates. 1 is the oscillation circuit. RTO% RT1, RT2, RT3, RT
is a timed resistance. CT is a time capacitor. Person 5O1ASI,
AS2 and AS3 are analog switches. 2 is the first counter. 3 is a second counter (automatic control counter) and 4 is a cycle detection circuit. 5.9 is the third counter. 6.12 is the R-S latch circuit. 7.10 is an OR gate. 8 is Samir switch. 11 is a rotary switch.

Claims (1)

[Claims] In clock pulse generation circuits for automatically controlled phase control devices and sequential flashing devices, the time-limited resistor of the oscillation circuit, which is composed of a time-constant circuit based on a time-limited resistor and a time-limited capacitor, and a switching element, is divided into multiple parts. Each pair of analog switches connected in series to each time-limiting resistor is connected in parallel, the control input of each analog switch is connected to each output of the first counter, and the output of the oscillation circuit is clocked to the second counter. Supplied as a pulse,
The pulse generated at the end of one cycle of the counting operation of the second counter is supplied to the third counter as a clock pulse, and the output value of the third counter is set to the initial value by the pulse generated at the end of one cycle of the counting operation of the third counter. At the same time, it is supplied as a clock pulse to the first counter, and the output value of this first counter sequentially controls the control input of each analog switch of the oscillation circuit to switch the time constant of the oscillation circuit. A frequency increase/decrease device characterized in that the frequency of a clock pulse supplied to a counter is automatically increased/decreased.