JPS63102511A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To generate a frequency division output fed to a synchronizing counter of the next stage in a normal state by latching a frequency division output signal of n stages of T flip-flops (T-FFs) by a D flip-flop (D-FF) and a reference clock and using its output as a synchronizing clock of the synchronizing counter thereby compensating a delay due to the T-FFs. CONSTITUTION:A T-FF1 is operated by the rising of a reference clock A after a reset signal (u) is released to obtain an output B. An output C is obtained by operating a T-FF2 by the rising of the output B. Then a T-FF3 is activated by the trailing of the output C and a T-FF4 is operated by the trailing of an output D similarly to obtain an output E. The output E is retarded by 1T via a D-FF5 with respect to the reference clock K to correct the leading of the output of the T-FF2 by 1T and to correct a delay time T4 at the output E into a delay T5 by one stage of the D-FF with respect to the reference clock K. Then the inverted output of the D-FF5 is used for the synchronizing clock of the synchronizing counter 6 to obtain outputs G and H.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency divider circuit for correcting the delay of a high-speed frequency divider.

BACKGROUND OF THE INVENTION In recent years, digital technology has become faster, and in video applications, frequency divider circuits using 14 MHz or 28 MHz clocks are being used.

An example of the above-mentioned conventional frequency dividing circuit will be described below with reference to the drawings. FIGS. 3 and 4 show the configuration of a conventional frequency dividing circuit and its operating waveforms. In Fig. 3, 10 to 13 are T-type flip-flops, 14 is a synchronous counter, 15° and 16 are respective gates, and 17 is a D-type flip-flop, which divides the reference clock K, and gates 15° and 16 output the frequency. is decoded to obtain the output S.

The operation of the frequency dividing circuit configured as described above will be explained below. First, in Fig. 4, assuming that the reference clock K is a clock signal with a period t, in order to divide this signal, the reset signal T must be released (...becomes an e-level) as shown in Fig. 3. ), the T-type flip-flop (hereinafter referred to as T-FF) 10 is operated at the rising edge of the signal to obtain the frequency-divided output shown in the fourth figure. From then on, T-
By operating the FFs 11 to 13 using the falling signal of the preceding stage, the divided signals M, N, and O in FIG. 4 can be obtained. However, the output ○ of the T-FF 13 is inverted. By using this signal as a synchronization clock for the next-stage synchronization counter 14, its frequency-divided outputs P and Q are obtained.

Here, as an example, if a decoding circuit consisting of gates 15 and 16 is assembled, its output will be as shown in FIG. 4R, and pulses of a certain section can be extracted. After that, the reference clock K is latched to the reference clock at the end of the D-type flip 70 (hereinafter referred to as -FF).
A frequency-divided decode output S synchronized with is obtained.

Generally, a synchronous counter is used for high-speed frequency division, but the circuit configuration of a synchronous counter is more complicated than that of a T-FF frequency divider, and the chip size becomes larger when integrated into an IC. +J-Rinari is often taken.

Problems to be Solved by the Invention However, in the above configuration, the delay from the reference clock due to T-FFO frequency division is as shown in FIG.
At the branch output, t s (sec), at the output M, t
9. Gradually add tlo at output N and tll at output O, for example, 10 ns per T-FF stage.
If there is a delay of 14 MHz (t = 70 n s
) When trying to operate with 7 stages or more T-F
F cannot be connected in cascade. In Figure 4,
16, the output P is delayed by t12. At this time, for example, if the D-FF is launched once before the total delay of the T-FF exceeds the period t of the reference clock, the delay can be corrected. Although we want to visually obtain the output P of 16 in frequency division, the problem is that it is delayed by 1t and outputs 17, which is inconvenient for frequency division after the reset is released. was.

In view of the above-mentioned problems, the present invention provides a frequency divider circuit that compensates for the delay caused by frequency division of T-FF and properly generates a frequency divided output to be added to the next-stage synchronous counter.

Means for Solving the Problems In order to solve the above problems, the frequency divider circuit of the present invention has a T-FF that operates on the rising edge of a signal and a T-FF that operates on the falling edge of the signal.
It has a configuration of an FF, a D-FF, and a synchronous counter.

Operation According to the present invention, with the above-described configuration, the delay in the T-FF is compensated for by the D-FF, and a one-clock shift due to the D-FF is corrected.

Embodiment Hereinafter, a frequency divider circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a frequency dividing circuit in one embodiment of the present invention.

In FIG. 1, 1 to 4 are T-FF, and s is D-FF.

6 is a synchronous counter, 7 and 8 are each gate 9 is D-F
It is F.

Regarding the first frequency dividing circuit configured as above, the first
The operation will be explained with reference to the drawings and FIG. 2.0 First, after the reset signal U is released, the T-FF1 is operated at the rising edge of the reference clock A, and the output B is obtained. By operating T-FF2 at the rising edge of output B, output C
is obtained, but at this time, the output C is relative to the reference clock A,
The station is branching out by 1T. Thereafter, T-FFa is operated by the fall of the output C, and similarly, T-FF4 is operated by the fall of the output C to obtain the output E. Output E via D-FFs, 1T with respect to reference clock K
By delaying, the advance of the output of the T-FF2 by 1T is corrected, and the delay time T4 at the output E is corrected to the delay amount T5 of one stage of the D-FF with respect to the reference clock K.

Thereafter, the inverted output of the D-FF 5 is used as a synchronous clock of the synchronous counter 6 to obtain outputs G and H.

Furthermore, a decoded output of the pulse I is obtained by the gate 7.8, and an output J is obtained via the D-FF9.

As described above, according to this configuration, the cascade-connected T-F
D-FFs are inserted between F 1 to 4 and the synchronization counter 6 to correct the delay caused by T-FF, and
By starting up the second stage of F, it is possible to correct the 1T delay caused by the D-FF without adding any circuit.

Effects of the Invention As described above, the present invention has the following effects by providing the D-FF.
Although the frequency division delay caused by the T-FF is corrected, the D-FF
The delay time due to insertion can be corrected by 1T of the reference clock.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a frequency dividing circuit in an embodiment of the present invention,
FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is a circuit diagram of a conventional frequency dividing circuit, and FIG. 4 is a waveform diagram for explaining its operation. 1.2, 3.4...T type flip-flop, 5
...D type flip-flop, 6...Synchronous counter.

Claims (1)

[Claims] a reference clock signal and n stages of T-type flip-flops connected in cascade;
The first stage is operated by the rising edge of the reference clock signal, the second stage is operated by the rising edge of the output signal of the previous stage, and the third and subsequent stages are operated by the falling edge of the output signal of the previous stage. The D-type flip-flops connected to each other and an m-stage synchronous counter inputting the inverted output thereof as a synchronous clock are provided, and the frequency-divided output signal of the n-stage T-type flip-flops is connected to the D-type flip-flop and a reference clock. 1. A frequency dividing circuit, characterized in that the frequency dividing circuit is latched by the synchronous counter, and its output is used as a synchronous clock for the synchronous counter.