JPS6310238A - Control system for main memory key - Google Patents

Abstract

PURPOSE:To avoid the effect of the key access of a main memory to the data access to a main memory by prefetching a main memory key before execution of an instruction or carrying out the replacement of the main memory key only with the first access of a page. CONSTITUTION:An access is previously supplied to a main memory key memory part 2 before an instruction is carried out by the pipeline control and a main memory key is saved to a main memory key holding register 21. Then no read access is given to the part 2 when the first access of an operand is issued to a main memory 1 and only a write access is given to the part 2 by means of the main memory key saved to the register 21. Furthermore no access is given to the main memory key before a page is through when the second and subsequent accesses are given to the device 1. As a result, the number of accesses can be decreased to the part 2 and at the same time the number of accesses to the main memory key can also be decreased when an access is given to the device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory key control method in a data processing device, and particularly relates to a main memory key control method suitable for a data processing device that processes by advance control. .

[Conventional technology]

In a data processing device, the main memory is divided into a plurality of blocks (pages) and a main memory key corresponding to each block is provided for the purpose of protecting the main memory and recording references and changes. As shown in Figure 2, the main memory key is a key part (KEY) for protecting access to the block.
), a reference bit (R) for keeping a record of access to the block, a change bit (C), and a check bit (P) for checking the main memory key. The R bit becomes 1'1" when writing or reading from the block, and the C bit becomes "1" when writing is performed.

Generally, the main memory key is prepared on the main memory key storage section,
For one access to the main memory, the main memory key storage section is read out for the purpose of memory protection check.
For example, when writing data to main memory, first read the main memory key. It is necessary to perform a write protection check. For this reason, even if the write data to the main memory is complete before the main memory key is read, a write request to the main memory cannot be issued until after the main memory key is read1.
Next, it is necessary to write the main memory key to update the R/C/P. With this write, R/C is set to logic "1" and P is generated and updated using the read data of the main memory key.

In this way, in a data processing device that partially has a memory protection function using a main memory key, only one access to the main memory can be made after one access to the main memory.

This is after the main memory key access by the first main memory access is completed. Therefore, in the case of a configuration in which the main memory and the main memory key storage are processed in the same access time, two access cycles to the main memory are determined by an access to the main memory key storage. This will result in
Main memory key access will affect data access to main memory.

Conventionally, as a method of reducing the influence that main memory key access has on the main memory device, for example, Japanese Patent Application Laid-Open No. 58-15019
As shown in No. 6, the main memory key storage section is
It is known to process main memory key access at high speed by configuring it with an AM or by configuring a high speed RAM as a copy of a part of the main memory key storage section.

[Problem that the invention seeks to solve]

In the above conventional technology, the main memory key storage section is a high-speed RAM.
In this method, as the capacity of the main storage device increases, the main memory key storage section also needs to have a large capacity with high-speed RAM. In addition, high-speed R
In the AM method, the logic for ensuring consistency between the main memory key in the main memory key storage unit and its copy main memory key becomes complicated, and the entire main memory key control logic group becomes complicated. In either case, cost and construction problems arise.

An object of the present invention is to provide a structure in which the main memory device and the main memory key storage section are processed in the same access time.
The purpose is to reduce the influence that main memory key access has on data access to the main memory.

[Means for solving problems]

The purpose of the above is to have a main memory key holding register, instead of performing both read and write access to the main memory key memory each time the main memory is accessed, and to is accessed and the main memory key is saved in the main memory key holding register, and when the operand first accesses the main memory, the main memory key storage section is not accessed for reading, and the main memory key is saved in the main memory key holding register. The main memory key that has been saved is used, and only write access is made to the main memory key storage section. Furthermore, when the main memory is accessed for the second time or later, the main memory key is not accessed until the page is exceeded.

[For production]

When writing data to the main memory, the main memory cannot be accessed for writing unless the data to be written is prepared, but it is possible to access the main memory for reading data. For this reason.

Before executing an instruction, if the instruction is an instruction that accesses data in the main memory, it performs read access to the main memory and the main memory key storage section and stores the main memory key in the main memory key holding register. By using the main memory key holding register when accessing the main memory of the operand in the execution of an instruction, accesses to the main memory key storage section can be reduced. In addition, since memory protection, references, and changes to the main memory are recorded on a page-by-page basis, access to the main memory key during instruction execution only needs to be made on the first access to the main memory or when a page has been exceeded. It is not necessary when accessing the main memory other than the above. When accessing the main memory when exceeding a page, two accesses are required to read and write to the main memory key storage section, but the page size is smaller than the data width processed in one main memory access. 2048 bytes or 40
Since it is large at 93 bytes, it does not pose a problem in terms of performance.

Therefore, main memory key accesses when accessing the main memory can be reduced. Thereby, even in a configuration where the main memory and the main memory key storage section are processed in the same access time, the influence of main memory key access on data access to the main memory is reduced. Can be done.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention, in which a main memory device 1 (MS), a main memory control section 10 (MSC), a main memory key storage section 2 (KS), a main memory key control section 20 (
KSC), main memory key holding register 2 for the first operand
1 (KSDR'F), main memory key register 22 (
KSDR), valid flag register 22 (KSDFV)
, a-fold circuit 24 (S E L), comparison circuit 25 (C
OMP), real address register 3 (PAR), and protection key register 4 (PKEY).

Logical address update unit 5 (AA), execution control unit 6 (ES
Consists of U). In the following explanation, the data processing device performs multiple processing of instructions by pipeline control, and reading and writing data to and from main memory 1 (MS) and main memory key storage 2 (KS) each requires one cycle. shall be.

First, let us briefly explain the control stages in pipeline processing using Figure 5. The stage shown by the 0-dot line is the advance control stage controlled by hardware, and the stage shown by the solid line is the execution stage controlled by the microprogram. . The D stage of the instruction A is a stage for decoding what instruction A is.The 0M stage is a stage for calculating the address of the operand.At this stage, the logical address of the operand of the instruction A is obtained.

The A stage is a stage for address conversion to obtain a real address from the logical address obtained in the M stage. In this A stage, data read access is made to the main memory and operand data is also prefetched at the same time.EU and E2 stages are execution stages controlled by a microprogram, and the E
The stage must be executed in cycles. In the A stage of instruction A, the D stage of the next instruction B is processed simultaneously, in the E stage, the M stage of the next instruction B is processed simultaneously, and furthermore, in the E2 stage, the A stage of the next instruction B and the next instruction C of the next instruction B are processed. In this way, each of the D stages is processed in advance of the control stage.

The three stages M and A are processed in an overlapping manner for each instruction, and what emerges as an execution cycle is the execution cycle of each E stage controlled by the microprogram.

The operation of FIG. 1 will be explained below according to the time chart of FIG. 3 using a transfer logical operation instruction (abbreviated as MVC instruction) as an example. Note that the MVC instruction transfers the second operand data in the main memory to the main memory. This is an instruction to transfer data to the first operand position in the .

At the D stage of advance control, the instruction is an MVC instruction,
The hardware recognizes that there is an access to main storage. At the M stage, the addresses of the first and second operands are calculated, and the logical address of each operand is determined. The A stage is a stage for address conversion to obtain a real address from the logical address of the first operand obtained by the M stage.The obtained real address is set in PAR3, and read access is performed to MSI and KS2. , the first operand is originally an operand area for performing write access to the main memory, but it is possible to perform read access in advance. The main memory key of the first operand read in the A stage is set in KSDRF21 and KSDR22, and at the same time, KSDFV23 is set to logic "1". 5EL24 selects KSDR22 for the data signal line 100, GOMP25 selects the data signal line 100 and PKEY4
KSC20 performs a read protection check for the first operand by comparing data signal line 1 with R/P update.
Create write data using 00 and write to KSI.

E□ to En are execution stages by the microprogram. El is the first read access of the second operand and microcode "FESI" is issued. This microcode sets the real address of the second operand in PAR3.

A read access is made to MSI and KS2, and the main memory key of the successively issued second operand is set only to KSDR22. 5EL24 connects KS to data signal line 100
Select DR22, GOMP25 is data signal line 100
and PKEY4, and performs a read protection check for the second operand. KSC20 creates write data using data signal line 100 for R/P update, and
KSDR22 is a main memory key register that is updated every time a main memory key read access is made, regardless of the operand.

In the E2 stage, the KS1 access of El requires two cycles of reading and writing, so the microcode for accessing the main memory cannot be issued.%N.

E is the first write access stage to the first operand area, and the real address of the first operand is set in PAR3 by the microcode "5TFI", and the second operand data read in the E1 stage is written to M.
Written to the first operand area of SI. At this time K.S.
A logic 1'i n is set in DFV, which indicates that the main memory key of the first operand held in KSDRF 21 has already been read in the A stage of advance control and is valid. Therefore, in the E3 stage, there is no need for read access to KS2, and a write protection check can be performed immediately. 5EL24 selects KSDRF21 of the data signal line 100 and is compared with PKEY4. If the comparison results in a mismatch (write prohibited),
A logic "1" is output to the signal line 101 and sent to the MSCLO, and writing to the MSI is inhibited. Match (1F
In the case of write permission), a logic at Ops is output to the signal line 101, and when writing to the MSI is performed, the data signal line 100 indicates that the KSDRF21 is selected for updating the R/C/P of the main memory key. Create write data using , and write to KS2. At the end of writing to KS2, KSDFV is reset to logic “O” and K
SDRF21 is disabled.

In this way, the access to KS2 in the E3 stage is only a one-cycle write access. Therefore, it is possible to continue accessing the main memory in the primary E4 stage @E4. Each stage after E is a stage for reading and writing the second and first operands from the main storage device. Since the R/C/P update by main memory key access has already been completed during the first main memory access for the first and second operands (E, E3 stage), the main memory key access is No storage key access is required. Therefore, each stage after E4 can continuously access the MSI to read the second operand data and write data to the first operand area.

The microcode "EOP" of the En stage is a code indicating the end of the MVC instruction.

FIG. 4 is a time chart when the first operand exceeds a page due to updating of the logical address during continuous access to the main memory.

E stage is the stage of access beyond the page when updating the first operand address in AA5. At this time, a signal line 102 indicating that the access exceeds the page
Logic “1” is output to (PGCR3), and signal line 10
2 are sent to MSCIO, KSC20 and ESU6, respectively. When the signal line 102 is at logic "1", the KSC 20 accesses the KS2 using the real address set in the PAR3 and updates the KSDR22. 5EL24 selects KSDR22 as the data signal line, and a write protection check is performed on the next page of the first operand. Also, write access is performed to KS2 for R/C/P update. For MSClo, the signal line 102 is logic “1”
If so, control is performed to make writing to MSI wait until the write protection check for the primary page is completed, that is, writing to MSI becomes possible in the second cycle after the end of reading of KS2.

For main storage accesses that exceed pages in this way,
A two-cycle execution stage is required for MSl and KS2, and the second operand main storage access in the next Ej stage cannot be executed.

For this reason, when the signal line 102 is logic "1" and the next stage is access to the main memory, the ESU 6 inhibits execution of the next stage and makes one cycle dummy. This control makes it possible to process the E stage in two cycles, and the main storage access for the second operand of the E stage is performed in the next cycle after one cycle dummy.

The same applies when the second operand is an access that exceeds a page.

Although the MVC instruction was taken up in this embodiment, the A
By reading the main memory key in advance on the stage,
At the time of data write access to the main memory in the execution stage, main memory key access only requires R/C/P update write access. Therefore, after the store instruction accesses the main memory to write data, it is possible to perform a prefetch access to the main memory in the A stage of the next instruction. In this way, according to this embodiment, after the first data write access to the main memory of an operand, data read access to the main memory can be performed subsequently, thereby effectively shortening the execution cycle. Can be done.

Furthermore, it becomes possible to perform continuous read and write access to the main memory like an MVC instruction, and it becomes possible to process instructions for writing data to the main memory at high speed.

〔Effect of the invention〕

According to the present invention, the main memory key is accessed at the instruction execution stage by prefetching the main memory key before executing the instruction or by updating the main memory key only at the first access of a page. Therefore, the influence of main memory key access on data access to the main memory can be reduced without configuring the main memory key storage unit with a high-speed RAM. Therefore, the performance is improved and the main memory key storage section can be constructed at low cost, resulting in cost reduction.

[Brief explanation of the drawing]

゛\Figure 1 is a configuration diagram showing an embodiment of the present invention, Figure 2 is a diagram showing an example of the configuration of a main memory key, and Figures 3 and 4 are operations of the transfer logic operation instruction in Figure 1. FIG. 5 is a time chart illustrating an example of stages by pipeline control. 1... Main memory device, 2... Main memory key storage section. 3... Real address register, 4... Protection key register, 5... Logical address update section. 6... Execution control unit, 10... Main memory control unit, 20... Main memory key control unit, 21... First operand main memory key holding register, 22... Main memory key register, 23... Valid flag register, 24
...Selection circuit, 25...Comparison circuit.・−7ゝ＼ Representative patent attorney Katsuo Ogawa.・1) ゛(' Figure 1 Figure 2 "Illegal roll 1 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a pre-control data processing device that has a memory protection function using a main memory key and in which the execution of an instruction and the preprocessing of a subsequent instruction are processed in parallel, the main memory key storage unit is used in the pre-control stage. A main memory key holding register that holds read data corresponding to the operand by performing read access to the main memory key holding register, a valid flag register that indicates whether the contents of the main memory key holding register are valid or invalid, and a main memory of the execution stage. A selection circuit is provided for selecting read data from the main memory key storage section or the main memory key holding register corresponding to the operand at the time of key access. The valid flag register is set to indicate that the main memory key holding register is valid, and when the main memory key is accessed in the execution stage, if the valid flag register corresponding to the operand is set, the operand is The main memory key holding register corresponding to the main memory key holding register is selected by the selection circuit and used as the main memory key, and the valid flag register is reset to disable the main memory key holding register. Main memory key control method. (2) When accessing the main memory key in the execution stage, if the valid flag register corresponding to the operand is in the reset state, the read data of the main memory key storage section is selected by the selection circuit and used as the main memory key. A main memory key control method according to claim 1, wherein the main memory key control method is used.