JPS63102319U - - Google Patents
Info
- Publication number
- JPS63102319U JPS63102319U JP19627586U JP19627586U JPS63102319U JP S63102319 U JPS63102319 U JP S63102319U JP 19627586 U JP19627586 U JP 19627586U JP 19627586 U JP19627586 U JP 19627586U JP S63102319 U JPS63102319 U JP S63102319U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- amplification
- variable resistors
- level
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims description 15
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 15
- 238000001514 detection method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図ないし第３図はこの考案の増幅度調整装
置の１実施例を示し、第１図は一部のブロツク図
、第２図ａ〜ｈは動作説明用のタイミングチヤー
ト、第３図はモニタ表示装置の表示説明図、第４
図は信号増幅器の１例のブロツク図、第５図は従
来の増幅度調整装置のブロツク図、第６図は第５
図のスペクトラム・アナライザの表示画面の波形
説明図である。
１…信号増幅器、２…信号入力端子、３…信号
出力端子、４ａ，４ｂ…制御入力端子、６ａ，６
ｂ…増幅度設定用の可変抵抗、１１…パルス発生
回路、１２…制御信号作成回路、１３…信号発生
器、１６…選択信号出力回路、１７…検波回路。
Figures 1 to 3 show one embodiment of the amplification degree adjusting device of this invention, Figure 1 is a partial block diagram, Figures 2 a to h are timing charts for explaining the operation, and Figure 3 is a partial block diagram. Display explanatory diagram of monitor display device, 4th
The figure is a block diagram of an example of a signal amplifier, Figure 5 is a block diagram of a conventional amplification adjustment device, and Figure 6 is a block diagram of a conventional amplification adjustment device.
FIG. 3 is an explanatory diagram of waveforms on the display screen of the spectrum analyzer shown in FIG. DESCRIPTION OF SYMBOLS 1... Signal amplifier, 2... Signal input terminal, 3... Signal output terminal, 4a, 4b... Control input terminal, 6a, 6
b... Variable resistor for setting amplification level, 11... Pulse generation circuit, 12... Control signal creation circuit, 13... Signal generator, 16... Selection signal output circuit, 17... Detection circuit.
Claims (1)
れる１つまたは複数の増幅度設定用の可変抵抗を
有し、前記各可変抵抗の非選択時に基準増幅度に
設定されるとともに前記各可変抵抗の選択時に選
択された可変抵抗の抵抗値によつて定まる増幅度
に切換え設定される信号増幅器の前記各可変抵抗
の調整に用いられる増幅度調整装置において、 前記増幅器の出力信号を検波処理し、前記出力
信号の正または負検波レベルの検波信号を出力す
る検波回路と、 前記検波信号または該信号に比例したレベルの
信号によつて前記検波レベルをモニタ画面に掃引
表示するモニタ表示装置と、 前記モニタ画面の１掃引期間を時分割して設定
された単位期間毎に前記基準増幅度、前記各可変
抵抗に対応して設定された各指定増幅度それぞれ
の増幅によつて前記出力信号のレベルが同一にな
るようにレベル可変される調整用試験信号を前記
増幅器の信号入力端子に出力する信号発生器と、 前記試験信号のレベル可変に同期して前記各可
変抵抗を順次に選択する調整用の増幅度選択信号
を前記増幅器に出力する選択信号出力手段と を備えた増幅度調整装置。[Claims for Utility Model Registration] It has one or more variable resistors for setting the amplification degree selected by an externally inputted amplification degree selection signal, and when each of the variable resistors is not selected, the amplification degree is set to the reference amplification degree. In the amplification adjustment device used for adjusting each of the variable resistors of a signal amplifier, the amplification degree is set and switched to an amplification determined by the resistance value of the variable resistor selected at the time of selecting each of the variable resistors. a detection circuit that performs detection processing on the output signal of the output signal and outputs a detection signal with a positive or negative detection level of the output signal; and a detection circuit that sweeps the detection level on a monitor screen with the detection signal or a signal with a level proportional to the signal. a monitor display device for displaying, and amplification for each of the reference amplification degrees and each specified amplification degree set corresponding to each of the variable resistors for each unit period set by time-sharing one sweep period of the monitor screen; Therefore, a signal generator outputs an adjustment test signal whose level is varied so that the level of the output signal is the same to a signal input terminal of the amplifier, and each of the variable resistors in synchronization with the level change of the test signal. and selection signal output means for outputting to the amplifier an adjustment amplification selection signal for sequentially selecting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19627586U JPS63102319U (en) | 1986-12-20 | 1986-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19627586U JPS63102319U (en) | 1986-12-20 | 1986-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63102319U true JPS63102319U (en) | 1988-07-04 |
Family
ID=31154946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19627586U Pending JPS63102319U (en) | 1986-12-20 | 1986-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63102319U (en) |
-
1986
- 1986-12-20 JP JP19627586U patent/JPS63102319U/ja active Pending
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