JPS63102319A - High frequency electrode - Google Patents

High frequency electrode

Info

Publication number
JPS63102319A
JPS63102319A JP24878386A JP24878386A JPS63102319A JP S63102319 A JPS63102319 A JP S63102319A JP 24878386 A JP24878386 A JP 24878386A JP 24878386 A JP24878386 A JP 24878386A JP S63102319 A JPS63102319 A JP S63102319A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
gas
substrate
gas flow
treated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24878386A
Other languages
Japanese (ja)
Other versions
JPH0646627B2 (en
Inventor
Nobuhiro Kajikawa
梶川 信宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP61248783A priority Critical patent/JPH0646627B2/en
Publication of JPS63102319A publication Critical patent/JPS63102319A/en
Publication of JPH0646627B2 publication Critical patent/JPH0646627B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the temperature rise of the substrate to be treated such as a semiconductor wafer by a method wherein the title electrode is provided with an electrode plate on which the substrate to be treated is retained, through the intermediary of an insulative layer covering the surface of the substrate to be treated and also high frequency electric power will be applied thereto, and the gas flow passage through which cooling gas will be supplied on the reverse side of said substrate to be treated, and the dielectric withstand voltage of the above-mentioned gas flow passage is made higher than the dielectric withstand voltage of said insulative layer. CONSTITUTION:The substrate to be treated such as a semiconductor wafer 14 is arranged on the surface of an insulative layer 12, high frequency power is applied across an electrode plate 11 and an opposing electrode or the like, the sputtering gas circulated in a treatment chamber is activated, and the surface of the wafer 14 is etched. At this time, the gas same as the sputtering gas circulated in the treatment chamber is supplied from a cooling gas feeding device 13 as cooling gas on the reverse side of the semiconductor wafer 14 using a gas flow passage 15. Accordingly, the semiconductor wafer 14 can be cooled with said gas. Also, by bringing the dielectric withstand voltage of the gas flow passage 15 higher than the dielectric withstand voltage of the insulative layer 12, the abnormal electric discharge by the self-biased voltage generating on the surface of the semiconductor wafer 14 can be prevented.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) 本発明は、半導体ウェハ等の被処理基板の高周波エツチ
ング等に利用される高周波電極に関する。
DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a high-frequency electrode used for high-frequency etching of a substrate to be processed such as a semiconductor wafer.

(従来の技術) 一般に高周波電極は、半導体製造装置の処理室内等に配
置され、高周波電力により半導体ウニ八等の被処理基板
のエツチング処理を行なう高周波エツチング等に利用さ
れる。
(Prior Art) Generally, high-frequency electrodes are placed in processing chambers of semiconductor manufacturing equipment, and used for high-frequency etching, etc., in which substrates to be processed, such as semiconductor urchins, are etched using high-frequency power.

第2図は、このような従来の高周波電極の一例として、
高周波エツチングを行なう半導体製造装置の処理室内に
配置される高周波電極を示すもので、この高周波電極は
、例えば円板状等に形成された電極板1と、例えば石英
ガラス等からなり、電極板1の表面を覆う絶縁体層2と
から構成されている。
Figure 2 shows an example of such a conventional high-frequency electrode.
This figure shows a high-frequency electrode placed in a processing chamber of a semiconductor manufacturing apparatus that performs high-frequency etching. An insulator layer 2 covers the surface of the insulating layer 2.

そして、絶縁体層2の表面に半導体ウェハ3等の被処理
基板が配置され、電極板1と図示しない対向電極等との
間に高周波電力が印加されて、この高周波電力により処
理室内に流通されるスパッタガスを活性化して半導体ウ
ェハ3表面をエツチングする。
A substrate to be processed, such as a semiconductor wafer 3, is placed on the surface of the insulator layer 2, and high-frequency power is applied between the electrode plate 1 and a counter electrode (not shown), and the high-frequency power is distributed into the processing chamber. The surface of the semiconductor wafer 3 is etched by activating the sputtering gas.

なお、電極板1の表面に絶縁体層2が配置されているの
は、イオン化されたスパッタガスと、電子との移動度の
差により半導体ウェハ3表面に数百から数キロボルト程
度の自己バイアス電圧が発生し、もし絶縁体層2がない
とこの自己バイアス電圧により半導体ウェハ3上に形成
された半導体素子がその電位勾配により特性劣化を起こ
すためである。
The insulator layer 2 is arranged on the surface of the electrode plate 1 because a self-bias voltage of several hundred to several kilovolts is applied to the surface of the semiconductor wafer 3 due to the difference in mobility between the ionized sputtering gas and the electrons. occurs, and if the insulator layer 2 were not present, this self-bias voltage would cause the characteristics of the semiconductor elements formed on the semiconductor wafer 3 to deteriorate due to the potential gradient.

(発明が解決しようとする問題点) しかしながら、上記説明の従来の高周波電極では、?!
Z 、F112板表m1を覆う石英ガラス等の絶縁体層
のため、半導体ウェハ等の被処理基板の放熱が悪くなり
、この被処理基板の温度が上昇する。このため、半導体
ウェハ上に形成された半導体デバイスに悪影響を与える
等被処理基板に悪影響を与−える。これを防ぐべく冷却
のために基板裏面にガスを導入するとこのガス流路の絶
縁耐圧が一般的には数Torrと比較的盲いガス圧のた
めガラス等の絶縁体層の絶縁耐圧より低くなり、このガ
ス流路を経由して処理基板と接地間で放電を生じ、ガラ
ス等絶縁体層か電気的に短絡されたと同じ状態になるた
め前述したように基板上の半導体素子を劣化させること
になるという問題がある。
(Problems to be Solved by the Invention) However, with the conventional high-frequency electrode described above, what is the problem? !
Because of the insulating layer such as quartz glass that covers the surface m1 of the F112 plate, heat dissipation from the substrate to be processed such as a semiconductor wafer becomes poor, and the temperature of the substrate to be processed increases. Therefore, it has an adverse effect on the substrate to be processed, such as adversely affecting the semiconductor devices formed on the semiconductor wafer. In order to prevent this, when gas is introduced to the back side of the substrate for cooling, the dielectric strength voltage of this gas flow path is generally a few Torr, which is relatively blind, and therefore becomes lower than the dielectric strength voltage of the insulating layer such as glass. A discharge occurs between the processed substrate and the ground via this gas flow path, resulting in the same state as if the insulating layer such as glass was electrically shorted, which leads to the deterioration of the semiconductor elements on the substrate as described above. There is a problem with becoming.

本発明は、かかる従来の事情に対処してなされたもので
、半導体ウェハ等の被処理基板の温度上昇を防止するこ
とができ、被処理基板に温度上昇によるM、影響を一す
−えることのない高周波電極を提供しようとするもので
ある。
The present invention has been made in response to such conventional circumstances, and is capable of preventing temperature rises of substrates to be processed, such as semiconductor wafers, and alleviating the effects of temperature increases on substrates to be processed. The aim is to provide a high-frequency electrode without

[発明の構成] (問題点を解決するための手段) すなわち本発明の高周波電極は、表面を覆う絶縁体層を
介して被処理基板を保持し高周波電力が印加される電極
板と、前記被処理基板裏面に冷却ガスを供給するガス流
路とを備え、前記ガス流路の絶縁耐電圧が前記絶縁体層
の絶縁耐電圧より高くなるよう構成されたことを特徴と
する。
[Structure of the Invention] (Means for Solving the Problems) That is, the high-frequency electrode of the present invention includes an electrode plate that holds a substrate to be processed through an insulating layer covering the surface and to which high-frequency power is applied, and an electrode plate to which high-frequency power is applied. A gas flow path for supplying cooling gas to the back surface of the processing substrate is provided, and the dielectric strength voltage of the gas flow path is higher than the dielectric strength voltage of the insulator layer.

(作 用) 本発明の高周波電極では、表面を覆う絶縁体層を介して
被処理基板を保持し、被処理基板裏面に冷却ガスを供給
するガス流路が形成されており、被処理基板を冷却する
ことができる。また、ガス流路の絶縁耐電圧が絶縁体層
の絶縁耐電圧より高くなるよう構成されているので、ガ
ス流路が放電パスとなって半導体ウェハと電極板との間
で異常放電が発生することがない。
(Function) In the high frequency electrode of the present invention, the substrate to be processed is held via an insulating layer covering the surface, and a gas flow path is formed on the back surface of the substrate to be processed to supply cooling gas. Can be cooled. In addition, since the dielectric strength voltage of the gas flow path is configured to be higher than the dielectric strength voltage of the insulator layer, the gas flow path becomes a discharge path and abnormal discharge occurs between the semiconductor wafer and the electrode plate. Never.

(実施例) 以下本発明の高周波電極を図面を参照して一実施例につ
いて説明する。
(Example) Hereinafter, one example of the high frequency electrode of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例の高周波電極を示すもので
、高周波エツチングを行なう半導体製造装置の処理室内
に配置されるものである。この高周波電極は、例えば円
板状等に形成された電極板11と、例えば主峰板11と
ほぼ同形の円板状の石英カラス等からなり、電極板11
の表面を覆う絶縁体層12と、冷却ガス供給装置13に
一端を接続され、絶縁体層12表面に配置された半導体
ウェハ14の裏面に冷却ガスを供給するガス流路15と
から構成されている。
FIG. 1 shows a high frequency electrode according to an embodiment of the present invention, which is placed in a processing chamber of a semiconductor manufacturing apparatus that performs high frequency etching. This high-frequency electrode consists of an electrode plate 11 formed, for example, in the shape of a disk, and a quartz glass or the like in the shape of a disk, for example, approximately the same shape as the main peak plate 11.
It is composed of an insulating layer 12 that covers the surface of the insulating layer 12, and a gas passage 15 that is connected at one end to a cooling gas supply device 13 and supplies cooling gas to the back surface of the semiconductor wafer 14 disposed on the surface of the insulating layer 12. There is.

また、ガス流路15は、冷却ガス供給装置13から高周
波電極までの外部配管15aと、この外部配管15aか
ら高周波電極内を通り、絶縁体層12表面に配置された
半導体ウェハ14の裏面までの内部配管15bとから構
成されている。
Further, the gas flow path 15 includes an external pipe 15a from the cooling gas supply device 13 to the high-frequency electrode, and from this external pipe 15a through the high-frequency electrode to the back surface of the semiconductor wafer 14 placed on the surface of the insulator layer 12. It is composed of an internal pipe 15b.

外部配管15aは、絶縁体層12の周縁部において内部
配管15bと接続されており、内部配管15bは、絶縁
体層12内を通り、絶縁体層12のほぼ中央部から絶縁
体層12の表面へ向けて形成されている。絶縁体N11
2表面には、この表面に配置される半導体ウェハ14よ
りやや小径の凹部12aが形成されており、外部配管1
5aおよび内部配管15bを経て、絶縁体層12のほぼ
中央部から絶縁体層12の表面へ向けて流出した冷却ガ
スは、凹部12a内を半導体ウェハ14の裏面に接触し
ながら半導体ウェハ14の外周方向へ向かい、この外周
部の絶縁体層12と半導体ウェハ14との間から処理室
内へ流出する。
The external piping 15a is connected to the internal piping 15b at the periphery of the insulating layer 12, and the internal piping 15b passes through the insulating layer 12 from approximately the center of the insulating layer 12 to the surface of the insulating layer 12. is formed towards. Insulator N11
A recess 12a having a diameter slightly smaller than that of the semiconductor wafer 14 disposed on this surface is formed on the surface of the external piping 1.
5a and the internal pipe 15b, the cooling gas flows out from approximately the center of the insulating layer 12 toward the surface of the insulating layer 12, and the cooling gas flows inside the recess 12a and contacts the back surface of the semiconductor wafer 14 while flowing around the outer periphery of the semiconductor wafer 14. direction, and flows out into the processing chamber from between the insulator layer 12 and the semiconductor wafer 14 at the outer periphery.

なお、ガス流路15は、絶縁体層12より絶縁11iJ
 ’$、圧が高くなるように構成されている。これは、
ガス流路15が放電バスとなって、前述のようにイオン
化されたスパッタガスと電子との移動度の差により半導
体ウェハ14表面に生じた数百から数キロボルト程度の
自己バイアス電圧による異常放電が発生することを防止
するためである。
Note that the gas flow path 15 is more insulated than the insulator layer 12 by 11iJ.
'$, the pressure is configured to be high. this is,
The gas flow path 15 serves as a discharge bus, and abnormal discharge occurs due to the self-bias voltage of several hundred to several kilovolts generated on the surface of the semiconductor wafer 14 due to the mobility difference between the ionized sputtering gas and electrons as described above. This is to prevent this from occurring.

このように、ガス流路15の絶縁耐電圧を高くするため
には、この実施例に示すように、内部配管15bを電極
板11に接触させない、あるいは外部配管15aにコイ
ル状等の曲折部を設ける等して、ガス流路15の半導体
ウェハ14側の端部から他の導体に接触する部位までの
ガス流路15・長さを長くする。ガス流路15の径を細
くする。
In this way, in order to increase the dielectric strength voltage of the gas flow path 15, as shown in this embodiment, the internal piping 15b should not be brought into contact with the electrode plate 11, or the external piping 15a should have a bent part such as a coil shape. The length of the gas flow path 15 from the end of the gas flow path 15 on the semiconductor wafer 14 side to the portion that contacts another conductor is increased by providing a conductor. The diameter of the gas flow path 15 is reduced.

ガス流路15内での冷却ガスのガス圧を高くする等の方
法があり、これらの方法を組合せて絶縁耐電圧を高くし
ても、他の方法により絶縁耐電圧を高くしてもよい。
There are methods such as increasing the gas pressure of the cooling gas in the gas flow path 15, and the dielectric withstand voltage may be increased by combining these methods or by other methods.

上記構成のこの実施例の高周波電極では、絶縁体層12
の表面に半導体ウェハ14等の被処理基板が配置され、
電極板11と図示しない対向電極等との間に高周波電力
が印加されて、この高周波電力により処理室内に流通さ
れるスパッタガスを活性化して半導体ウェハ14表面を
エツチングする。この時、冷却ガス供給装置13からガ
ス流路15により半導体ウェハ14裏面に冷却ガスとし
て、処理室内に流通されるスパッタガスと同じガスが供
給される。したがって半導体ウェハ14をこのガスによ
って冷却することができ、半導体ウェハ14の温度上昇
により、半導体ウェハ14表面に形成された半導体デバ
イスに悪影響を与えることを防止することができる。
In the high frequency electrode of this embodiment having the above structure, the insulator layer 12
A substrate to be processed, such as a semiconductor wafer 14, is placed on the surface of the
High frequency power is applied between the electrode plate 11 and a counter electrode (not shown), etc., and the high frequency power activates the sputtering gas flowing into the processing chamber to etch the surface of the semiconductor wafer 14. At this time, the same gas as the sputtering gas flowing into the processing chamber is supplied from the cooling gas supply device 13 to the back surface of the semiconductor wafer 14 through the gas flow path 15 as a cooling gas. Therefore, the semiconductor wafer 14 can be cooled by this gas, and an increase in the temperature of the semiconductor wafer 14 can be prevented from adversely affecting the semiconductor devices formed on the surface of the semiconductor wafer 14.

また、ガス流路15の絶縁耐電圧を絶縁体rrj12の
絶縁耐電圧より高くしであるので、ガス流路15が放電
パスとなって、半導体ウェハ14表面に生じた自己バイ
アス電圧による異常放電が発生ずることを防止すること
ができる。
Furthermore, since the dielectric strength voltage of the gas flow path 15 is made higher than the dielectric strength voltage of the insulator rrj12, the gas flow path 15 becomes a discharge path, and abnormal discharge due to the self-bias voltage generated on the surface of the semiconductor wafer 14 is prevented. It is possible to prevent this from occurring.

[発明の効果] 上述のように、本発明の高周波電極では、半導体ウェハ
等の被処理基板の温度上昇を防止し、かつ半導体ウェハ
表面を電位的にフローティングにすることができ、被処
理基板に温度上昇による悪影響をテえることがない。
[Effects of the Invention] As described above, the high-frequency electrode of the present invention can prevent the temperature of the substrate to be processed, such as a semiconductor wafer, from rising, and can make the surface of the semiconductor wafer potential floating. There is no adverse effect due to temperature rise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の高周波電極を示す縦断面図
、第2図は従来の高周波電極を示す縦断面図である。 11・・・・・・電極板、12・・・・・・絶縁体層、
14・・・・・・半導体ウェハ、15・・・・・・ガス
流路。
FIG. 1 is a vertical cross-sectional view showing a high-frequency electrode according to an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view showing a conventional high-frequency electrode. 11... Electrode plate, 12... Insulator layer,
14... Semiconductor wafer, 15... Gas flow path.

Claims (1)

【特許請求の範囲】[Claims] (1)表面を覆う絶縁体層を介して被処理基板を保持し
高周波電力が印加される電極板と、前記被処理基板裏面
に冷却ガスを供給するガス流路とを備え、前記ガス流路
の絶縁耐電圧が前記絶縁体層の絶縁耐電圧より高くなる
よう構成されたことを特徴とする高周波電極。
(1) An electrode plate that holds a substrate to be processed through an insulator layer covering the surface and to which high frequency power is applied, and a gas flow path that supplies cooling gas to the back surface of the substrate to be processed, the gas flow path A high-frequency electrode characterized in that the dielectric withstand voltage of the insulator layer is higher than the dielectric withstand voltage of the insulator layer.
JP61248783A 1986-10-20 1986-10-20 Processor Expired - Lifetime JPH0646627B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61248783A JPH0646627B2 (en) 1986-10-20 1986-10-20 Processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61248783A JPH0646627B2 (en) 1986-10-20 1986-10-20 Processor

Publications (2)

Publication Number Publication Date
JPS63102319A true JPS63102319A (en) 1988-05-07
JPH0646627B2 JPH0646627B2 (en) 1994-06-15

Family

ID=17183326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61248783A Expired - Lifetime JPH0646627B2 (en) 1986-10-20 1986-10-20 Processor

Country Status (1)

Country Link
JP (1) JPH0646627B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5792304A (en) * 1993-09-16 1998-08-11 Hitachi, Ltd. Method of holding substrate and substrate holding system
WO2003046969A1 (en) * 2001-11-30 2003-06-05 Tokyo Electron Limited Processing device, and gas discharge suppressing member

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62252943A (en) * 1986-04-25 1987-11-04 Fujitsu Ltd Hight frequency plasma etching apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62252943A (en) * 1986-04-25 1987-11-04 Fujitsu Ltd Hight frequency plasma etching apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5792304A (en) * 1993-09-16 1998-08-11 Hitachi, Ltd. Method of holding substrate and substrate holding system
US5961774A (en) * 1993-09-16 1999-10-05 Hitachi, Ltd. Method of holding substrate and substrate holding system
WO2003046969A1 (en) * 2001-11-30 2003-06-05 Tokyo Electron Limited Processing device, and gas discharge suppressing member
CN1322557C (en) * 2001-11-30 2007-06-20 东京毅力科创株式会社 Processing apparatus and gas discharge suppressing member
JP2009218607A (en) * 2001-11-30 2009-09-24 Tokyo Electron Ltd Processing apparatus and gas discharge suppressing member
US7622017B2 (en) 2001-11-30 2009-11-24 Tokyo Electron Limited Processing apparatus and gas discharge suppressing member

Also Published As

Publication number Publication date
JPH0646627B2 (en) 1994-06-15

Similar Documents

Publication Publication Date Title
US20190198297A1 (en) Plasma processing apparatus and plasma processing method
KR100427459B1 (en) Electro-static chuck for preventing arc
US4968374A (en) Plasma etching apparatus with dielectrically isolated electrodes
US5255153A (en) Electrostatic chuck and plasma apparatus equipped therewith
CN100474521C (en) Temperature controlled hot edge ring assembly, and device comprising the same and the use thereof
KR100328135B1 (en) Inductively Coupled Plasma Reactor With Electrodes To Improve Plasma Ignition
US4384918A (en) Method and apparatus for dry etching and electrostatic chucking device used therein
US4184188A (en) Substrate clamping technique in IC fabrication processes
US20150200124A1 (en) Method of manufacturing semiconductor device
JP2002502550A (en) Apparatus for improving the coupling of power to a workpiece in a semiconductor wafer processing system
KR19990063844A (en) Method and device for electrostatic holding of dielectric material in vacuum processor
US20050120960A1 (en) Substrate holder for plasma processing
US3419761A (en) Method for depositing silicon nitride insulating films and electric devices incorporating such films
JPS60115226A (en) Substrate temperature control method
US20070227664A1 (en) Plasma processing apparatus and plasma processing method
JPH06244143A (en) Treating device
JPS63102319A (en) High frequency electrode
KR20050091854A (en) Focus ring of semiconductor wafer manufacturing device
JP2003100720A (en) Plasma apparatus
JP2851766B2 (en) Electrostatic chuck
JP2580791B2 (en) Vacuum processing equipment
JPH0670984B2 (en) Sample temperature control method and apparatus
JP3357737B2 (en) Discharge plasma processing equipment
JPH0476495B2 (en)
JP3485335B2 (en) Electrostatic chuck for plasma processing equipment

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term