JPS6299813U - - Google Patents
Info
- Publication number
- JPS6299813U JPS6299813U JP19130585U JP19130585U JPS6299813U JP S6299813 U JPS6299813 U JP S6299813U JP 19130585 U JP19130585 U JP 19130585U JP 19130585 U JP19130585 U JP 19130585U JP S6299813 U JPS6299813 U JP S6299813U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- signal
- output
- expander circuit
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
Landscapes
- Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
- Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
Description
第１図は、本案の一実施例を示す回路構成図、
第２図は従来の説明図でａは２入力の記録計、ｂ
は記録状態図、第３図は説明図で、ａは入力側に
信号圧縮のための演算器を取付けた状態図、ｂは
記録状態図、ｃは演算器の特性図である。
ＢＯはバイアス信号発生器、Ｔ１〜Ｔ４は端子
、ＶＲ１，ＶＲ２は抵抗器、Ｒｅは記録計。
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
Figure 2 is an explanatory diagram of the conventional system, where a is a two-input recorder, and b is a 2-input recorder.
3 is a recording state diagram, FIG. 3 is an explanatory diagram, a is a state diagram in which an arithmetic unit for signal compression is attached to the input side, b is a recording state diagram, and c is a characteristic diagram of the arithmetic unit. BO is a bias signal generator, T 1 to T 4 are terminals, VR 1 and VR 2 are resistors, and Re is a recorder.
Claims (1)
うなものに於て、前記信号を流すための第１の抵
抗器と、この第１の抵抗器の一方の出力端にその
一端が接続される第２の抵抗器と、この第２の抵
抗器の両端に接続され、この第２の抵抗器に一定
のバイアス電流を流すためのバイアス信号発生器
とを備え、前記第１の抵抗器の他方の出力端と前
記第２の抵抗器の他端側より出力を得るように構
成したことを特徴とするエキスパンダー回路。 In a device that compresses a measured signal and outputs it to a recorder, there is a first resistor for passing the signal, and one end of which is connected to one output end of the first resistor. a second resistor connected to both ends of the second resistor, and a bias signal generator connected to both ends of the second resistor to cause a constant bias current to flow through the second resistor; An expander circuit characterized in that the expander circuit is configured to obtain an output from the other output end and the other end of the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19130585U JPS6299813U (en) | 1985-12-12 | 1985-12-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19130585U JPS6299813U (en) | 1985-12-12 | 1985-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6299813U true JPS6299813U (en) | 1987-06-25 |
Family
ID=31145320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19130585U Pending JPS6299813U (en) | 1985-12-12 | 1985-12-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6299813U (en) |
-
1985
- 1985-12-12 JP JP19130585U patent/JPS6299813U/ja active Pending
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