JPS629741Y2 - - Google Patents
Info
- Publication number
- JPS629741Y2 JPS629741Y2 JP1980172970U JP17297080U JPS629741Y2 JP S629741 Y2 JPS629741 Y2 JP S629741Y2 JP 1980172970 U JP1980172970 U JP 1980172970U JP 17297080 U JP17297080 U JP 17297080U JP S629741 Y2 JPS629741 Y2 JP S629741Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- clip
- semiconductor device
- lead wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 29
- 230000017525 heat dissipation Effects 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 16
- 239000000919 ceramic Substances 0.000 description 5
- 230000005855 radiation Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は、半導体装置に関し、特には半導体チ
ツプの収納されたパツケージに対して複数のリー
ドと放熱フインを取付けた構成の半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure in which a plurality of leads and heat dissipation fins are attached to a package containing a semiconductor chip.
従来の半導体装置の多くは、第１図ａに示すよ
うに、半導体チツプを内部に収納したパツケージ
１の側表面に電極２を取り出し、この電極２にコ
バール等によりなるリード線３を銀−銅ロー材等
で取着していた。 In many conventional semiconductor devices, as shown in FIG. 1a, an electrode 2 is taken out on the side surface of a package 1 that houses a semiconductor chip inside, and a lead wire 3 made of Kovar or the like is connected to the electrode 2 using a silver-copper wire. It was attached with raw material etc.
また、従来の他の半導体装置におけるリード線
は、第１図ｂに示すように、その頭部がパツケー
ジ１をはさみ込むための開口部を有するクリツプ
状部分４となるように形成され、このクリツプ状
部分４よりリード線部分５が延出していた。この
場合、各電極２を、１個のリード線３′のクリツ
プ状部分４によつてはさみ込み、かつロー付け或
いは半田付けによつて固着していた。 Further, as shown in FIG. 1b, the lead wire in another conventional semiconductor device is formed so that its head becomes a clip-shaped portion 4 having an opening for sandwiching the package 1. A lead wire portion 5 extended from the shaped portion 4. In this case, each electrode 2 was sandwiched between the clip-shaped portions 4 of one lead wire 3' and fixed by brazing or soldering.
従つて、各リード線３′を逐一パツケージ１の
各電極２に取着しなければならず、作業性が極め
て悪かつた。しかも、リード線３′を各電極２に
逐一取付けるので、半田付けを行つてもなお両者
の結合強度は十分ではなかつた。 Therefore, each lead wire 3' must be attached to each electrode 2 of the package 1 one by one, resulting in extremely poor workability. Moreover, since the lead wires 3' are attached to each electrode 2 one by one, even after soldering, the bonding strength between the two is not sufficient.
また、第２図に示すように、従来のリード線３
がパツケージ１に予め一体的に形成されている場
合、半導体チツプ８の取付を容易にするため、リ
ード線３はパツケージ１のキヤツプ６とは反対側
に延出するように形成される必要があつた。その
ため、放熱フイン７はキヤツプ６側（半導体チツ
プ８の収納側）に設けねばならなかつた。従つ
て、半導体チツプ８からの放熱は、パツケージ１
のセラミツク基台９中を遠回りして放熱フイン７
の端部に伝搬するので、熱の伝搬径路が長く、放
熱効果が充分でなかつた。 In addition, as shown in Fig. 2, the conventional lead wire 3
If the lead wire 3 is formed integrally with the package 1 in advance, the lead wire 3 needs to be formed to extend to the opposite side of the package 1 from the cap 6 in order to facilitate the attachment of the semiconductor chip 8. Ta. Therefore, the heat radiation fins 7 had to be provided on the side of the cap 6 (the side where the semiconductor chip 8 is housed). Therefore, the heat dissipated from the semiconductor chip 8 is
Heat dissipation fins 7 are installed in a detour through the ceramic base 9.
Since the heat propagates to the end of the body, the heat propagation path is long and the heat dissipation effect is not sufficient.
本考案は従来の上述の欠点に鑑みて、リード線
のパツケージへの取付けの作業性を向上でき、か
つリード線と電極との結合強度を増強できるとと
もに、パツケージ内への半導体チツプの取付けが
容易なまま放熱効果を向上できるようにした半導
体装置を提供することを目的とする。 In view of the above-mentioned drawbacks of the conventional technology, the present invention improves the workability of attaching the lead wires to the package, increases the bonding strength between the lead wires and the electrodes, and makes it easier to attach the semiconductor chip inside the package. An object of the present invention is to provide a semiconductor device that can improve the heat dissipation effect without changing the heat dissipation effect.
本考案の半導体装置の特徴とするところは、ク
リツプ状部分と線状に延出した部分とよりなる複
数のリード線を絶縁物で一体化し、しかも、半導
体チツプの収納側とは反対側に放熱フインを設け
たパツケージに対して、上記一体化されたリード
線を所定の方向で嵌め込んだことである。 The semiconductor device of the present invention is characterized by integrating multiple lead wires, each consisting of a clip-shaped part and a linearly extending part, with an insulator, and dissipates heat on the side opposite to the side where the semiconductor chip is housed. The integrated lead wire is fitted in a predetermined direction into a package cage provided with fins.
以下、図面を参照して本考案の一実施例を説明
する。従来と同一部分は同一参照番号を付する。
第５図には本考案に係る半導体装置の全体構成
を、第３図にはリード部材の斜視図を、第４図に
はその断面図を示す。 An embodiment of the present invention will be described below with reference to the drawings. The same parts as before are given the same reference numbers.
FIG. 5 shows the overall structure of a semiconductor device according to the present invention, FIG. 3 shows a perspective view of a lead member, and FIG. 4 shows a sectional view thereof.
第３図において、リード線３を複数個そのクリ
ツプ状部分４が直線状に並ぶように配列して、ク
リツプ状部分４を樹脂等の絶縁物１０でモールド
化し、互いに接続する。第３図のリード部材の断
面図である第４図に示されるように、絶縁物１０
がクリツプ状部分４に設けられ、クリツプ状部分
４によつてパツケージ１の電極２をはさみ込める
ようにしてある。このようにすれば、複数個のリ
ード線のクリツプ状部分４を１回の操作にて、パ
ツケージ１の電極２に嵌め込めばよいので、リー
ド線３をパツケージ１に取着する際の作業性が向
上する。 In FIG. 3, a plurality of lead wires 3 are arranged so that their clip-shaped portions 4 are lined up in a straight line, and the clip-shaped portions 4 are molded with an insulating material 10 such as resin and connected to each other. As shown in FIG. 4, which is a cross-sectional view of the lead member in FIG.
is provided on the clip-shaped portion 4, so that the electrode 2 of the package 1 can be sandwiched between the clip-shaped portion 4. In this way, the clip-shaped portions 4 of a plurality of lead wires can be fitted into the electrodes 2 of the package 1 in a single operation, which improves work efficiency when attaching the lead wires 3 to the package 1. will improve.
また、複数のクリツプ状部分４とパツケージ１
とが結合するので、クリツプ状部分４を電極２に
半田付けしなくても十分な結合強度が得られる。 Also, a plurality of clip-shaped parts 4 and a package 1 are provided.
Therefore, sufficient bonding strength can be obtained without soldering the clip-shaped portion 4 to the electrode 2.
更に、絶縁物１０の両端部に、パツケージ１に
おける電極２の設けられた側面と隣接する側面に
嵌合するよう、それぞれガイド１１を設けた。こ
のようにすることにより、第３図に示したリード
部材をパツケージ１に取着する際に、位置合わせ
用治具が不用となる。 Furthermore, guides 11 were provided at both ends of the insulator 10 so as to fit into the side surfaces of the package 1 adjacent to the side surfaces on which the electrodes 2 were provided. By doing so, when attaching the lead member shown in FIG. 3 to the package 1, no positioning jig is required.
また、本実施例に係る半導体装置は、第５図に
示すように、半導体チツプ８をセラミツク基台９
に載置すると共に、その反対側の面に放熱フイン
７を配設し、その後に上記リード部材をパツケー
ジ１に嵌め込むことにより完成する。このような
組立てにあたつては、リード線３のリード線部分
５を半導体チツプ８の収納側に位置させることが
できるため、放熱フイン７を上記のようにセラミ
ツク基台９の裏面に容易に取付けることができ
る。このため、半導体チツプ８からの放熱はセラ
ミツク基台９中の最短距離を通つて放熱フイン７
に達するので、放熱効果は大幅に改善される。 Further, in the semiconductor device according to this embodiment, as shown in FIG. 5, the semiconductor chip 8 is mounted on a ceramic base 9.
At the same time, the heat dissipation fins 7 are placed on the opposite surface, and the lead member is then fitted into the package 1 to complete the package. In such an assembly, since the lead wire portion 5 of the lead wire 3 can be positioned on the storage side of the semiconductor chip 8, the heat dissipation fin 7 can be easily attached to the back surface of the ceramic base 9 as described above. Can be installed. Therefore, the heat from the semiconductor chip 8 is radiated through the heat radiation fin 7 through the shortest distance in the ceramic base 9.
, the heat dissipation effect is greatly improved.
以上説明したように本考案の半導体装置によれ
ば、リード線の取付け作業性を向上できると共
に、リード線と電極との結合強度を増すことがで
き、しかもパツケージ内への半導体チツプの取付
け容易性を維持したまま放熱効果を著しく高める
ことができる。 As explained above, according to the semiconductor device of the present invention, it is possible to improve the workability of attaching the lead wires, increase the bonding strength between the lead wires and the electrodes, and furthermore, it is possible to easily attach the semiconductor chip into the package. The heat dissipation effect can be significantly enhanced while maintaining the
第１図ａは従来の半導体装置においてリード線
がパツケージに取着された状態を示す斜視図、第
１図ｂは従来の他の半導体装置におけるクリツプ
状部分を持つリード線の斜視図、第２図は従来の
リード線と放熱フインとのパツケージに対する取
り付けを示す断面図、第３図は本考案の一実施例
に係るリード部材の斜視図、第４図は第３図に示
したリード部材の断面図、第５図は上記実施例に
係る半導体装置の全体構成を示す断面図である。
１……パツケージ、２……電極、３……リード
線、４……クリツプ状部分、５……リード線部
分、６……キヤツプ、７……放熱フイン、８……
半導体チツプ、９……セラミツク基台、１０……
絶縁物、１１……ガイド。
FIG. 1a is a perspective view showing a lead wire attached to a package in a conventional semiconductor device, FIG. 1b is a perspective view of a lead wire having a clip-shaped portion in another conventional semiconductor device, and FIG. 3 is a perspective view of a lead member according to an embodiment of the present invention, and FIG. 4 is a sectional view showing the attachment of a conventional lead wire and a heat radiation fin to a package. Cross-sectional view FIG. 5 is a cross-sectional view showing the overall structure of the semiconductor device according to the above embodiment. DESCRIPTION OF SYMBOLS 1...Package, 2...Electrode, 3...Lead wire, 4...Clip-shaped part, 5...Lead wire part, 6...Cap, 7...Radiating fin, 8...
Semiconductor chip, 9... Ceramic base, 10...
Insulators, 11...Guide.
Claims (1)
りなるリード線３を複数個一列に配列すると共
に、該複数個のリード線を絶縁物１０で一体化し
てなるリード部材と、 半導体チツプ８を収納し、該半導体チツプの収
納側とは反対側に放熱フイン７を設けたパツケー
ジ１とからなり、 前記半導体チツプ８の収納側に前記線状に延出
した部分５が位置するように、前記パツケージ１
に前記リード部材を嵌め込んだことを特徴とする
半導体装置。[Claims for Utility Model Registration] A plurality of lead wires 3 each consisting of a clip-shaped portion 4 and a linearly extending portion 5 are arranged in a line, and the plurality of lead wires are integrated with an insulator 10. and a package 1 which houses a semiconductor chip 8 and has heat dissipation fins 7 on the side opposite to the side where the semiconductor chip 8 is housed, and which extends linearly to the side where the semiconductor chip 8 is housed. Said package 1 such that portion 5 is located
A semiconductor device, wherein the lead member is fitted into the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980172970U JPS629741Y2 (en) | 1980-12-02 | 1980-12-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980172970U JPS629741Y2 (en) | 1980-12-02 | 1980-12-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5794959U JPS5794959U (en) | 1982-06-11 |
| JPS629741Y2 true JPS629741Y2 (en) | 1987-03-06 |
Family
ID=29531244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980172970U Expired JPS629741Y2 (en) | 1980-12-02 | 1980-12-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS629741Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0331085Y2 (en) * | 1985-05-07 | 1991-07-01 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5315787A (en) * | 1976-07-28 | 1978-02-14 | Fujitsu Ltd | Integrated circuit package |
-
1980
- 1980-12-02 JP JP1980172970U patent/JPS629741Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5315787A (en) * | 1976-07-28 | 1978-02-14 | Fujitsu Ltd | Integrated circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5794959U (en) | 1982-06-11 |
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