JPS629591A - Mos dynamic ram - Google Patents

Abstract

PURPOSE:To attain high-speed access by controlling an output timing of a row address buffer activating signal circuit in response to a CBR-enable signal to eliminate the need for retarding the row address buffer activating signal. CONSTITUTION:First-stage signals phi1, phi2 are fed to a CBR deciding circuit 4 from a RAS first stage signal generating circuit 1 and a CBR 1st-stage signal generating circuit 2 respectively, the level of the inverse of input column address clock CAS goes quickly to L more than the inverse of input row address clock RAS, the circuit 4 decides the CBR mode and generates a CBR-enable signal phi4. A row address buffer activating signal phi3 outputted from a row address buffer activating signal circuit 5A in response to the signal phi4 is outputted after the input of the signal phi4. Thus, it is not required to retard the signal phi3 to apply high-speed access to the RAM at the CBR mode using an internal address counter generation circuit 5 for refresh.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to a CAS BEFORE RAS REF using an internal address counter.
Regarding MOS dynamic RAM with RESHMODE.

[Conventional technology]

In recent years, MOS dynamic RAM has been increasing in capacity and speed, and its functions have been improved.8 For example, 1-transistor type MOS dynamic RAM
In 18K DRAM.

READ MODE, WRITE MODE, RE
AD MODIFY WRITE MODE, RAS-
ONLY-REFRES)I MODE and PAGE
There was a MODE function, but the integration degree was 4 times higher84
In K IIRAN, in addition to the above functions, CAS BEFORE RA using an internal address counter
S REFRESHMODE is added, PAGE
The NIBBLEMODE function was introduced instead of MODE, and especially in 256KDRAM, CAS BEFO using an internal address counter was introduced.
RE RAS REFRESHMODE has come to be adopted by most manufacturers.

CAS BEFORE using internal address counter
RAS REFRESHMODE is a mode in which the row address buffer circuit takes in the internal address signal generated by the internal address counter and performs refresh.
On the other hand, the mode that takes in external address signals and performs operations such as refresh, write, and read is called external address mode (EXTERNA).
L ADDRESS MODE) The following explanation will be given.

FIG. 5 is a circuit diagram of a conventional example, and FIGS. 6 and 7 are time charts showing the circuit operation.

This circuit generates a high level RAS first stage first stage signal sound when the external input clock RAS goes low level.
A first-stage signal generation circuit 1, a CBR first-stage signal generation circuit 2 that generates a high-level CBR first-stage signal φ2 when the external input clock CAS becomes a low level, and a high-level row address buffer activation when the RAS first-stage first-stage signal sound 1 becomes a high level. The row address buffer activation signal circuit 3 outputs the activation signal φ3, and when the CBR first stage signal φ2 is at the low level, the CBR enable signal φ4. Outputs the CBR disable signal φ, and
When the BR first stage signal φ2 is at a high level, the CBR enable signals φ4. When a high-level row address buffer activation signal φ3 is input to the CBR determination circuit 4 that outputs the CBR disable signal sound 5 and the internal address counter generation circuit 5 that generates the internal address signal φ6t (i=0 to n), Driven.

When the CBR enable signal φ4 is at high level, the internal address signal φ61 output from the internal address counter generation circuit 5 is converted into the address buffer output signal φ7! It is composed of (nil) row address buffer circuits 6 that output an external address signal Ai (i=0 to n) as an address buffer output signal φ71 when the CBR disable signal signal tone 5 is level.

First, the operation in external address mode will be explained using FIG. 6. When the external input clock RAS falls to low level, the RAS first stage signal φ! becomes high level, drives the RAS first stage first stage signal sound 1 row address buffer activation signal circuit 3, and makes the row address activation signal φ3 high level.

This row address activation signal φ3 drives the row address buffer circuit 6 to generate a row address output signal φ71. Since the input clock CAS is at high level,
The CBR first stage signal φ2 is at a low level, the CBR enable signal φ4 is at a low level, and the CBR disable signal tone 5 is at an high level.

In this case, row address buffer circuit 61 does not take in internal address signal φGl output from internal address counter generation circuit 5, but takes in external address signal Ai.

Next, the operation in the internal address mode will be explained using FIG. In this case, before the external input clock RAS falls to a low level, the external input clock CAS falls to a low level, and the CBR first stage signal φ2 becomes a high level. When the external input clock RAS falls to the low level, the RAS first stage first stage signal sound 1 becomes the high level. The CBR determination circuit 4 receives the RAS first stage signal φ! and the CBR first stage signal φ2 are input, but since the CBR first stage signal φ2 becomes high level quickly, the CBR enable signal φ4 becomes high level, and the CBR first stage signal φ2 becomes high level.
The BR disable signal signal tone becomes level 5. The row address buffer activation signal φ3 is driven by the RAS first stage first stage signal sound 1, becomes high level, drives the row address buffer circuit 6, and generates the row address output signal φ7t(j
-0 to n). In this case, since the CBR enable signal φ4 is at high level and the CBR disable signal is at low level, the row address buffer circuit 6 takes in the internal address signal φ61, which is the output signal of the internal address counter generation circuit 5, and the external address clock Does not incorporate AI.

[Problem that the invention seeks to solve]

In the conventional MOS dynamic RAM described above, the row address buffer circuit 6i (i=0 to n) outputs an internal address signal φ when the CBR enable signal φ4 is at a high level.
61 and takes in the external address signal Ai when the CBR enable signal φ4 is low level, so the CBR
After the determination circuit 4 has fully operated and the CBR enable signal sound 4 has been determined to be high or low, the signal φ3 that drives the row address buffer circuit 61 is applied.
If the signal does not go to a high level, the sixth layer of row address buffer circuits will malfunction and take in the external address signal Ai or the internal address signal φ6I.

In order to eliminate the above-mentioned malfunction, in a dynamic RAM equipped with an internal address counter, it is necessary to delay the row address buffer activation signal φ3, which is one of the important characteristics of the dynamic RAM. This results in a delay in the access time, which is a major problem, and hinders the realization of dynamic RAM, which is becoming faster.

[Means for solving problems]

The present invention has an input clock of RAS and CAS, and has an external address mode in which an external address signal is taken in, and an internal address mode in which an output signal from an internal address counter generation circuit is generated when the input clock CAS becomes a low level state earlier than the input clock RAS. In a MOS dynamic RAM that has an internal address mode that takes in address signals and performs refresh, in the internal address mode, C
The present invention is characterized in that it includes a row address buffer activation signal circuit that outputs a row address buffer activation signal after receiving a BR enable signal.

Therefore, in order to prevent the row address buffer circuit from malfunctioning, it is no longer necessary to delay the row address buffer activation signal as in the prior art, and a MOS dynamic RAM that can be accessed at high speed is realized.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the MOS dynamic RAM of the present invention, and FIGS. 2 and 3 are time charts showing the operation of the embodiment of FIG. 1 in external address mode and internal address mode, respectively. .

Row address buffer activation signal circuit 3A.

In addition to RAS first stage signal φ1, CBR first stage first stage signal upper 2B
When the R enable signal signal tone 4 is input, and the CBR first stage first stage signal is level 2, the CBR enable signal signal tone 4 is output.
The row address buffer activation signal φ3 is not activated until the RAS initial stage signal φl becomes a high level. The rest is the same as the conventional example shown in FIG.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3.

(1) In external address mode (Figure 2) When external input clock RAS falls to low level, RAS first stage signal φl goes to high level, RAS first stage signal φ1 drives row address buffer activation signal circuit 3A, and row address The activation signal φ3 is set to high level. Row address activation signal φ3 drives row address buffer circuit 61 to generate row address buffer signal φ71. Since the external input clock CAS is at a high level, the CBR first stage first stage signal is at the upper 2W level, and the CBR enable signal signal tone is at the 4W level.

CBR disable signal φ5 is at high level. In this case, the row address buffer circuit 6i (i-〇~n) receives the internal address signal φG! output from the internal address counter generation circuit 5. Without taking in (i-0~n),
Take in external address signal Ai (i=0 to n).

(2) Internal address mode (FIG. 3) Before the external human clock RAS falls to low level, the external human clock CAS falls to low level and the CBR first stage first stage signal becomes 2-high level. External input clock RAS
When the signal Φ1 falls to a low level, the RAS first stage signal Φ1 becomes a high level. The CBR determination circuit 4 receives the RAS first stage signal φ1.
Since the CBR first stage first stage signal is at a high level, the CBR enable signal tone 4 is at a low level and the CBR disable signal φ5 is at a low level. Further, the CBR first stage first stage signal 2BR enable signal φ4 is input to the row address buffer activation signal circuit 3A, and when the CBR first stage signal φ2 is at a high level, the CBR enable signal φ4 is input to the row address buffer activation signal circuit 3A.
Even if the RAS first stage signal φ1 becomes high level, the row address buffer activation signal φ
3. is no longer at a high level. Therefore, in the internal address mode, the row address buffer activation signal φ3 becomes high level after the CBR enable signal φ4 becomes high level, and the row address buffer circuit 61 is activated by the internal address counter generating circuit 5.
can stably capture the internal address signal φ61, which is the output signal of the row address output signal φ7.
! Output.

FIG. 4 is a circuit diagram of a specific embodiment of the row address buffer activation signal circuit 3A of FIG. 1.

In the external address mode, the CBR first stage signal φ2 is at a low level, and the node N4 is always at a high level. R.A.
S-system precharge signal φ2. is external input clock RA
This signal drops from high level to low level immediately when S goes low level, and is used to keep node '2+NS+N9 at high level and node '1+NIO at low level. When the RAS first stage signal φ5 becomes high level, node N6 is charged through transistor Q9, node N1 is set to high level, and transistor Q
4+Q5 to node N2. The charge of N5 is extracted, the level is set to low level, and the row address activation signal φ3 is set to high level.

Next, the operation in internal address mode will be described.

When external input clock RAS is at high level, node N2+
"So '9 is at high level, and nodes N1+N16 are at low level. When external input clock CAS becomes low level earlier than external human clock RAS, CBR first stage signal φ2 becomes high level, and node N becomes low level. External input When clock RAS becomes low level,
The RAS first stage signal φ1 goes high and the node N6 is charged, but even if one node N1 goes high, the gate of the transistor Q5 is at a low level, so the node N2 remains at a high level, and the row address activation signal φ3 is suppressed to low level. When the CBR enable signal φ4 becomes high level, the node 810 becomes high level and the node N9 becomes low level. Row address activation signal φ3
is considered a high level.

Therefore, it is possible to delay the row address buffer activation signal only in the internal address mode. Further, the cycle time required in the internal address mode is determined as the time from when the data of the memory cells connected by the word line selected by the X decoder is supplied to the digit line to when the amplification is completed by the sense amplifier.

The read cycle time in external address mode is
The data of the memory cells connected by the word line selected by the decoder is supplied to the digit line, and the digit line selected by the i-Y decoder, which is amplified by the sense amplifier, is connected to the I10 pass line and passes through the data output buffer. This is determined as the time it takes for the output to be output. Therefore, a delay in internal address mode cannot result in a cycle time delay.

〔Effect of the invention〕

As explained above, in the internal address mode, the present invention includes a row address buffer activation signal circuit that outputs a row address buffer activation signal after receiving a CBR enable signal, thereby preventing the row address buffer circuit from malfunctioning. In order to prevent this, it is no longer necessary to delay the row address buffer activation signal as in the conventional case, and there is an effect that a MOS dynamic RAM that can be accessed at high speed can be realized.

[Brief explanation of drawings]

FIG. 1 is a flow diagram of one embodiment of the MOS dynamic RAM of the present invention, FIGS. 2 and 3 are time charts showing the operation of FIG. 1, and FIG. 4 is the row address buffer activation of FIG. 1. FIG. 5 is a block diagram of a conventional example, and FIGS. 6 and 7 are time charts for explaining the operation of FIG. 5. 1: RAs first stage signal generation circuit, 2: CBR first stage signal generation circuit, 3A: Row address buffer activation signal circuit, 4:
CBR judgment circuit, 5: Internal address counter generation circuit, 61: Row address buffing circuit, RAS, CAS: External manual clock, φ,: RAS
First stage signal. φ2: CBR first stage signal, φ3: Row address buffer activation signal φ4: CBR
enable signal. φ5: CBR disable signal, $61 (i-0~n): Internal address, φ7t (
j-0 to n) Near address buffer output signal. Ai (i=0 to n): external address signal, φ, □: R
AS system pre-precharge signal t'' Neo: Node, Q, ~ Q2゜: Transistor, C,: Capacitive element. V: Power supply. Patent applicant: Nippon'ichikyikishiki Kaisha 5--, Agent: Hara Uchi, patent attorney Jin 4/°゛＼゛ - Figure 1 Figure 2 Figure 5 Figure 6

Claims (1)

[Claims] An external address mode that has @RAS@ and @CAS@ input clocks and takes in an external address signal, and an internal address mode that takes in an external address signal when the input clock @CAS@ becomes low level earlier than the input clock @RAS@ MO having an internal address mode that takes in an internal address signal, which is the output signal of the address counter generation circuit, and performs refreshing.
A MOS dynamic RAM comprising a row address buffer activation signal circuit that outputs a row address buffer activation signal after inputting a CBR enable signal in an internal address mode.