JPS6295623A - Keyboard display device - Google Patents

Abstract

PURPOSE:To decrease the repeating frequency of the same operation when the rise, the maintenance and evaluation are carried out with a system,by providing an automatic answering function to a keyboard display device for transfer of data with a host device. CONSTITUTION:The regular input data which is transferred when the rise, the maintenance and the evaluation are carried out by a host device 1 to a keyboard display device 6 is estimated as the estimated input data. Then the answer data is previously produced to said input data and stored in the 2nd memory circuit 106. The input data transferred from the device 1 is compared with the estimated input data stored in the circuit II 106 by a data comparison controller 109. When the coincidence is secured between both data, the corresponding answer data is sent to the device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a keyboard display device, and particularly to a data transfer control method with a host device.

INDUSTRIAL APPLICABILITY The present invention is suitable for use in a keyboard display device of an information processing system that transfers data to a host device in a conversational format using DMA control.

〔overview〕

The present invention provides a keyboard display device that performs system startup, maintenance, and evaluation in a conversational manner for data transfer with a host device, by creating and storing standard response data in advance and comparing it with input data from the host device. By providing an automatic response function that transfers the response data to the host device when these match, it reduces the frequency of operator key operations, reduces operation time and erroneous key operations, and improves overall system operation. It improves efficiency.

[Conventional technology]

Conventionally, this type of keyboard display device uses DMA to transfer data with a host device through an operator's conversation.
This is done through control.

FIG. 6 is a block diagram of a conventional keyboard display device 7. As shown in FIG. Input data sent from the host device 1 via the interface 2 is input to the host device interface control circuit 101, and is stored in the storage circuit 110 under the control of the main control logic circuit 202 and the DMA control circuit 103.
5 is written in order from the beginning. By interrupting the main control logic circuit 202 at preset time intervals by the interval interrupt circuit 104, the DMA control circuit 103
The main control logic circuit 202 transfers data written in the storage circuit 1105 and input from the host device 1 (hereinafter referred to as input data) to the display unit control circuit 107. The display section control circuit 107 displays this input data on the display section 4.

The operator recognizes the displayed input data and inputs the data manually from the keyboard section 5 in response to this. Manually input data (hereinafter referred to as response data) is sent to the storage circuit 1105 via the keyboard section control circuit 108 under the control of the main control logic circuit 202 and the DMA control circuit 103, and is stored in the host device 1 previously written. Write after the input data from.

The above-mentioned response data by manual input is sent to the main control logic circuit 2.
02 and the DMA control circuit 103, the memory circuit ■105
The data is sent from the host device interface control circuit 101 and transferred to the host device l.

Furthermore, as described above, by interrupting the main control logic circuit 202 of the interval interrupt circuit 104, the storage circuit
Since all the data stored in 05 is sent to the display unit control circuit 107, the input data from the host device 1 and the response data manually input from the keyboard unit are displayed.

In this case, the data displayed on the display section 4 is 1/2 of the total capacity of the storage circuit 105. In other words, if the storage capacity is for two images, one of the images is displayed.

When the capacity displayed on the display section 4 is filled with input data and response data, the displayed data moves by 172 capacities of the upper address of the storage circuit 1105.

In this case, the data displayed first is the memory circuit ■105.
Although it is written in, it is not displayed on the display section 4. However, as more data is input, the memory circuit ■1
When the full capacity of 05 is filled, the data is rewritten from the beginning of the memory circuit 105, so the previous data is erased and the data displayed on the display section 4 is also rewritten as described above.

[Problem that the invention seeks to solve]

However, with such conventional keyboard display devices, when performing system startup, maintenance, and system evaluation, it is often necessary to manually input the same data displayed on the display from the host device multiple times from the keyboard. There is a need to. For this reason, there are disadvantages in that it takes time to operate and is prone to operational errors.

SUMMARY OF THE INVENTION An object of the present invention is to solve this drawback and provide a keyboard display device that shortens operation time and reduces operational errors by having an automatic response function.

[Means for solving problems]

The keyboard display device of the present invention includes a circuit that stores response data expected in advance to be input from the keyboard section in response to input data transferred from a host device;
It is equipped with a circuit that compares the data transferred from the host device and displayed on the display with the aforementioned pre-stored response data, and when the data displayed on the display matches the pre-stored response data, the pre-stored response data is The feature is that response data is transferred to a higher-level device.

That is, the present invention provides a keyboard display device that is connected to a host device and includes display means for displaying input data transferred from the host device, and keyboard means for manually inputting response data to the host device.゛A circuit that stores input data from the keyboard means in advance, a comparison circuit that compares the display display data from the host device with the input data that has been stored in advance, and a matching output from this comparison circuit, The apparatus is characterized by comprising means for transmitting input data stored in advance in a circuit to the above-mentioned host device.

[Effect]

Since the typical input data transferred from the host device during system startup, maintenance, and evaluation can be assumed in advance, this assumed scheduled input data and response data thereto can be created in advance. Therefore, this planned input data and response data are manually input into the second storage circuit, and when the input data is transferred from the host device and this input data and the above planned input data match, the corresponding Controls the transfer of response data to the higher-level device. This can reduce the frequency of manual input operations by the operator.

〔Example〕

Next, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, the keyboard display device 6 includes:
A host device interface control circuit 101 that sends and receives various data to and from the host device l via the interface 2, a main control logic circuit 102 that controls the inside of this keyboard display device, and a DMA that controls the control of this main control logic circuit. 11 control circuit 103, an interval interrupt circuit 104 that interrupts the main control logic circuit 102 at preset time intervals, a display section control circuit 107 that controls the display section 4, and a keyboard section control circuit that controls the keyboard section 5. A memory circuit 105 stores input data from the circuit 108 and the host device 1 and corresponding response data manually input by the operator from the keyboard section 5 under the control of the main control logic circuit 102. connected.

Here, the features of the present invention include a memory circuit 106 that stores scheduled input data that is assumed to be input from the host device 1 and response data that is created in advance in response to the scheduled input data; A data comparison control circuit 109 is provided which compares the input data actually input from the device 1 with the planned input data, and when they match, controls the response data to be controlled by the main control logic circuit 102. It is in.

Next, FIG. 2 is an explanatory diagram of the operation of the memory circuit 1105, FIG. 3 is an explanatory diagram of the operation of the memory circuit 106, FIG. 4 is an explanatory diagram of the operation of the main control logic circuit 102, and operation of the data comparison circuit 109. The operation of this embodiment will be explained using FIG. 5 and FIG. 1, which are explanatory diagrams.

In order to write the input data assumed in advance from the host device l and the corresponding response data, the operator manually sets the write mode in the main control logic circuit 102 using the keyboard unit 5.

Once the write mode is set, each data manually input from the keyboard section 5 is transferred to the keyboard section control circuit 108.
The main control logic circuit 102 and DMA1# control circuit 1
03, the data is written to the memory circuit I[106.

As shown in FIG. 4, writing to the memory circuit I[106 is carried out by sending the contents of the memory circuit ■ write address pointer 74 in the main control logic circuit 102 to the DMA control circuit 103,
DMA transfer is performed word by word between the keyboard section control circuit 108 and the memory circuit 106.

In this case, since the initial value of the memory circuit (2) write address pointer 74 indicates the first address of the memory circuit (2) 106, writing is performed from the first address.

When an operator manually inputs data, expected input data from the host device 1 (indicated by 51.53.55--1 in FIG. 3) and corresponding response data (indicated by
(shown as 52.54.56-・ in the figure),
Code 6 preset to indicate data boundaries
1 and 62 are manually entered at the end of the data.

When the writing is completed, the operator manually inputs data from the keyboard section 5 to cancel the writing mode of the main control logic circuit 102.

When input data is input from the host device 1, the data is transferred from the host device interface control circuit 101 to the main control logic circuit 102.
The contents of the memory circuit 1 write address pointer 71 in the main control logic circuit 102 and the data transfer range sent from the higher-level device are output to the DMA control circuit 103, and the upper-level device interface control circuit 101 and the memory circuit DMA transfer is performed between 1105 and 1105.

Since the memory circuit I write address pointer 71 indicates the start address of the memory circuit 105 in the initial state, it is written to area 3 in FIG. 2.

On the other hand, the main control logic circuit 102 writes the contents of the memory circuit I write address pointer 71 to the fifth point before starting the above-mentioned DMA transfer.
As shown in the figure, the memory circuit I of the data comparison control circuit 109
Comparison data is output to address pointer 81 and transferred to DMA.
After the transfer is completed, the data transfer range described above is added to the contents of the memory circuit I write address pointer 71, and the address pointer to be written next is updated. In this case, address 2 in Figure 2
2.

When the interval interrupt circuit 104 interrupts the main control logic circuit 102 at predetermined intervals, the main control logic circuit 102 transfers the contents of the display blade head address pointer 72 and the number of data transfer ranges for one screen to the DMA control circuit. 103, and the display data is transferred by DMA between the storage circuit 1105 and the display control circuit 107.

Since the display blade head address pointer 72 indicates the head address of the storage circuit 1105 in the initial state, the data will be transferred starting from the area 31 in FIG.

When the DMA transfer to the display section starts as described above, the data comparison control circuit 109 transfers the contents of the memory circuit 1105 indicated by the comparison data address pointer 81 and the memory circuit indicated by the comparison data address pointer 82. ■Storage circuit for the contents of 106 ■Comparison data address pointer 81 and storage circuit ■Comparison data address pointer 8
2 and are read and compared while updating each by +1.

Since the initial value of the memory circuit ■ comparison data address pointer 82 indicates the start address of the memory circuit ■ 106,
In this case, the contents of area 31 in FIG. 2 and scheduled input data 51 in FIG. 5 will be compared.

The comparison ends when the memory circuit ■ write address pointer 71 indicating the next address to be written to the memory circuit 1105 by the main control logic circuit 102 and the address indicated by the memory circuit I comparison data address pointer 81 match. Determine whether a match is found.

If a match is found, the comparison data control circuit 109 generates a code 61 in which the contents of the memory circuit 106 indicated by the comparison data address pointer 82 are set in advance.
After confirming that the code 61 is the same, the memory circuit 102 of the main control logic circuit 102 is stored until code 62 is detected at the memory circuit port 106 at the address of the memory circuit 105 indicated by the write address pointer 71. Memory circuit■
Transfer is performed while updating the comparison data address pointer 82 and the memory circuit I write address pointer 71 by +1, respectively.

In this case, the contents of 52 in FIG. 3 will be written into area 32 in FIG. 2.

On the other hand, the main control logic circuit 102 moves the contents of the memory circuit I write address pointer 71 to the host device data output address pointer 73 before updating by +1 as described above. That is, in this case, the address 22 in FIG. 2 will be entered into the host device data output address pointer 73.

When the preset code 62 is detected in the memory circuit n 106, the data comparison control circuit 109 terminates the transfer from the memory circuit IT 106 to the memory circuit 1105, and the data comparison control circuit 109 transfers the data to the output control logic circuit 102. is notified from the keyboard unit 5 as if the manual input has been completed. In this case, the data comparison control circuit 109
The preset code 62 is stored in the memory circuit 1105.
control so that it is not written to.

At this point, the memory circuit I comparison data address pointer 82 indicates the address 42 in FIG. 3, and the memory circuit I write address button 71 indicates the address 23.

As mentioned above, the iter-pulse interrupt circuit 104 is activated at predetermined intervals.
By the interruption to the main control logic circuit 102, the main control logic circuit 102 sends the contents of the display blade head address pointer 72 and the number of data transfer ranges for one screen to the DMA control circuit 103, and Since the display data is transferred by DMA between the display control circuits 107, the data in area 31 and the data in area 32 in FIG. 2, which are indicated by the display cutting head address pointer 72, are transferred.

When input data is input from the host device 1 to the host device interface control circuit 101 again, the same operation as described above is repeated.

Next, a case will be described in which the input data from the host device and the planned input data assumed in advance do not match.

If there is no match, the data comparison control circuit 109 connects the memory circuit ■Comparison data address pointer 81 and the memory circuit■
The comparison data address pointer 82 is not updated by +1 and is stopped as it is, and the data is transferred from the memory circuit 106 to the memory circuit 1.
Control is performed so that the scheduled transfer of response data to 105 and the transfer to host device 1 are not performed.

By the operator's manual input operation on the keyboard section 4, the comparison data address pointer 82 of the memory circuit 1 can be moved as follows under the control of the data comparison control circuit 109.

The data comparison control circuit 109 adds +1 and subtracts -1 to the memory circuit comparison data address pointer 82 until the code 62 preset according to the data contents is detected. Control is performed twice or until the first address is reached. That is, the storage circuit (1) moves the comparison data address pointer 82 from address 42 to address 43 or from address 42 to address 41;

As mentioned above, the operator's promised keyboard section 4
By manually inputting the address of the memory circuit comparison data address pointer 82, the operation procedure can be advanced or reversed, and the data to be compared with the host device written in advance in the memory circuit n106 can be arbitrarily selected. .

Further, the memory circuit ■ comparison data address pointer 82 is notified to the data comparison control circuit 109 via the keyboard section control circuit 108 by manual input from the keyboard section 4 promised by the operator in advance, and is set to the start address of the memory circuit ■ 106, that is, the initial value. It is also possible to control the return.

However, in this case, the operation from the host device will have to be redone.

In addition to the above-described operation example of the embodiment described above, the present invention can also perform other operations.

That is, as described above, when the storage circuit ■ comparison data address pointer 82 is moved, the data displayed on the display section 4 is changed to the storage circuit currently indicated ■ the storage circuit immediately before the comparison data address pointer 82 ■ 106 The data comparison control circuit 109 controls to display the output data when a match is found (in this case, the output data 54 is displayed).

At this time, it can be implemented so that the operator knows where the pointer address of the data to be compared next points.

Furthermore, when the display data returns to the beginning of the storage circuit 106, an arbitrary character indicating the beginning can be displayed.

Generally, the storage capacity of the storage circuit 11106 is the storage capacity of the storage circuit 110.
This is achieved regardless of the size of the storage capacity of 5.

As described above, in the present invention, the keyboard display device 6 can be provided with a changeover switch to change over the function corresponding to automatic response and the function according to the conventional example, and the changeover can be made at any time. Furthermore, by configuring this switching circuit so that it can be removed or attached to the bus 3, the present invention can be operated flexibly.

〔Effect of the invention〕

As explained above, the present invention provides a keyboard display device with an automatic response function during data transfer with a host device, thereby preventing the same operation from being repeated during system startup, maintenance, and evaluation. (1) Reduces operation time, (2) Prevents operational errors, (3) Frees the operator from operations, and (4) Reliably and quickly responds to the host device. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is an explanatory diagram of the operation of the memory circuit (2) of the above embodiment. FIG. 3 is an explanatory diagram of the operation of the memory circuit (2) of the above embodiment. FIG. 4 is an explanatory diagram of the operation of the main control logic circuit of the above embodiment. FIG. 5 shows the data comparison control circuit of the above embodiment. FIG. 6 is a block diagram of a conventional example. 1... Upper device, 2... Interface, 3...
Bus, 4...Display section, 5...Keyboard section, 6.7...Keyboard display device, 21
．． 23.25... Address of data input from the host device, 22.24... Address of data sent to the host device, 31.33.35... Area for writing input data from the host device. 32.34... Area for writing data to be sent to the host device, 41.42.43...
Address to be compared with data in memory circuit ①, 51.53.
55...Data to be compared with data in memory circuit H, 52
．． 54.56...Output data when a match is found, 6
1.62... preset code, 71...
Memory circuit I write address pointer, 72... Display blade start address pointer, 73... Upper device data output address pointer, 74... Memory circuit ■ Write address pointer, 81... Memory circuit I comparison data address pointer. , 82...Storage circuit ■Comparison data address pointer, 101...Upper device interface control circuit, 102.202...Main control logic circuit, 103...
・DMA control circuit, 104...Interval interrupt circuit, 105...Storage circuit 1.106...Storage circuit■
, 107...Display unit control circuit, 108...
Keyboard unit control circuit, 109...Data comparison control circuit.

Claims (1)

[Claims] (1) A keyboard display device connected to a host device and comprising display means for displaying input data transferred from the host device, and keyboard means for manually inputting response data to the host device; a circuit that stores the input data in advance; a comparison circuit that compares the display display data from the host device with the input data that is stored in advance; and a matching output from the comparison circuit that causes the data to be stored in the storage circuit in advance. A keyboard display device comprising: means for sending the input data inputted to the host device to the host device.