JPS6295584A - Dot matrix type display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a dot matrix display device (α) that realizes gradation display in a dot matrix display device using the CG system.

[Reluctance of invention]

The gradation display method in a dot matrix type display device using the CG method, especially the half-brightness display method, was published in Japanese Patent Application Laid-Open No. 58
As shown in Japanese Patent No. 57192, a method of realizing this using high-speed blinking display is known. However, in this method, since the entire character is blinked at high speed, there is a problem in that flicker becomes noticeable when one character has many dots.

The prior art and its problems will be explained in detail using a half-brightness display as an example using FIGS. 2 to 4.

FIG. 2 shows a block diagram of a liquid crystal display device that realizes half-brightness display using the CG method, in which 1 is a display address counter;
2 is an address bus, 3 is a rask address bus, and the display address counter 1 sequentially outputs the display address and the rask address to the display address bus 2 and the rask address bus 3, and counts the display addresses for one side (hereinafter referred to as this period). is called one screen period) ends.

Count the displayed addresses again from the beginning. 4 and 5 store character codes of characters to be displayed in code memory A and code memory B, respectively. 6 and 7 are character code A7 character code B, and code memory A4. The code memory B5 converts each character code stored at the address indicated by the display address given by the display address bus 2 into a character code A6.
, is output to character code B7. 8 is a character code A B switching device, 9 is a character code switching counter, 10 is a character code switching signal, and 11 is a display character code. Character code AB switching device 8 for switching between “high” and “low”
outputs the character code A6 to the display character code 11 when the character code switching signal 1o is PAHIPA, and outputs the character code B7 when it is PAKU-'' to the display character code 11.12 is the character pattern generator (C
aracter Generator (hereinafter abbreviated as CG), 13 is display character data, and CG12 is 1
Raster address bus 3 of the character indicated by display character code 11
The character data of the raster indicated by is output to the display character data 13. Reference numeral 14 denotes a display device having a dot matrix structure, typified by a liquid crystal display device, which displays the display character data 13 as visible information.

FIG. 3 is a diagram showing part of the information stored in the code memory A4 and code memory B5, and FIG. 3(a) shows the code memory A4 and the code memory B5.
, FIG. 3(b) shows the information stored in the code memory B5. FIG. 4 is a display pattern diagram displayed on the display device 14, and FIG. 4 (,) is a display pattern diagram when the code memory A4 stores the character code shown in FIG. 3 (,). ,
FIG. 4(b) is a display pattern diagram when the code memory B5 stores the character code shown in FIG. 3(b), and FIG. 4(C) is a display pattern diagram of FIG. A display pattern diagram that is displayed on the display device 13 as visible information when the display pattern diagram shown in b) is alternately and repeatedly displayed is shown.

In FIG. 2, the display address output from the display address counter 1 is given to a code memory A4 and a code memory B5 via a display address bus 2. The code memory A4 and the code memory B5 each output the character code stored at the display address indicated by the display address bus 2 as the character code A6 character code I37.

Now, when the character code switching signal 10 becomes "high", the character code A is selected as the display character code 11 by the character code AB switching device 8 and is applied to the CG 12. C
From G12, the character data indicated by the display character code 11, that is, the character code A6, is output as display character data 13 and displayed on the display device 14. Since the character code switching signal 10 remains in the same state during one screen period, the contents of the code memory A4 are continuously displayed for one screen on the display device 14, and in the next one screen period, the character code switching signal 10 is "
LOW", and the contents of the court memory B5 are continuously displayed for one screen on the display device.

Assume that the code memory A4 stores the character code shown in FIG. 3(a), and the code memory BS stores the character code shown in FIG. 3(b). If character code memory No. 10 is set to “high” during the first one screen period, character code AB
The switching device 8 selects the character code A by using the display device 14.
The information stored in the character code memory A, that is, the characters shown in FIG. 4(a) are displayed.

When the display address counter 1 finishes counting the display addresses for one screen, the character switching counter 9 changes the character code switching signal 10 from "high" to "low". As a result, the character code AB switching device 8 selects the character code B, so that the information stored in the character code memory B, that is, the characters shown in FIG. 4(b) are displayed on the display device 14. Since the character code switching counter 9 counts each time the display address counter 1 finishes counting display addresses for one screen, it repeatedly outputs "high" and "low" to the character code switching signal 10 in one screen period. Therefore, since the character code AB switching device 8 alternately selects character code 86 and character code B7 in one screen cycle, the character patterns shown in FIGS. 4(a) and 4(b) are displayed alternately on the display device 14. Ru. That is, among the displayed character patterns shown in Figure 4, characters A and C are always displayed and are displayed normally, but character B is not displayed when the contents of code memory A4 are displayed. However, when the contents of code memory B5 are displayed, other characters A are not displayed, as shown in FIG. 4(c).

This is a half-brightness display with lower brightness than C.

As explained above, in the conventional method, the entire character is linked at high speed and displayed at half brightness, so that the constituent dots of the character (the blacked out part of the displayed character pattern shown in Figure 4)
There was a problem that flicker was noticeable when there were many.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a dot matrix type display device which solves the problems of the prior art as described above and realizes gradation display in which printing power is not noticeable even when a character has many dots.

[Summary of the invention]

In order to achieve the above object, the present invention realizes gradation display with less noticeable flicker by dividing a character pattern read from CG and alternately plinking the divided blocks at high speed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail using the drawings. For convenience of explanation, the explanation will be limited to half-brightness display. FIG. 1 is a block diagram showing one embodiment of a liquid crystal display device using the present invention, and 1 to 3 and 12 to 14 are the same as in FIG. 2. 15 is a code memory, 16 is a character code, and the code memory 15 outputs the character code stored at the display address indicated by the display address bus 2 as the character code 16. 17 is an attribute memory; 18 is a half-brightness signal; the attribute memory 17 stores an attribute code indicating whether or not to display the character code stored at the same address on the code memory 15 in half-brightness on the display device 14; Similarly to the code memory 15, the attribute information stored at the display address indicated by the display address bus 2 is output as a half-brightness signal 18. When the half-brightness signal 18 is "high", the character code 16 read out at the same time is displayed at half-brightness, and when it is "low", the character code 16 is displayed normally.

19 is a gradation control device; 20 is display data; the gradation control bag @19 controls whether or not to blink the display character data 13 at high speed according to the half-brightness signal 18, and outputs the result as display data 20; 23 is a plink clock generator, 24
is the plink clock, and the plink clock generator 23
generates a plink clock 24 of one screen period.

Figure 5 is a diagram showing the reading of CG12, character code 1
6. 1 of character data indicated by raster address 3
Data for 8 raster dots is read from the CG 12.

FIG. 6 is a block diagram showing the gradation control device 19 in more detail, 21 is a raster address decoder, 22 is a raster up/down signal, and the rask address decoder 21 is a raster address decoder when the raster address bus 3 indicates Φ~3. The upper and lower signals 22 are set to "high", and when the raster address bus indicates 4 to 7, the raster upper and lower signals 22 are set to "low". 25 is a gate signal generator, 26 is a left gate signal, and 27 is a right gate signal. Yes, when the half-brightness signal 18 is "low", the left gate signal 26,
The right gate signal 27 is set to the "high" state indicating that the gate is ON, and when the half-brightness signal 18 is "high", the raster upper and lower signals 2 are turned on.
2. According to the plink clock 24, switching control of the left gate signal 26 and the right gate signal 27 between gate ON and gate OFF is performed. 28 is a left data gate device, 29 is a right data gate device, 2o is display data, and the left data gate device 28 and the right data gate device 29 respectively follow the left gate signal 26 and the right gate signal 27, and display character data 13.
The left 4 bits and right 4 bits are ON/OFF controlled to create display data 20.

FIG. 7 is a diagram showing the operation of the gate signal generation device 25 when the half-brightness signal 18 is "high", and FIG. 8 is a diagram showing the flow of data around the left data gate device 28 and the right data gate device 29. be.

FIG. 9 shows display character patterns, (a) is a display pattern diagram displayed in one screen period of even-numbered screens, (b) is a display pattern diagram displayed in one screen period of odd-numbered screens, and (c
) is a diagram showing a display pattern displayed on the display device 14 when the display patterns of (a) and (b) are displayed alternately.

In FIG. 1, a code memory 15 and an attribute memory 17 each contain character code information stored at an address indicated by the display address bus 2.

The half-brightness attribute information is output as a character code 16 and a half-brightness signal 18. Character code 16 output from code memory 15 is given to CG 12 together with raster address bus 3. For example, in CG12, if character code 16 indicates "code of character A" and raster address bus 3 indicates "2", as shown in FIG. 1 rusk 8 dots (5th
The portion surrounded by a bold line in the figure) is output from the CG 12 as display character data 13.

The display character data 13 is given to the gradation control device 19, and is divided into left data and right data as shown in FIG. 6, and is divided into left data gate device 28 and right data gate device 2, respectively.
given to 9. The gate signal generation device 25 generates raster upper and lower signals 22. The left gate signal 26 and right gate signal 27 are switched according to the link clock 24. For example, Fig. 7 (a
), when the raster address bus 3 indicates Φ~3, the plink clock 24 changes the "low" waiting gate signal 26 to "low" (display 0FF), and the right gate signal 2
7 as "high" (display ON), blink clock 24
When is "high", the left gate signal 26 is set to "high" and the right gate signal 27 is set to "low". That is, left-hand data and right-hand data are displayed in the form shown by the display character pattern in the figure. Also, as shown in FIG. 7(b), when the raster address bus 3 indicates 4 to 7, the plink clock 24 sets the low waiting gate signal 26 to high and the right gate signal 27 to low. ", the plink clock 24 is set to "high", the waiting gate signal 26 is set to "low", and the right gate signal 27 is set to "high". That is, the left side data and the right side data are displayed in the form shown by the display character pattern in the figure.

Left side data gate device 28, right side data gate device a
29, as shown in FIG. 8, the 8-bit display character data 13 is divided into two parts, 4 bits each on the left and right, and the 4 bits on the left are sent to the left data gate device 28, and the 4 bits on the right are sent to the right data gate device. Give to 29. Now, left gate signal 2
6 is set to ``high'' and the right gate signal 27 is set to ``low'', the left data gate device 28 turns on the display, and the left 4 bits of the display character data 13 are directly transferred to the display data 2.
Output as 4 bits on the left side of 0. On the other hand, in the right data gate device, the right gate signal 27 is "low".
Therefore, the display is turned off, and all bits are made into spaces, regardless of the right four bits of the display character data 13, as shown in the figure.

Due to the operation of the gradation control device 19 described above, when the half-brightness signal 18 is "high", the character pattern shown in FIG. However, when the plink clock 24 is "low", the character pattern shown in FIG. 9(b) is displayed.Assuming that the plink clock 24 repeats "high" and "low" in one screen cycle, , the display becomes half-brightness, as shown in FIG. 9(c).

In this half-brightness display, instead of blinking the entire character at high speed, the character is divided into four blocks, as shown in Fig. 9(a).
As shown in (b), the display is alternately blinked, resulting in a half-brightness display with less noticeable flicker.

Although one embodiment of the liquid crystal display device using the present invention has been described above, it is not limited to this example.
As shown in the figure, it is also possible to implement a method in which the raster is divided into four parts. Furthermore, in addition to the raster direction, it is also possible to divide the display character data 13 not only into two, but also into four, eight, etc., and finely control display ○N2 display OFF.

In addition, in this embodiment, the duty of the blink clock 24 is set to 1.
:1, and the period is 2 screen periods (each 1 screen period is ``
Although only ``high'' and ``low'' repeating) and half-brightness display were used, by using a plurality of blink clocks with different duties and cycles, it is possible to display different gradations.

〔Effect of the invention〕

As explained above, according to the present invention, characters are divided and the divided blocks are alternately blinked at high speed.
It is possible to realize a liquid crystal display capable of displaying gradation without noticeable flicker even when a character has many dots.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional example of a liquid crystal display that performs half-brightness display, and Fig. 3 is a code memory A and a code memory B.
FIG. 4 is an explanatory diagram showing the character code information stored in , FIG. 4 is a display character pattern diagram, FIG. 5 is an explanatory diagram showing reading of display character data of CG, and FIG. 6 is a half-brightness control device in FIG. 1. , FIG. 7 is an operation diagram of the gate signal generation device in FIG. 6, FIG. 8 is a flowchart of display data in the half-brightness control device, FIG. 9 is a display character pattern diagram according to the present invention, and FIG. The diagram is. It is a character pattern diagram when characters are further divided into smaller parts and displayed at half brightness. 1... Display address counter, 2... Display address bus, 3... Rask address bus, 13... Display character data, 15... Code memory, 16... Character code, 17... Attribute memory, 18...half R degree signal, 19...half brightness control device, 20...display data, 24...blink clock, 25...gate signal generator, 26...left gate Signal, 27...
Right gate signal, 28...left data gate device. 29...Right side data gate device. 14 and (υ Fig. 1 Fig. 2 Fig. 3 Section (α) (b) Section 4 (α) Diagram (α) Rask address bus 3 ψ ~
3 (b) Rasguadshi Suhas 3 4 ~ 7 Ding - γ A γ Ding - Kuchi - y Tower 8 Figure 9 (α) (b) (C) 107th (α) (b) (C)

Claims (1)

[Claims] 1. A display address counter, a display memory that stores a display character code, and a character that outputs the character pattern of the character indicated by the display character code read from the display memory according to the display address output from the display address counter. In a display device equipped with a pattern generator and a display device having a dot matrix structure that displays the character pattern as visible information, a gradation control device that divides the character pattern and alternately blinks the divided character patterns is provided. In addition, a dot matrix type display device is characterized in that gradation display is possible on the display device.