JPS6293972A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6293972A JPS6293972A JP60233218A JP23321885A JPS6293972A JP S6293972 A JPS6293972 A JP S6293972A JP 60233218 A JP60233218 A JP 60233218A JP 23321885 A JP23321885 A JP 23321885A JP S6293972 A JPS6293972 A JP S6293972A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- integrated circuit
- circuit device
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 abstract description 8
- 239000001301 oxygen Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- 230000001590 oxidative effect Effects 0.000 abstract 5
- 239000010408 film Substances 0.000 description 46
- 239000011148 porous material Substances 0.000 description 17
- 239000004020 conductor Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、゛Ｌ導体集＋ｊ１回路装置に関士ろものであ
り、特に、異なる結晶面をイｊする゛ヒ導体集ｆ５１”
、！路装誼に適用してＣｆ効な技術に関する（〕ので、
１うろ。[Detailed Description of the Invention] [Technical Field] The present invention relates to "L conductor collection + J1 circuit device", and in particular "L conductor collection F51" which conducts different crystal planes.
,! Regarding Cf effective technology when applied to road design (),
1 around.
［背景技術］
ダイナミック型うンダムアクセスメモリタ備えた゛撚導
体集積回路装置（以Ｆ、Ｄ Ｒ、へ＼１とい゛））は、
情報蓄積用客足素子とスイッチ素子との直列回路でメモ
リセルを構成している。このメモ１１セルは、高集積化
で面積か縮小する傾向にあり、情報拵積用容斌素子の情
報となるｊｔｆ ６１ｊ捨積猷が低ドする、この屯荷捨
積量の低ドは、（Ｉ徐にょろリフト工っ−を生じ易く、
情報の保持特性の信頼ｌ−ｉ″を低Ｉ：させる。[Background Art] A twisted conductor integrated circuit device (hereinafter referred to as F, D R, H\1)) equipped with a dynamic random access memory is
A memory cell is composed of a series circuit of an information storage element and a switch element. The area of this memo 11 cell tends to decrease as it becomes highly integrated, and the amount of data stored in the storage element for information storage decreases. (It is easy to cause gradual lifting,
The reliability l-i'' of information retention characteristics is made low I:.
ソコテ、高集（Ｉｌ（化を図ルトトもに、７ｉｉ ６１
＋ ｆｆ＋’ Ｔｄ Ｉｌｌを向上することがｉｊＪ能
な技術が知ら（している（特公昭５８−１２７３９号公
報）。この技術は、゛ｉ導体基板に設けられた細孔と、
この細孔に冶って設けられた絶縁膜と、この絶縁膜上部
に設けられた導電層とでＭｉｓ型情報蓄積用容ｉ累子が
構成されたものである。すなわち、半導体基板の深さ方
向を利用し、情報蓄積用容量素子の平面的な面積を縮小
するとともに、電荷蓄積量を向上するものである。Sokote, Takashu (Il), 7ii 61
+ff+' A technology capable of improving Td Ill is known (Japanese Patent Publication No. 58-12739).
An insulating film provided in this pore and a conductive layer provided on top of this insulating film constitute a Mis-type information storage capacitor. That is, by utilizing the depth direction of the semiconductor substrate, the planar area of the information storage capacitor element is reduced and the amount of charge storage is improved.
しかしながら、かかる技術における検討の結果、本発明
者は、前記情報蓄積用容量素子の電荷蓄積量を充分に向
上することができないので、集積度も充分に向上できな
いという問題点を見出した。However, as a result of studies on this technology, the inventors of the present invention found a problem in that the amount of charge storage in the information storage capacitive element cannot be sufficiently improved, and therefore the degree of integration cannot be sufficiently improved.
第１ｙエンチージヨンフラツトを（１００）面で構成す
ると、情報蓄積用容量素子の細孔の底面の結晶面が、（
１００）面で構成され、その側壁の結晶面が（１１０）
而で構成される。９００［°Ｃコで酸素分圧１．０［ａ
ｌ＝ｍｌのスチーム又はドライ酸化を行うと、この細孔
に沿って構成される絶縁膜は、底面と側壁で膜厚が異な
る。すなわち、酸化速度の結晶面依存度性があるため、
底部に比べで側壁の酸化シリコン膜々厚が１．７倍も厚
く構成される。この酸化反応は、シリコン−酸化１漠界
而における酸化反応が律速となる所謂反応律速で行われ
る。このため、電荷蓄積量の多゛ｒの面積を占る細孔の
側壁での電荷蓄積量を充分に確保することができない。When the first y encroachment flat is configured as a (100) plane, the crystal plane at the bottom of the pore of the information storage capacitive element is (
It is composed of (100) planes, and the crystal planes on its side walls are (110)
It consists of Oxygen partial pressure 1.0[a at 900[°C]
When 1=ml steam or dry oxidation is performed, the insulating film formed along the pores has different thicknesses at the bottom and side walls. In other words, since the oxidation rate depends on the crystal plane,
The silicon oxide films on the side walls are 1.7 times thicker than on the bottom. This oxidation reaction is carried out in a so-called rate-limiting manner, in which the oxidation reaction in the silicon-oxide interface is rate-limiting. For this reason, it is not possible to secure a sufficient amount of charge storage on the side walls of the pores, which occupy a large area of the charge storage amount.
［発明の目的］
本発明の目的は、異なる結晶面を有する半導体集積回路
装置であって、異なる結晶面に熱酸化技術で形成される
それぞれの酸化シリコン膜を、略同等の膜厚で構成する
ことが可能な技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a semiconductor integrated circuit device having different crystal planes, in which silicon oxide films formed on the different crystal planes by thermal oxidation technology have approximately the same thickness. Our goal is to provide technology that makes it possible.
本発明の他の目的は、ＤＲＡＭにおいて、情報蓄積用容
量素子の電荷蓄積量を向上し、その集積度を向上するこ
とが可能な技術を提供することにある。Another object of the present invention is to provide a technique that can improve the amount of charge stored in an information storage capacitive element and the degree of integration in a DRAM.
本発明の前記ならびにその他の目的と新規な特徴は１本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要コ
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.
すなわち、異なる結晶面を有する半導体集積回路装置で
あって、酸素の供給量が酸化速度を決定する所５’＋１
拡散律速で酸化反応が行える高温分圧酸化法を用いて、
面記異なる結晶面に略等同の膜厚の酸化シリコン膜を構
成する。That is, in a semiconductor integrated circuit device having different crystal planes, where the oxidation rate is determined by the amount of oxygen supplied, 5'+1
Using a high temperature partial pressure oxidation method that allows diffusion-controlled oxidation reactions,
Silicon oxide films having substantially the same thickness are formed on crystal planes with different surface registries.
これにより、ＤＲＡＭは、異なる結晶面で構成される細
孔を有する情報蓄積用容量素子の電荷蓄積量を向上する
ことができるので、集積度を向上することができる。Accordingly, in the DRAM, the amount of charge storage in the information storage capacitor element having pores formed of different crystal planes can be improved, and the degree of integration can be improved.
以下、本発明の構成について、本発明をＤＲＡＭに適用
した一実施例とともに説明する。Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a DRAM.
なお、実施例の全図において、同一機能を有するものは
同一符号を付け、そのくり返しの説明は省略する。In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
［実施例コ
本発明の一実施例であるＤＲＡＭのメモリセルを第１図
の一部断面斜視図で示す。[Embodiment] A memory cell of a DRAM which is an embodiment of the present invention is shown in a partially cross-sectional perspective view in FIG.
第１図において、１は単結晶シリコンからなるｐ−型の
半導体基板（又はウェル領域）、２はフィールド絶縁膜
、３はρ型のチャネルストッパ領域である。フィールド
絶縁膜２及びチャネルス１へソバ領域３は、メモリセル
間の半導体基板ｌの主面に設けられている。In FIG. 1, 1 is a p-type semiconductor substrate (or well region) made of single crystal silicon, 2 is a field insulating film, and 3 is a ρ-type channel stopper region. The field insulating film 2 and the channel region 3 are provided on the main surface of the semiconductor substrate l between the memory cells.
ＤＲＡＭのメモリセルは、情報ａ積用容１に索ＰＣとス
イッチ用ＭＴＳＦＥＴＱとの直列回路で構成されている
。The memory cell of the DRAM is constituted by a series circuit including an information storage capacity 1, a cable PC, and a switch MTSFETQ.
情報蓄積用容量素子Ｃは、細孔４、絶縁膜５及び導電プ
レート６で構成されるＭＩｓ型容量素子で構成されてい
る。The information storage capacitive element C is composed of an MIs type capacitive element composed of a pore 4, an insulating film 5, and a conductive plate 6.
細孔４ば、半導体基板１の主面から深さ方向に構成され
たものであり、情報′？！Ｉ積用容ｈｔ１３子Ｃの平面
的な面積を縮小するとともに、情報となる電荷蓄積量を
向上するように構成されている。細孔４は、第２図に示
すように、オリエンテーションフラットの結晶面を（＋
１０）面で構成すると、底面及びそれと平行な而の結晶
面が（１００）面で構成され、側壁の結晶面が（＋ １
０）面で構成される。The pores 4 are formed in the depth direction from the main surface of the semiconductor substrate 1, and contain information '? ! It is configured to reduce the planar area of the I product capacity ht13 child C and to improve the amount of charge storage which serves as information. As shown in Fig. 2, the pore 4 is arranged so that the crystal plane of the orientation flat is (+
10) plane, the bottom surface and the crystal plane parallel to it are composed of (100) planes, and the crystal planes of the side walls are (+1) planes.
0) consists of surfaces.
絶縁膜５は、細孔４に沿った半導体基板１の主面上部に
設けられており、酸素（０２）の供給量が酸化速度を決
定する所４１７拡散律速で酸化反応が行える高温分圧酸
化法を用いた酸化シリコン膜で構成されている。絶縁膜
５は、第３図の酸化膜厚の酸素分圧依存性図で示すよう
に、例えば、８５０〜９５０［℃］程度の酸化温度Ｔ、
と、 ０．１ ［ａｊｍコ程度又はそれ以下の酸素分圧
で構成する。The insulating film 5 is provided on the upper main surface of the semiconductor substrate 1 along the pores 4, and is a high-temperature partial pressure oxidation where the oxidation rate is determined by the amount of oxygen (02) supplied. It is composed of a silicon oxide film using a method. As shown in the oxygen partial pressure dependence diagram of the oxide film thickness in FIG.
and an oxygen partial pressure of about 0.1[ajm] or less.
このように構成される絶縁膜５は、細孔４の底面、それ
と平行な而及び側壁に略同等の膜厚、すなわち、（１１
０）結晶面と（１００）結晶面とか１．７倍よりも小さ
な０．９〜１．１倍程度の膜厚比で構成することができ
る。また、絶縁ＩＩ！５５は、１０００〜１１００［’
Ｃコ程度の高い酸化温度Ｔ２と、０．５ ［ａＬｍ］程
度の高い酸素分圧で構成しても、前記酸化温度Ｔ、と同
様の膜厚比を得ることができる。なお、酸化シリコン膜
は、ＣＶＤ技術、スパッタ技術等で形成される酸化シリ
コン膜に比べて良質であり、微小な情報となる電荷を蓄
積する情報蓄積用容量素子Ｃには最適な絶縁膜である。The insulating film 5 constructed in this manner has approximately the same thickness on the bottom surface of the pore 4, on the walls parallel to it, and on the side walls, that is, (11
The film thickness ratio between the 0) crystal plane and the (100) crystal plane can be about 0.9 to 1.1 times, which is smaller than 1.7 times. Also, insulation II! 55 is 1000-1100['
Even if the oxidation temperature T2 is as high as C and the oxygen partial pressure as high as 0.5 [aLm], the same film thickness ratio as the oxidation temperature T can be obtained. Note that the silicon oxide film is of better quality than silicon oxide films formed by CVD technology, sputtering technology, etc., and is the most suitable insulating film for the information storage capacitive element C that stores electric charge that becomes minute information. .
導電プレート６は１例えば、ＣＶ ｌ）技術で形成され
る多結晶シリコン膜に抵抗を低減するリン又はヒ素を拡
散したものを使用する。The conductive plate 6 is made of, for example, a polycrystalline silicon film formed by CV l) technology in which phosphorus or arsenic is diffused to reduce resistance.
このように、情報蓄積用容置索子Ｃの異なる結晶面を有
する細孔４に沿って略同等の膜ＪＩメで絶縁膜５を構成
し、細孔４の底面と同様に側壁の絶縁膜５を薄い膜厚で
構成できるので、情報となろ′１１ｉ荷蓄積＋ｉを向Ｊ
−することかできる。また、α線によるソフトエラーを
抑制し、情報蓄積用容量素子Ｃの平面的な面積を縮小し
てメモリセル＋Ｍｉ ＰＡを縮小することができるのて
、ｌ） ＲＡ ｘ・１の１７６集積化を図ることができ
る。In this way, the insulating film 5 is formed of substantially the same film JI along the pore 4 of the information storage container C having different crystal planes, and the insulating film 5 is formed on the side wall as well as the bottom surface of the pore 4. Since 5 can be constructed with a thin film thickness, it is possible to reduce the information and load accumulation +i.
- I can do something. In addition, it is possible to suppress soft errors caused by α rays, reduce the planar area of the information storage capacitive element C, and reduce the memory cell + Mi PA. can be achieved.
なお、本実施例では、（１１０）結晶面と（ｉｏｏ）ｊ
＜’ｒ結晶面に構成する絶縁膜５について説明してぃ＜
’ｓが。In addition, in this example, the (110) crystal plane and (ioo)j
<Explain the insulating film 5 formed on the r crystal plane<
's.
本発明は、（Ｉｌｌ）結晶面と（１００）結晶面とに構
成する酸化シリコン膜についても同様の効果をべするこ
とができる。すなわち、９００［’（’：］で酸７４分
１．ｉ二１ 。The present invention can achieve similar effects on silicon oxide films formed on the (Ill) crystal plane and the (100) crystal plane. That is, acid 74 min 1.i21 at 900['(':].
０ ［ａｊｍ］のスチーム又はドライ酸化では１．１倍
の膜厚比で酸化シリコン膜が構成されるが、本発明は、
１．４倍よりも小さな０．９〜１．１（９の膜厚比で酸
化シリコン膜を構成することができろ。In steam or dry oxidation of 0 [ajm], a silicon oxide film is formed with a film thickness ratio of 1.1 times, but in the present invention,
It is possible to form a silicon oxide film with a film thickness ratio of 0.9 to 1.1 (9), which is smaller than 1.4 times.
７は導電プレート６を覆う絶縁膜（例えば、酸化シリコ
ン膜）、８は細孔４の上面を平担化するために埋込まれ
た埋込層である。7 is an insulating film (for example, a silicon oxide film) that covers the conductive plate 6, and 8 is a buried layer buried in order to flatten the upper surface of the pore 4.
前記スイッチ用Ｍ Ｉ Ｓ ＦＥＴＱは、半導体基板１
、グーＩ−絶縁膜９、ゲートｔＳ！極１０、ソース領域
又はトレイン領域として使用される一対のｎ゛型の゛姓
導体領域１３及びその一部として使用されるｎ型の半導
体領域１１で構成されている。The switch M I S FETQ has a semiconductor substrate 1
, goo I-insulating film 9, gate tS! It consists of a pole 10, a pair of n-type conductor regions 13 used as a source region or a train region, and an n-type semiconductor region 11 used as a part thereof.
ゲート電極１０は、例えば多結晶シリコン膜の上部に高
融点金属シリサイＦ（ＭｏＳｉ２．Ｔｉ５ｉｚ 。The gate electrode 10 is made of, for example, a high melting point metal silicide F (MoSi2.Ti5iz) on the top of a polycrystalline silicon film.
ＴａＳｉ２．ＷＳｉ２）膜が設けられたポリサイド膜で
構成する。また、ゲート電極１ｏは、単層の多結晶シリ
コン膜、高融点金属（Ｍ ｏ 、 Ｔ ｉ 、 Ｔ ａ
、 Ｗ ）膜、高融点金属シリサイド膜又はそれらの
複合膜で構成する。このグー１−世極１０は、所定の方
向に配置された他のメモリセルのゲートｔｉ電極１ｏと
一体に構成されており、ツー１−線（ＷＬ）１０を構成
するようになっている。TaSi2. It is composed of a polycide film provided with a WSi2) film. Further, the gate electrode 1o is made of a single layer polycrystalline silicon film, a high melting point metal (Mo, Ti, Ta
, W) film, a high melting point metal silicide film, or a composite film thereof. This goo 1-world electrode 10 is constructed integrally with the gate ti electrode 1o of another memory cell arranged in a predetermined direction, and constitutes a two-world line (WL) 10.
低濃度の半導体領域１１は、高濃度の半導体領域１３と
チャネル形成領域との間に設けられておＭ Ｉ ５ＦＥ
ＴＱを構成するようになっている。The low concentration semiconductor region 11 is provided between the high concentration semiconductor region 13 and the channel forming region.
It is designed to constitute TQ.
１２はゲート電極１０の側部に自己整合で構成される不
純物導入用マスクであり、実質的なソース領域又はトレ
イン領域として使用される半導体領域１３を構成するよ
うになっている。Reference numeral 12 denotes an impurity introduction mask self-aligned on the side of the gate electrode 10, and is configured to form a semiconductor region 13 used as a substantial source region or train region.
１４はメモリセルを覆う絶縁膜、１５は所定の半導体領
域１３上の絶縁１漠１４を除去して設けられた接続孔で
ある。14 is an insulating film covering the memory cell, and 15 is a contact hole formed by removing the insulating layer 14 on a predetermined semiconductor region 13.
１６はデータ線ＤＩ−であり、接続孔１５を通して所定
のや導体領域１３と〒ヒ気的に接Ｑｌ、、ワード線１０
と異なる方向に延在するように、絶乾（膜１４の上部に
設けられている。Reference numeral 16 denotes a data line DI-, which is in air contact with a predetermined conductor region 13 through the connection hole 15, Ql, and the word line 10.
The bone-dry membrane (14) is provided on top of the membrane 14 so as to extend in different directions.
「効果コ
以」−説明したように、本願において開示された新規な
技術によ汎ば、以下に述へる効果を／ｊＪろことができ
る。"Effects" - As explained, the following effects can be achieved by the novel technology disclosed in this application.
（１）異なる結晶面を有する゛１１導体集積回路装置で
あって、拡散律速で酸化反応が行える高温分圧酸化法を
用いることにより、前記異なる結晶面に略等同の膜ｊ１
メの絶縁膜を構成することができろ。(1) A 11-conductor integrated circuit device having different crystal planes, by using a high temperature partial pressure oxidation method in which an oxidation reaction can be carried out under a diffusion-controlled manner, approximately the same film j1 is formed on the different crystal planes.
Is it possible to construct a metal insulating film?
（２）前記（１）により、ＤＲＡＭは、異なる結晶面で
構成される細孔を有する情報蓄積用容量素子の電荷蓄積
量を向」ニすることができるので、α線によるソフトエ
ラーを抑制することができる。(2) Due to (1) above, the DRAM can control the amount of charge storage in the information storage capacitive element that has pores composed of different crystal planes, thereby suppressing soft errors caused by α rays. be able to.
（３）前記（２）により、メモリセルの面積を縮小でき
るので、集積度を向上することができる。(3) According to (2) above, since the area of the memory cell can be reduced, the degree of integration can be improved.
以上、本発明者によってなされた発明を、前記実施例に
もとづき具体的に説明したが、本発明は、前記実施例に
限定されるものではなく、その要旨を逸脱しない範囲に
おいて、種々変形し得ることは勿論である。As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.
例えば、本発明は、ＤＲＡＭのメモリセルを構成する情
報蓄積用容量素子だけでなく、細孔又は細溝を利用する
容に素子に広く適用することができる。For example, the present invention can be widely applied not only to information storage capacitive elements constituting DRAM memory cells, but also to elements that utilize pores or narrow grooves.
また、本発明は、容量素子だけでなく、細孔又は細溝に
構成されるＭ Ｉ Ｓ ＦＥＴのゲート絶縁膜に適用し
てもよい。すなわち、異なる結晶面に延在して形成され
るゲート絶縁膜の膜厚を略同等にし、Ｍ Ｔ Ｓ ＦＥ
Ｔのしきい値電圧Ｖｔ、ｈを均一に構成することができ
る。Further, the present invention may be applied not only to capacitive elements but also to gate insulating films of MI S FETs configured in pores or narrow grooves. In other words, the thicknesses of the gate insulating films formed extending on different crystal planes are made approximately equal, and the M T S FE
The threshold voltages Vt and h of T can be made uniform.
第１図は、本発明の一実施例であるＤＲＡＭのメモリセ
ルの一部断面斜視図、
第２図は、第１図の所定の＋Ｍ造工程におけるメモリセ
ルの一部断面斜視図。
第３図は、本発明の一実施例を説明するための酸化膜厚
の酸素分圧依存性を示す図である。
図中、１・・・半導体基板、４・・細孔、５・・・絶縁
膜。
６・・・導電プレート、９・・・ゲート絶縁膜、１０・
・・ゲート電極又はワード線、１１．１３・・・半導体
領域、１６・・・データ線、Ｃ・・・情報蓄積用容量素
子、Ｑ・・・スイッチ用ＭＩＳＦＥＴである。FIG. 1 is a partial cross-sectional perspective view of a memory cell of a DRAM according to an embodiment of the present invention, and FIG. 2 is a partial cross-sectional perspective view of the memory cell in a predetermined +M manufacturing process of FIG. FIG. 3 is a diagram showing the dependence of oxide film thickness on oxygen partial pressure for explaining one embodiment of the present invention. In the figure, 1... semiconductor substrate, 4... pore, 5... insulating film. 6... Conductive plate, 9... Gate insulating film, 10.
. . . gate electrode or word line, 11. 13 . . . semiconductor region, 16 . . . data line, C .
Claims (1)
、前記異なる結晶面に熱酸化技術で形成されるそれぞれ
の酸化シリコン膜を、略等同の膜厚で構成してなること
を特徴とする半導体集積回路装置。 ２、前記異なる結晶面は、（１１０）面と（１００）面
とであり、それぞれの結晶面に構成される酸化シリコン
膜が、１．７倍よりも小さい膜厚比で構成されてなるこ
とを特徴とする特許請求の範囲第１項に記載の半導体集
積回路装置。 ３、前記異なる結晶面は、（１１１）面と（１００）面
とであり、それぞれの結晶面に構成される酸化シリコン
膜が、１．４倍よりも小さい膜厚比で構成されてなるこ
とを特徴とする特許請求の範囲第１項に記載の半導体集
積回路装置。 ４、前記酸化シリコン膜は、酸化反応が拡散律速で行わ
れる高温分圧酸化法で構成されてなることを特徴とする
特許請求の範囲第１項に記載の半導体集積回路装置。[Claims] 1. A semiconductor integrated circuit device having different crystal planes, in which silicon oxide films formed on the different crystal planes by thermal oxidation technology have approximately the same thickness. A semiconductor integrated circuit device characterized by: 2. The different crystal planes are a (110) plane and a (100) plane, and the silicon oxide film formed on each crystal plane is formed with a film thickness ratio smaller than 1.7 times. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The different crystal planes are a (111) plane and a (100) plane, and the silicon oxide film formed on each crystal plane is formed with a film thickness ratio smaller than 1.4 times. A semiconductor integrated circuit device according to claim 1, characterized in that: 4. The semiconductor integrated circuit device according to claim 1, wherein the silicon oxide film is formed by a high-temperature partial pressure oxidation method in which an oxidation reaction is performed at a diffusion rate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60233218A JPS6293972A (en) | 1985-10-21 | 1985-10-21 | Semiconductor integrated circuit device |
| KR1019860007490A KR870004514A (en) | 1985-10-21 | 1986-09-08 | Semiconductor integrated circuit device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60233218A JPS6293972A (en) | 1985-10-21 | 1985-10-21 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6293972A true JPS6293972A (en) | 1987-04-30 |
Family
ID=16951608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60233218A Pending JPS6293972A (en) | 1985-10-21 | 1985-10-21 | Semiconductor integrated circuit device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6293972A (en) |
| KR (1) | KR870004514A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044390A (en) * | 1999-07-22 | 2001-02-16 | Internatl Business Mach Corp <Ibm> | Vertical sidewall device aligned to crystal axis and manufacture thereof |
-
1985
- 1985-10-21 JP JP60233218A patent/JPS6293972A/en active Pending
-
1986
- 1986-09-08 KR KR1019860007490A patent/KR870004514A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044390A (en) * | 1999-07-22 | 2001-02-16 | Internatl Business Mach Corp <Ibm> | Vertical sidewall device aligned to crystal axis and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR870004514A (en) | 1987-05-11 |
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