JPS6292513A - Non-grounded type switched capacitor inductor - Google Patents

Abstract

PURPOSE:To make the value of an equivalent inductance accurate by using two sets of switched capacitors so as not to connect both the capacitors to the same terminal by means of the switch control at the same time. CONSTITUTION:Two switched capacitors comprising switches S3, S3', a capacitor 3 and switches S4, S4' and a capacitor 4 are provided. The switches S3, S3' and S4, S4' are controlled to connect one of the capacitors 3, 4 to input terminals 1, 2, while buffers 5, 6 are connected to respective output terminals 10, 11, the capacitors 3, 4 are not connected to the same terminal. Thus, an electric charge flows between signal terminals over the entire period of the sampling period and an error due to the interruption of the flow of electric charge is generated and the equivalent inductor of the non-grounded switched capacitor is made accurate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the construction of an ungrounded inductor using switched capacitor technology.

[Conventional technology]

Conventionally, this type of non-grounded switched capacitor inductor has been theoretically analyzed using two transformations. That is, the admittance Y(
The electric charge Q(8) flowing in s) is 0. If a bilinear transformation is applied to this, equation (1) becomes as follows. However, T is the sampling period.

The charge ΔQ flowing through the admittance Y(z) during the sampling period T is expressed as (3) where z”-1 is the unit delay operator.
ΔQ = Q(Z) −Q(Z) Z−1. Here, if the admittance Y(s) is due to the inductance L, then Y(s) = - (5) L, and when the conversion of (2) is applied here, it becomes. (6)
By substituting equation (4) into equation (4), a satisfying equation for ΔQ can be obtained.

As shown in Figure 3, an example of a conventional circuit that realizes the above equation (7) is the Switched Capacitor A' Shita Filter by Fujii, Electronics Bunko (28), published by Ohmsha in September 1980. 95, No. 5.
There is one shown in Figure 12.

According to FIG. 3, the two signal terminals 1 and 2, the output terminal of the buffer that generates an output of the same polarity as the output of the positive phase integrator circuit, and the output terminal of the one of the two buffers 5 and 6, By alternately connecting the entire capacitance to the output terminal, a non-grounded switched capacitor/mother inductor that satisfies equation (7) is realized. S4. S4'
, S9', S9 are switches, 7 is an operational amplifier, and %8 is a capacitor.

[Problem that the invention seeks to solve]

The conventional non-grounded switched capacitor inductor described above is realized by having a configuration in which charge movement between the two signal terminals is prevented during the period when the switch is connected to the buffer and positive-sequence integrating circuit side. The disadvantage is that the calculated inductance deviates from the theoretical value.

The present invention provides an inductor that solves the above problems.

[Means for solving problems]

The present invention provides a two-terminal circuit having two signal terminals,
It includes a set of buffers connected to each signal terminal and a positive-phase integrator circuit which takes the outputs of the two buffers as two inputs, and a first set of switches connects both ends to each of the signal terminals. and a first capacitor alternately connected to each of the output terminals of the buffer, and a second set of switches having both ends connected to each of the signal terminals, the output terminal of the positive phase integrating circuit, and the output terminal of the buffer. , second capacitors are alternately connected to the output terminal of the buffer that generates the output of the positive phase integrating circuit and the same polarity, and these two capacitors are simultaneously connected to the two signal terminals. This is a non-grounded switched capacitor-inductor, characterized in that the two switches are controlled so as not to be connected to the ground.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Signal terminals 1 and 2 are connected to buffer 5 and 60 input terminals. The buffers 5 and 6 have a sufficiently high input impedance, a sufficiently low output impedance, and a voltage gain of 1, and are constructed of, for example, a voltage follower. The terminals 31 and 32 at both ends of capacitor 3 are linked to signal terminals 1 and 2, respectively.
side and the buffer output terminal 10°]1 side alternately. The terminals 41 and 42 at both ends of the capacitor 4 are interlocked and alternately connected to the signal terminals 1 and 2, the output terminal 10 of the buffer 5, and the output terminal 12 of the operational amplifier 7 that constitutes the entire positive-phase integration circuit. .

The positive phase integrator circuit includes an amplifier 7 whose non-inverting input terminal is connected to the output terminal 11 of the buffer 6, a capacitor 8 connected between the inverting input terminal of the amplifier 7 and the output terminal 12, A capacitor 9 whose both ends terminals 9] and 92 are connected alternately to the output terminal 10 of the buffer 5 and the non-inverting input terminal of the operational amplifier 7, and to the output terminal 11 of the buffer 6 and the inverting input terminal of the operational amplifier 7, respectively. It consists of

Three sets of switches S3 in the circuit of FIG. S3'.

S4. S4', S9. The operation timing of S9' is set to the second
As shown in the figure.

All switches are controlled by switch control signals φ7. Regarding φ2, when the signal φ1 is at a high level, it is connected to the contact ■ side shown in FIG. 1, and when the signal φ2 is at a high level, it is connected to the contact ■ side. The signals φ and φ2 are in opposite phases and do not overlap.

According to this configuration, the switch S3. S3', S4. S4', S9. S9
' When the signal φ1 is at high level, the switch S3
, S3' are output terminals 10 and 11 of buffers 5 and 6, respectively.
connected to switch S4. S4' are signal terminals 1,
2 and the switch S9. S9' is each buffer 5
output terminal 10. Connected to the non-inverting terminal of the operational shift.

When the signal φ2 is at high level, the switches S3. S3' are connected to signal terminals 1 and 2, respectively, and switches 84 and S4
' are respectively connected to the output terminal 10 of the buffer 5 and the output terminal 12 of the operational amplifier 7, and switches S9 and 89' are connected to the output terminal 11 of the buffer 6 and the operational amplifier 1f0 inverting input terminal, respectively.

Next, the circuit operation will be explained with reference to FIG.

For convenience, the potential of the signal terminal 2 will be described as a reference (0 delt), but this is clearly not an essential restriction. The voltage of the signal terminal 1 is 'tV(Z), the output voltage of the operational amplifier 7 is Vo(z), and the value of the capacitor 3 is 1c.

Set the value of capacity 4 to 04. The value of capacitance 8 is C8, the value of capacitance 9 is fc
C7, the input voltage of the positive phase integrating circuit is V(z), and its output voltage V(z) is as well known. On the other hand, when the signal φ is at high level, the charge Q4(Z) charged in the capacitor 4 is Q4(Z) = CaV(z)
-(9) Signal φ2 is . (z) )
−... is α value. On the other hand, the charge Q3(Z) charged in the capacitor 3 is the signal φ4. Regardless of the change in φ2.

Q3(Z) = C, V(Z)
−・・It is α force. For the capacity 3, there is a switch S3. S
There is no rapid charge movement associated with 3' switching. Now, at the sampling time, when the signal φ2 transitions from a high level state to a high level state, the charge ΔQ flowing between signal terminals 1 and 2 during the sampling period T is the sum of the following three components. Given.

(1) Charge flowing through capacitor 4 while signal φ1 is high level (11) Charge O width flowing through capacitor 3 while signal φ2 is high level Momentary capacitance when signal φ2 changes from high level to signal φ1 high level If the values of capacitance 3 and capacitance 4 are made equal and C3=C4, then the sum of the charges in (i) and (11) above is equal to the signal terminal 1,
C5V(
z)-CsV(z)Z-1-(equal to Ll.

Next, the above zero-width charge is the difference between equation (9) and equation 01, and C
4V(z) C4(V(z) V.(z))=C4
■. (Z) = C3Vo(Z) 04. Therefore, the total charge ΔQ flowing between the signal terminals ] and 2 during the period T is the sum of equations 60 and 01 as ΔQ=C3V(z)−C3V
(z)Z-' +C3V0(z) -α→. If we substitute equation (8) here and rearrange it, we get the following. Here, if the gain of the positive phase integrator circuit is C9/C8i 4, then (C,
/C8=4), formula (g) becomes. This and (7)
The equivalent inductor L can be obtained by equating the equations. In other words, the circuit shown in FIG. 1 realizes an inductor.

From the above explanation, it is clear that in the conventional example shown in FIG. 3, since equation (2) does not hold, the equivalent inductor includes an error.

〔Effect of the invention〕

As explained above, the present invention realizes an accurate equivalent inductance value by providing two capacitors that are alternately connected to the signal terminals so that charge flows between the signal terminals during the entire sampling period. There is an effect that can be done.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a timing diagram showing the control of the switch shown in FIG. 3, and FIG. 3 is a conventional circuit diagram. 1.2... Signal terminal, 3, 4, 8, 9... Capacity, 5
, 6... Buffer, 7... Operational amplifier, S3. S3
', S4. S4', S9. S9'...Switch, 31
．． 32,4], 42,91.92...Switch common movable piece, 10.11...Buffer output terminal, 12.
...Op-amp output terminal. Figure 1 Figure 3

Claims (1)

[Claims] (1) A two-terminal circuit having two signal terminals, including a set of buffers connected to each signal terminal, and a positive-phase integrator circuit that uses the outputs of the two buffers as two inputs, and a first A first capacitor whose both ends are alternately connected to each of the signal terminals and each output terminal of the buffer by a set of switches, and a second capacitor whose both ends are connected to the signal terminal by a second set of switches. and a second capacitor alternately connected to the output terminal of the positive phase integrator circuit and the output terminal of the buffer that generates an output of the same polarity as the output of the positive phase integrator circuit. An ungrounded switched capacitor-inductor, characterized in that the two switches are controlled so that these two capacitors are not connected to the two signal terminals at the same time.