JPS6292341A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of an inversion layer, and to scale down the size of a chip by forming an inversion-layer generation preventive region to at least one part between active element regions and making the thickness of an insulating film on the preventive region thicker than that of other sections. CONSTITUTION:A film layer 8 consisting of a CVD oxide film, etc. is shaped onto a thermal oxide film 6 on a section positioned just under an aluminum wiring 7 and positioned on a collector layer held by a driver-step base diffusion layer 1 and a power-step base diffusion layer 3, a section where an inversion is most generated. Since the film layer 8 is attached, field strength due to the increase of a distance between the aluminum wiring 7 and the surface of a chip is reduced, thus preventing the generation of the inversion layer. Accordingly, a distance between the diffusion layer 1 and the diffusion layer 3 is shortened, thus scaling down the size of the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to prevention of inversion in semiconductor devices in which the generation of an inversion layer significantly deteriorates the characteristics of the semiconductor device.

[Conventional technology]

Conventionally, this type of inversion layer countermeasure method, taking a transistor as an example, involves diffusion to stop the inversion layer at a certain part during diffusion to form the emitter 2, as shown in Figure 2. While forming layer 5, the distance between the diffusion layers 1 and 3 was kept large in order to prevent a short circuit between the diffusion layers 1 and 3 due to the generation of an inversion layer.

[Problem that the invention seeks to solve]

The above-mentioned conventional methods for countering the inversion layer do not prevent the generation of the inversion layer itself, but rather suppress the elongation of the inversion layer, and also increase the chip size, which increases the cost of the chip itself. Another disadvantage is that the assembled parts, such as the lead frame on which the chip is mounted, are also large, resulting in high costs.

[Means for solving problems]

The semiconductor element with the inversion layer generation prevention structure of the present invention is provided on a thermal oxide film of about 5000A above the location where the generation of the inversion layer is thought to occur in the semiconductor element where the generation of the inversion layer adversely affects the characteristics. Furthermore, it has a thick film layer such as an oxide film of about 10000A.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

A semiconductor device according to an embodiment of the present invention is a Darlington transistor having two transistors in an l chip. The driver single-stage base diffusion layer 1 and the driver single-stage emitter diffusion layer 2 form a first-stage driver single-stage transistor, and the power single-stage space diffusion layer 3 and the power single-stage emitter diffusion layer 4 form a second-stage power single-stage transistor. There is. A Darlington transistor is formed by connecting the emitter of the first driver stage and the pace of the first power stage using the aluminum wiring 7. The above-mentioned driver construction I, aluminum wiring connecting the power and first stage emitter ll11
7 and above the collector layer sandwiched between the driver single-stage base diffusion layer 1 and the power single-stage base diffusion layer 3, that is, on the thermal oxide film 6 on the part where an inversion layer is most likely to occur. A film layer 8 such as a CVD oxide film is formed. By adding this film layer 8, the distance between the aluminum wiring a7 and the chip surface becomes larger, so the electric field strength becomes smaller, and the generation of an inversion layer can be prevented. Therefore, the driver single-stage base diffusion layer l
By reducing the distance between Q and the power single-stage base diffusion layer 3, the chip size can be reduced accordingly.

Further, by forming a guard link 5 which is formed to prevent a short circuit between the diffusion layers even if an inversion layer occurs, countermeasures against the inversion layer can be made more complete.

〔Effect of the invention〕

As explained above, the present invention has the effect of preventing the generation of an inversion layer and reducing the chip size by having a film layer such as an oxide film.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device with an anti-inversion film according to the present invention, and FIG. 2 is a sectional view of a semiconductor device according to the prior art. 1...Driver single-stage base diffusion layer, 2...
... Driver single-stage emitter diffusion layer, 3... Power single-stage base diffusion layer, 4... Power single-stage emitter diffusion layer, 5... Guard ring, 6... - Thermal oxide film, 7... Aluminum wiring, 8... Film layer, 9... Collector layer.

Claims (1)

[Claims] 1. A semiconductor device comprising an inversion layer generation prevention region at least in part between active element regions, and an insulating film on the region being thicker than in other parts.