JPS6289300A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To secure the actuation of an IC chip even though a semiconductor memory element has several defective pits by using the semiconductor memory element that is not selected by address information and a comparator which decides the coincidence between the contents of plural registers and the address information. CONSTITUTION:An action test of a memory is carried out from the outside of the memory by a control IC for CPU, etc. Thus it is decided that the action of a memory element corresponding to a specific address of a main memory MAIN 7 is defective. Then the MODE is set at L and the operation is switched to a write mode on an ADR.REG 3 and the addresses corresponding to the defective pits are written on the REG 3. Meanwhile it is always checked by comparison at the inside of the memory whether or not the address information decoded by a decoder is coincident with the contents of the REG 3 stored as a defective address through a COMP 4. If the coincidence is obtained, coincidence signals CEphi-CEm are used as the selection signals for the specific memory element of a SUBMEMORY 5. Then a memory circuit is switched to the SUB 5 from the MAIN 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memories.

[Conventional technology]

Conventionally, as shown in FIG. 6, in a semiconductor memory, information of an external address/code 21 is decoded into rows and columns by an address decoder 22 on a semiconductor memory chip selected by a CB (chip enable) signal 20, and the memory is then decoded into rows and columns. A specific memory element is selected from the circuit 23, and the information on the data node 25 is latched into the data latch circuit by the E and /W signals 24.

The latched information stored in the selected specific storage element is latched into the data latch circuit 27 via the internal data bus 26, and the fR information is outputted to the data bus 24. (Reading operation) [Problems to be solved by the invention] In the conventional semiconductor memory described above, a number of memory elements corresponding one-to-one to the number of bits of an address bus are manufactured on an IC chip. -Therefore, if even one of the memory elements on this IC chip fails, the IC chip becomes unusable.

[Means for solving problems]

The semiconductor memory device of the present invention includes a plurality of registers capable of storing address information, a semiconductor storage element that is not selected by the address bus, and a comparator for determining whether the contents of the plurality of registers match the address information. have.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in the present invention, in addition to the blocks constituting the conventional semiconductor memory, an address for storing information obtained by converting information on an external address bus 1 into internal address signals (ADRφ to ADRn) 2 is provided. Register (ADR, RgG
3, a comparator (abbreviated as COMF) 4 for comparing whether the contents of ADR and REG match the internal address signal, and a semiconductor memory element selected by the output signal of COMP. (SUBMEMOR, Y
) 5, and there is a MODE signal 6 as a sterilization signal of the internal block.

The general operation of this embodiment is as follows. First, we performed a memory operation test using a control IC such as a CPU from outside the memory, and found that the main memory (MAIN,
If it is found that the operation of the memory element corresponding to a specific at1/s of RY)7 is defective, MODE is set to "L"' to switch to the write mode to ADR and REG, and the address corresponding to the defective bit is written. During normal memory operation when writing to ADR, Rg(), MODE is set to "H" to enter the operating state. Inside the memory during operation, COMP is used to constantly compare whether the address information decoded by the decoder matches the internal information of ADR, RFiG, which was previously stored as a defective address. If there is a match, it will correspond to that address information, MAIN M
EMORY t7) RF 200 million R child is defective, so 5
This coincidence signal (CF)φ~CEm) is converted into 8'[JBMEM
ORY specific storage element selection No. 7 to signal [receive,
In this embodiment, where the memory circuit is switched from MAIN to SUB, ADR, FJG, and CO are switched in order to increase the operation speed.
The number of circuits for each of the bit numbers of MP, SUB MEMOR, and Y is kept the same, and the information in the internal address, ADR, and EG is compared at the same time.

The number of these circuits is the expected MAIN IIMOR
Insert 12 worth of defective bits of Y into the chip in advance.

Next, the operation of each block will be explained in more detail.

Figure 2 shows the circuit of the ADR and REG sections. This implementation'
In ρ1, the address bit length n is the number of 113G φ
It is a fixed configuration of m+11 up to Φm. In other words, if the number of defective bits is up to m+1, the chip appears to be operating normally from the outside. Furthermore, as an additional circuit, counter 8
8 and a decoder 9.

The operation of writing a defective address into this circuit is shown using the time chart of FIG. First, the reset signal 28 causes the counter 88 and F/Fφ to F/
The output of Fm becomes "0". Next, bad addresses 1 and 2
9 is output to ADRφ to ADRn from the external address bus. At this time, the output of the counter becomes 0'' and 89, and the output of the decoder becomes 'H''' only for φ, and the register group mφφ to mφn of ◆O becomes the 21 selection state. The information of DR, φ to ADRn is input into the register 13, and the output ADH, φn+ of F/F 6 is input.
Set 132 to 'H'.F/Fq62''H'
' state indicates that defective address information is not stored in the register group of φ. When another defective address tζ is detected, the logical combination of the DATAφ (1') LSB of the ATA bus) and the MODI signal is used as the count signal 33 of the counter, and the counter is incremented by one. Due to this signal, the output of the decoder becomes +1="H", and the register group 1 is in the selected state.The following operation is the same as at the time of the defective address 10, and the defective address register S of ADR,φ~A D n n information 34 is stored in the register group of N1,
F/F, = 1H" is set. Subsequently, m
+1 defective address can be stored in ADR6 EG.

Next, the operation of the COMP section shown in FIG. 1 will be shown in FIG. When MOD E='''L', the information of ADRφ~ADRn is supplied to the bus 14, and the information of ADRφ~ADRn in FIG.
It is connected to the R port and enters the defective address write mode. Address match detection is performed when ΔfODE="H", and when MODE="H", ADR and REG in FIG.
The information stored in ADRφφ to ADRφn
, ADR+φ~A D Rt n -ADRmφ~A
It is output to D Rm n. These news and ADRφ
, AD 几n rW report EX-NOII, do the logic,
Ka, enter DR, R, EG group F/Fm (7) Perform the logical product operation Jl: In this series of operations, if AD φ
When the information in ~AD and the information in any one register group of ADI (, -BEG match, one of CBφ ~ CEm becomes "H". This signal becomes 'I-I'. At the time, MAIN MEi”/10 AD on Y
~The memory element for the information on the AD card was defective, resulting in an IC.

Next, the operation of the 5uf3 MEMOR, Y5 shown in FIG. 1 will be described using an x5 diagram. In the real case, 1 pint x m) S u B M E LiOB
Although Y and 'fK are used, the operation is the same for any bit length. In FIG. 5, M1 to MW 15 to 17 are memory elements, and have a one-to-one correspondence with the coincidence signals CEφ to CEm of C0%1r shown in FIG. Sweet C
If Eφ is “H”, the ultimate element of Mφ is MAIN
(Instead of EMERY) (I will be making 5 works for 2 months.

In other words, CFJφ・CE-MODE-R/W=“H”
Then, the clear information of Mφ is output to DA'L'A-BuS18, and if cgφ-CE-R, /W="H", then MφKDAT
The information on A-Bu8 is very important.

Also, if there is no defective address (・, MODE=″L
”, then when CE-(J$- n...5 蒲 = "H", Mcg19 in Figure 1 becomes "H@", and MAIN MEMORY
It becomes a slow movement.

[Effects of the Invention] As explained above, the present invention provides a conventional semiconductor memory device with a plurality of registers capable of storing address information and address information, but an unselected semiconductor memory element and the contents of the plurality of registers and address information. By having a comparator for determining whether or not they match, there is an effect that the memory element can operate as a 4IC chip even if several bits of the memory element become defective.

By having this % enemy, for example, even if a satellite placed in a space environment breaks down after leaving the substation, it can continue to operate and extend the life of the device. It can also be expected to have a prolonging effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the semiconductor memory of the present invention, FIG. 2 is a detailed circuit diagram of the ADR and BEG sections in the block of FIG. 1, and FIG. 3 is a timing diagram showing the operation of FIG. 4
1 is a detailed circuit diagram of the COMP section in FIG. 1, FIG. 5 is a detailed circuit diagram of the SuBMEMORY section in FIG. 1, and FIG. 6 is a block diagram of a conventional semiconductor memory. In the figure, 1: External address bus, 2: Internal address bus, 3: ADR, BEG (address register) 4: -COMp (Comparator) ), 5
------・SuBMEMO 几Y、6・・・・・・MO
DB,%l,7...MAINMEMOET,Y
, 8...--counter, 9...-- decoder,
10.11.12...-F/F (flip-flop). 13...Register, 14...Bus, 1
5,16゜17・°°・・・Storage element, 18−・=DA
TA-Bu S (data bus), 19...M
CE (No. 7, 20...CE double signal 21...
・・External address bus, 22 Yamakawa address decoders, 2
3... Memory circuit, 24... R/W signal, 25... External data bus, 26...
Internal data bus, 27... data latch circuit,
28... 几EsE'r, 29... Bad address, 1,3o...MODE, 31---
---R/W, 32 ・-・-ADRφn+1.33・
...--C0UNT, 34...--Defective address 2. Agent: Patent Attorney Uchihara 2 days, Tori Kaya 3 Zuko 5 Diagrams

Claims (2)

[Claims] (1) A memory circuit composed of a large number of semiconductor memory elements, a decoder that converts external address information into an address signal within the IC chip under the control of a timing signal controlled by a clock signal, and this decoder. In a semiconductor memory device having a data switching circuit for writing external data to the only selected semiconductor memory element or reading data to the outside from the only selected semiconductor memory element based on the address signal converted by the address signal, A semiconductor memory comprising a plurality of registers capable of storing information, a semiconductor memory element that is not selected according to the address information, and a comparator for determining whether the contents of the plurality of registers match the address information. Device. (2) The plurality of registers that can store the address information can be written to from the outside, and the semiconductor memory elements that are not selected by the address information can be written to from the outside.
It is characterized by being readable. Claims (1)
) Semiconductor memory device described in item 1.