JPS6289088A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display device, and particularly to a display device that stores image information processed in a word processor, personal computer, etc. in a memory, and displays data based on the image information data in the memory. The present invention relates to a display device that can rewrite an image on any part of a display screen.

[Prior Art] Conventionally, displays such as CRTs do not have the ability to memorize display image signals, but because they respond quickly, even when rewriting a part of a static display screen, the display screen remains unchanged. A display image signal containing data for the entire surface is supplied to the display. On the other hand, if a ferroelectric liquid crystal with memory properties is used for the display, partial rewriting is possible by driving only one display element to be rewritten.

[Problems to be Solved by the Invention] However, displays using such ferroelectric liquid crystals have the following problems: the display response is extremely slow, comparable to that of CRTs; A matrix drive method is used. However, this drive system is fixed, and therefore partial rewriting can only be done row by row or column by column.
It would be convenient if the mode of partial rewriting on the display screen could be changed according to the difference between vertical and horizontal writing. It is possible to display FL
A display device using C can display in one-to-one correspondence with the hard output from a printer, so it must have a partial rewrite function that can be rewritten regardless of the directionality of the format.

[Means for Solving the Problems] The present invention aims to eliminate the above-mentioned conventional drawbacks, and for this purpose, a plurality of display elements arranged in two-dimensional directions in rows and columns; In a display device having a drive means for driving a plurality of display elements in a matrix, the drive means includes a plurality of drive circuit printers that drive the plurality of display elements by dividing them into two parts along the row and column directions. The drive circuit block includes a register for serial transfer of display data and a scan pulse transfer using an external clock, a selection means for causing the register to select either the serial transfer of display data or the scan pulse transfer, and a and control means for causing the register to transfer the scan pulse based on the corresponding external address signal input when the scan pulse transfer is selected.

[Example] An embodiment of the present invention will be explained in detail using FIG.

In FIG. 3, FLC is a ferroelectric liquid crystal display having 1344 pixels connected in a matrix in the line direction and 2048 pixels in the column direction. 42 drive circuit blocks 100-1 to 100-1 along the line direction of the display FLC
100-42, and 64 drive circuit blocks 1011 to 101-64 are arranged along the column direction. Each circuit block has a shift register, data latch, and driver as described below. Each block is responsible for 32 pixels in each direction.

The shift registers of each block are arranged in series along the line and column directions of the display FLC, and have a total capacity of 1344 bits and 2048 bits in the line and column directions, respectively. MOD is a mode signal, and the switch 10 is controlled by the switching control means 104.
5 is switched to display the serial image data from the input terminal Si along the line direction when the circuit block +00-1 is rewritten.
- too-42 side, and circuit blocks +01-1 to +101-134 side at the time of display rewriting along the column direction. WE is a write enable signal.

When rewriting the display along the line direction, the shift registers of the 42 circuit blocks 100-1 to 100-42 transfer one line of serial image data supplied from the input terminal S1 via the switch 105 to the corresponding image data. The data is sequentially transferred to the corresponding register using a data clock synchronized with the data clock. Similarly, when rewriting seven columns in the column direction, 64
The shift registers of the circuit blocks 101-1 to 101-64 sequentially transfer one output RAM of serial image data supplied from the input terminal Si via the switch 105 to the corresponding register using a data clock synchronized with the image data. Forward.

The data latches are arranged in one-to-one correspondence with the outputs of the shift registers and latch parallel outputs of the shift registers. When rewriting the display along the line direction, one line latched in the data latch is input by the line crotter that occurs when the transfer of one line of image data by the shift registers of the 42 circuit blocks 100-1 to 100-42 is completed. The image data for 1:1 is supplied to one electrode of each pixel cell in the line direction of the display FLC from a driver corresponding to the latch in a one-to-one manner. Similarly, when rewriting the display along the column direction, image data in one column direction is supplied to one electrode of each pixel cell in the column direction of the display FLC.

Decoder 103 receives an address signal specified by 6 bits, decodes the upper and lower 3 bits of the 6 bits into decimal format, and outputs the decoded signals to 16 decode lines +03A. Each circuit block receives one signal from the decoder 103.
Two selection lines selected from the six decode m 103A are respectively input, and one of all circuit blocks corresponding to the address decoded by the decoder 103 becomes scannable.

Therefore, display rewriting along the line direction, for example,
Now, one line of serial image data from the input terminal Si is sent to the 42 circuit blocks 100 via the switch 105.
-1-100-42 and the transfer has been completed, and the 64 circuit blocks 101-1 to 101
If circuit block 101-1 of -84 is selected by the address signal, the input of the line clock sets the first register scan pulse of the shift register of circuit block 101-1, and its output signal is supplied to the driver. This driver allows the display FL
Each pixel cell S00 of the first line of C. S01. SO2,
..., 5O1344 are driven, and each of these cells has 42 circuit blocks +00-1 to +00-42.
Since an electric field corresponding to the display image data from the driver is applied, the display data can thus be written on the first line of the display FLC.

Then, in the same manner, 42 circuit blocks 100-1~
The shift register 100-42 has finished transferring the second line of serial image data, and the second line data is supplied from the drivers of the same circuit blocks 100-1 to too-42 to each cell in the line direction by line clock input. At the same time, the shift register of circuit block +01-1 shifts the scanning pulse by one in the column direction, and as a result, each cell S10. of the second line of the display FLC. ! 11i11
．． ..., 511344 are displayed.

When the above-mentioned serial image data transfer and scanning pulse shift in the column direction are completed 32 times, data writing to the blocks shared by circuit block 1oll, that is, display rewriting of 32×1344 (column×line) pixels is completed. (See FIG. 1(a)). Note that display rewriting along the column direction can also be performed in the same manner as described above. That is, the mode signal MOD causes the switch 105 to be connected to the 64 circuit blocks 1ot-1-1.
01-f34 side, one of the 42 circuit blocks 100-1 to 100-42 is selected by the address signal and made scannable (see FIG. 1(b)).

Note that since the display device FLC used in this embodiment has a time of about 1 mS to write one line, it takes 32m5 to partially write 32 lines, but if this embodiment is used in a word processor, etc., for example, it takes 24×24 (Column×Line) Even if a dot kanji is displayed, it will fit within one block of 32 lines used in this embodiment, so display data for one character can be written at high speed in 32 m5.

Furthermore, rewriting of data over a plurality of blocks can be performed in the same manner as a normal rask scan by specifying an address from the CPU.

Next, specific examples of each of the above-mentioned circuit blocks will be explained with reference to FIG. The circuit shown in Figure 2 has a mode signal NOD.
By reversing the polarity of switches 2 and 3, the 42 circuit blocks +00-
1 to 100-42 and 64 circuit blocks 101-
1 to 101-84 are applied together. First, a case where the present invention is applied to 42 circuit blocks 100-1 to 100-42 will be described. That is, in Figure 2, 8-1.8-
2. . . . is a shift register consisting of a D (delay) type flip-flop (F/F), 10 is a data latch, and 11 is a display driver, each of which is responsible for 32 pixels.

Now, as shown in FIGS. 1(a) and 1(b), the mode signal 13 for switching the display rewriting along the line direction and the display rewriting along the column direction is set to low I.
When I L is 11, the switch 2 is connected to the signal line 4 from the terminal Si for inputting serial image data, and the serial image data is input to the data terminal of the first stage D F/F 8-1 forming the shift register. . At the same time, the OF/
A data clock synchronized with the serial image data is supplied to the clock terminal of F8-1 by the switch 3.
947 minutes of serial image data are sequentially transferred. 19
47 minutes of data transfer is completed, and in synchronization with the input of the line clock, the data latch IO configures the shift register D F/F 8-1.8-2. ..., that is, the image data for one line that has been transferred, is input to the driver IT, and the driver 11 outputs the image data to the display FL.
A voltage corresponding to each data can be applied in parallel to one electrode of each pixel cell of C.

On the other hand, the circuit in FIG. 2 is divided into 64 circuit blocks 101-1.
-101-Ei4, the mode signal line 13 is high (that is, the mode signal line on the 42 circuit blocks 100-1- to 100-42 is low). ), switch 2 is R-S.
It is connected to the signal line 5 from the Q terminal of the F/F 12. Furthermore, the two address selection lines 14 to the Nant gate 1 are both high (H) (that is, this circuit block is selected so that it can be scanned), and the write permission signal W
When E is high (H), the Q terminal output of R-3F/12 is set. At this time, switch 3 is set to line black
Since it is connected to the LK side, when the line clock CLK is input, all D F/Fs 8-1, 8-2. ...
The Q output of is set, and the R-SF/FI2 is reset, and the scan pulse output from the driver 11 via the latch 10 drives the first line of the display FLC connected to the driver. The scanning pulse sequentially scans the display FLC connected to the driver 10 line by line every time the line clock CLK is input, and the scanning of 32 lines handled by the driver 11 is completed.

At this time, if an adjacent circuit block is selected by the address line 14, the subsequent 32 lines can be scanned in the same manner.

[Effects of the Invention] As explained above, according to the present invention, any part of the display screen can be rewritten in accordance with the format.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a mode of partial rewriting corresponding to a difference in format on a display screen, Fig. 2 is a circuit block diagram showing details of the main part of an embodiment of the present invention, and Fig. 3 is an embodiment of the present invention. FIG. 2 is an example circuit block diagram. 1...Nant Gate, 2.3...Switch. 8A, 8B, 8C...Shift register, 10...Latch, 11...Driver.

Claims (1)

[Scope of Claim] A display device including a plurality of display elements arranged in a two-dimensional direction of rows and columns, and a driving means for driving the plurality of display elements in a matrix, It consists of a plurality of drive circuit blocks that divide each display element into a plurality of parts along the row and column directions and drive them. a register; a selection means for causing the register to select either serial transfer or scan pulse transfer of the display data; and when the selection means selects the scan pulse transfer, the scan pulse is transferred to the register based on a corresponding external address signal input. A display device characterized by having a control means for performing.