JPS628664A - Data recovering circuit - Google Patents

Abstract

PURPOSE:To process the recovery of the data at a high speed, to synchronize with the system speed of the electronic photograph system printer and to send the signal by providing two pairs of the data recovering part and recovering and processing the data outputted from the memory, in parallel. CONSTITUTION:The compressing data from a picture buffer 3 are inputted through a black shifter 13a and a white shifter 13b to a black decoding table 14a and a white decoding table 14b, the recovered run length data are selected by a selector 15, and signals RUNL 0-11 are sent to a run length counter 7. Each time a control line PIPE 1 falls, H is inputted to AND circuits ANDa and ANDb, in accordance with an output signal BLK/WHT of the run length counter 7, the black shifter 13a and the white shifter 13b output respectively the compressing data of the black dot and the white dot and the selector 15 alternately selects the recovering data and sends run length signals RUNL 0-11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data restoration circuit for restoring compressed image data in an electrophotographic printer such as a laser printer or an LED printer.

[Prior art and its problems] In general, when using a laser printer as an output device, there are two ways to transfer data sent from a host computer device such as a word processor: one is to send code information such as a character code, and the other is to send images as dot data. There are cases where it is sent. There are two types of printers based on code information: the bitmap method and the character map method. Of these, the bitmap method can print arbitrary characters in any position and has functions such as full graphics, but it also controls the operation of the printer. Since it cannot be stopped midway, the memory is expensive because it requires a capacity to store at least one page of data. In addition, in the dot data transfer method, the transfer speed from the computer device is controlled,
If the output speed of the print dot data of the printer is completely matched, the data from the computer device can be output as print data, but generally the processing speed of the computer device is slower than that of the printer. , data transfer cannot be synchronized, etc., so it is necessary to be able to print on the printer side regardless of the data transfer speed of the computer device. However, even in this case, electrophotographic printers have a fixed process speed depending on the sensitivity of the photoreceptor and the characteristics of development, transfer, etc. For example, like thermal printers, the paper feed speed can be varied and the process speed can be changed to a computer device. Since it is not possible to use a method that matches the timing of data transfer, it is necessary to provide a buffer memory on the printer side and store approximately one page worth of dot data sent from the computer device, which also requires a large capacity memory. required and became expensive.

Therefore, if the data sent from the computer device is compressed by encoding it and then stored in the memory, the memory capacity can be reduced.

First, data compression and restoration will be explained. For compression, Modified Huffman (Ml
-1) method, and as shown in the following table, the run length (run length) of white or black dots or black and white dots are encoded separately.

Modified Huffman code table Run length White run Black run 3　　toooo　　　t.

5 1100' 001164 110
11 QOOOOOOIII1EOL 0
00000000001 000000000001
This compression process is performed by a compression conversion table in the CPU, and the CPU detects the change point from the white run to the black run while importing the raster data sent from the outside, and corresponds to the number of dots up to the change point. The MH code of the white run length is searched from the compression conversion table, written to the memory consisting of RAM, and then the data is imported.This time, the change point from black run to white run is detected, and the black run length up to this change point is The MH code with the black run length corresponding to the number of dots is similarly searched and written into the memory. Each line sent as raster data is arranged so that it always starts with a white run, and if it starts with a black run, a white run of length "0" is inserted.

Therefore, the MH code and the code length of the MH code are stored in this compression conversion table so that the compression conversion is performed in accordance with the input raster data.

Incidentally, the code lengths to be converted are 4 bits to 9 bits for white runs, 2 bits to 13 bits for black runs, and 11 bits to 12 bits for black and white common runs. Therefore, data for one run length was stored in two addresses, as shown in Figure 4! It has a 2-byte configuration consisting of 6 bits, and the code length of the MI-I code is stored in binary in the upper 4 bits of the first address, and M However, in the case of a black run with a length of 13 bits, the high-order 1 bit of 0 is omitted and stored as 12 bits.With this configuration, codes up to 4 pits long that are frequently converted can be compressed by accessing 1 byte. Data according to the bit array encoded in this way is written to a memory address in units of 8 bits, which is 1 byte.

In this case, as shown in FIG. 5, byte boundaries are ignored, bits are compressed, and the data is written as a linear address. still,
If all lines in one scan are white dots, the white run length for one line is not compressed and encoded, but simply EO
Make sure to include only the L (end of line) code,
Also, if there are only white dots in the effective image area in one scanning line, an EOL code is also inserted.

Further, a restoration table ROM is used in the decoder for restoring data, and the contents of the data in the MH code written in the memory are stored as addresses in the ROM. The maximum length of data according to this MH code is 13
Also, when stored, the most significant bit of the data must be used for switching between the white run table and the black run table, and the stored data is 14 bits. Therefore, the restoring table ROM uses 14 address lines. The data to be output from this restoration table has a run length of 2 as shown in Figure 6.
The 12 bits of binary data required to represent up to 560 and the 4 bits of binary data required to represent the maximum code length of 13 bits make up a total of 16 bits.
Two are used.

FIG. 7 shows a block diagram of an image information processing device for a printer that performs the above-described data compression and restoration. The configuration and operation will be explained below.

The external interface 1 is a part connected to a raster data output type computer device, and specifically, a parallel interface such as Centronics or R9232.
This is a serial interface such as C, R9422, etc. C
The PU2 consists of a microprocessor, a program memory, a system RAM memory, and a table memory for compressing and converting the raster data from the above interface 1 into MH code by software, and the MH encoded data is processed according to the prescribed procedure as described above. is written into the image buffer 3 by The image buffer 3 is composed of a memory consisting of RAM, and when writing, 16 bits AO to
It is connected to the CPUI by an address bus of 15 and a data bus of 8 bits)DO to 7, and the data from the CPUI is written to the memory.When printing, the image buffer 3 is separated from the CPUI, 16
is connected to the address counter 4 by the address bus of
Then, it is connected to the shifter 5 by a 16-bit data bus of BFoUTO to I5. The address counter 4 is a circuit that generates an address for reading out the memory in the image buffer 3 via the address bus, and the generated address is held in the latch circuit 3a of the image buffer 3. Data at a predetermined address is read out by this access by the address counter 4, and sent to the shifter 5 in 16-bit units via the data bus. shifter 5
inputs manually input 16-bit data into a latch circuit 5a in this shifter 5, shifts it by a number indicated by a signal C0DEO-3 output from a decoding table 6, which will be described later, and outputs it as a signal C0DE15-0.

The decode table 6 is the MI output from the shifter 5.
This is a restoring circuit for restoring the signals C0DE15 to 0 based on the -1 code, and the restoring table ROM in the decoding table 6 outputs binary data of RUNO to 11 as the run length, and also outputs the input M
The code length of the H code is sent to the shifter 5 as binary data of C0DEO to 3. Therefore, shifter 5
The data in is Ml-1 decoded by decoding table 6.
The signal C0DE input to the decoding table 6 is output after being shifted by the number of bits equal to the code length.
The head of the MH code to be decoded next is located at C0DE l 5 of the upper bits from '15 to 0.

The run length counter 7 outputs the binary run length data inputted from the decoding table 6 as a serial black or white signal BLK/WHT, and also outputs BLK/Wl(T) every time it outputs a series of serial data. The data from the decode table 6 is latched into the latch circuit 7a of the run length counter 7.

The EOL detection circuit 8 detects when the EOL code is output from the shifter 5, and controls the control line U[sigma] to signal all the - rows to be white.

The output control unit 9 converts the serial data from the run length counter 7 or the EO17 signal from the EOL detection circuit 8 into a predetermined 8-bit parallel signal LDDATAO~7, and then outputs the signal to the engine interface IO connected to the engine of the printer. It is being sent to Pipe signal generation circuit 12
are circuits that generate signals to control each of the blocks described above, and CPU2. Run length counter 7, output control section 9
and control line INPRN from engine interface lO
T, ENI' I PE1, ENP I PE2 and SO 錗- are input, and the control lines ptpEt and v
Ding V “Controlling Ding.

Next, the operation of the block diagram of the above configuration will be explained with reference to the time chart of FIG.

When the control line INPRNT from the CPU 2 becomes “H”, that is, becomes non-active, the image buffer 3
The MH codes compressed by the CPU 1 are sequentially written into the image buffer 3.

In this CPU mode, the pipe signal generation circuit 12
．． Address counter 4. Shifter 5. Run length counter 7
And the output control section 9 is in the initial state. When one page of data is written to the image buffer 3, the CPU 2
When the engine interface IO is activated via the control line and further P n N 'I' = L, that is, activated, the image buffer 3 is disconnected from the CPU 2 and connected to the address counter 4 and shifter 5. Also, each block after the image buffer 3 becomes active and enters print mode.

Next, when a one-line scan start synchronization signal from the external engine is input to the engine interface IO, the control line SO8 falls in a pulsed manner.

As a result, the control line ENP lPE from the output control unit 9
2 becomes "active", that is, becomes active, and T is applied to the control lines PIPEI and PIPIε2 from the pipe signal generation circuit 12.
A falling pulse is generated in cycles of 1. Also, the control line 10-NPIPEI from the run length counter 7 is the control line PI.
This is a control line for enabling only PEI.

PIPE eye, address counter 41 image buffer 3.
Shifter 5, decode table 6 and run length counter 7
PIPE2 is also connected to a run length counter 7 and an output control section 9, and each block is connected to a PIPE2.
PE 1. P I Interval of pulses generated in PE2 1
The processing assigned to each block is completed within 1 hour.

In this print mode, the address counter 4 is
Every time I PE 1 falls, the counted address is sequentially sent to the image buffer 3 using 17 bits of the MAO-16, the address of the image buffer 3 is accessed, the data written in the memory is read, and the shifter 5
output as the I6 bit of BFOUTO to I5.

Note that when the control line C0UNTEN from the shifter 5 is "H", the address counter 4 remains unchanged even if ptpEt falls.
From then on, the counted addresses will not be sent.

As described above, the shifter 5 takes in the input data, shifts it so that the top of the next MH code to be decoded is placed in the upper 16 bits of output C0DE15-0, and sends it to the decoding table 6. do. In decode table 6, the run length of MH code is RUNLO~2
The data is restored as I2-bit binary data and sent to the run length counter 7. This run length counter 7 serially outputs data indicating the length of white or black.
Further, each time white or black serial data is output, the signal BLK/Wl-IT indicating white or black is inverted. At the falling edge of the control line σ, BLK/WI (T is set to I-level). Next, at the falling edge of PEI, the input run length value is preset in the run length counter. When this preset value is O, BLK/WHT is inverted, and when it is l, BLK/WHT is inverted at the falling edge of PIPE2.
I-IT is reversed. When this preset value is 2 or more, ENP I PE l is made inactive to prohibit falling of PIP El and stop the operation up to the run length counter section. Then, the preset value is decreased every time PMPE2 falls, and when this preset value becomes 1, BLK/WH〒 is inverted, and ENP I
Returning PEI to active status. Output control section 9
has a counter that is set to "8" at the falling edge of PIFE2, and every time PIFE2 falls, the real data from the run length counter 7 is taken into the latch circuit 9a in the output control section 9, and the above-mentioned The set value is decremented by l by the count. When this count value reaches 0, the count value is set to 8 again and the ENPIP
E2 becomes inactive and P I PE I and P I
Only the falling edge of PE2 is prohibited, and each block 3, 4, 5,
The operations at 6 and 7.9 stop. At this time, 8-bit data is latched in the latch circuit 9a,
When the control line LDREQ from the engine interface IO falls in a pulsed manner, data is sent from the output control unit 9 as parallel 8-bit LDDATAO to 7 to the engine via the engine interface IO, and at this time, ENPIPE2 returns to active. do. When the EOL signal is input to the output control unit 9, ENP I P is unconditionally set.
E2 becomes inactive, and in this case, ENP I PE returns to active at the next falling edge of SO8. After the EOL signal is generated, the signal from the run length counter 7 is invalidated.

Now, the problem with the above circuit is the decode table 6.
This is the processing speed in . This processing speed depends on the access time of the table ROM of the decode table 6, and the shift amount is not shown in the shifter 5. After the signal of C0DEO~3 or the control line PI PE I is input, the run length signal is output from the decode table 6. Until nUNLO~11 is output, a processing time of T3 in the shifter 5 and T in the decoding table 6, totaling 1'3+T4, is required.

When the run length is 1 or O, the restoration process is most severe and requires T 3 + T 4 per dot.

Therefore, the limit of the Dobutto clock is t/('r3+'r,), and this value is about 3 MI when using cheap memory.
The disadvantage is that the system speed of an electrophotographic printer needs to be reduced to match this speed.

[Object of the Invention] The present invention has been made in order to eliminate the above-mentioned problems, and an object thereof is to provide a data restoration circuit that can restore compressed data at high speed.

[Structure of the Invention] The data restoration circuit of the present invention includes a memory that encodes and stores the run length of image data, and appropriately shifts data output from this memory with a predetermined number of bits.
A shifter circuit that outputs the next restored run length code so that it becomes the beginning of data, and a restoration memory that restores the run length code output from the shifter circuit and outputs the run length in binary code. The data restoration circuit is characterized in that it includes two sets of data restoration sections each consisting of the shifter and a restoration memory connected to the shifter, and processes data output from the memory in parallel.

[Example 1] Figure 1 shows a data restoration section showing an example of the present invention.
It processes signals separately for black and white data.

Compressed data BFOUTO-15 from the image buffer 3 is input to a black shifter 13a and a white shifter 13b.

Output signal C0 of black shifter 13a and white shifter 13b
DE15-0 are manually input to the black decode table 14a and white decode table 14b, respectively, and signals C0DEO-3 representing the shift amount are input to each decode table 14.
a, 14b to each shifter 13a, 13b, respectively. Then, the run length data BRUN restored using the black decode table 14a and the white decode table +4b
LO~II.

WRUNLO-1 (are respectively input to the selector 15. The signal RUNLO-1 selected by the selector 15
1 is sent to the run length counter 7 described above. Then, the control line PIPEI is made into a positive logic control line PIPEI by the inverter INVI, and then the AND circuit ANDa, AND
black shifter 13a and white shifter 13 via b
b, and the output signal BLK/W of the run length counter 7
HT is input to the other input terminal of the AND circuit ANDb, and is input to the other input terminal of the AND circuit ANDa via the inverter INV2.

Next, the operation will be explained. Every time the control line PIPEI falls, "H" is input to one input terminal of the AND circuits ANDa and ANDb. Now, when the output signal BLK/WHTh (BLK, that is, "H") of the run length counter 7, the
The ND circuit ANDa is blocked, only the AND circuit ANDb is enabled, and a pipe signal via the control line PIPEI is sent to the white shifter +3b. And the control line P I
At the falling edge of the next pulse of PE I, the output signal BL
Since K/WHT is inverted to W HT , that is, "L", only the AND circuit ANDa is enabled this time, and a pipe signal is sent to the black shifter 13a. In this way, according to the output signal BLK/WHT of the run length counter 7, the black shifter 13a and the white shifter 13b transfer the compressed data of black dots and white dots to the black decode table 1, respectively.
4a, the data is output to the white decoding table 14b, and the compressed data is individually restored. The selector 15 selects restored data l3UTINLO~Il,Wr(UN
LO to 11 are alternately selected and sent to the run length counter 7 as a run length signal RUNLO-II. Therefore,
The processing speed of the restoration circuit can be approximately doubled compared to the conventional restoration circuit.

A time chart at this time is shown in FIG. In this time chart, the clock period is T1, but the ROM
sum of access time and delay time at shifter T
3+T, run length RtJNL and code length C0
The time required for DEO~3 is T even in the worst case, so there is plenty of time. Therefore, as shown in FIG. 3, even if the clock period is set to 'r,/2, the operation is possible and data can be restored at high speed.

[Effects of the Invention] As explained below, the data restoration circuit of the present invention has the following effects:
Two sets of data restoration units are provided to restore the data output from memory in parallel, making it possible to restore data at high speed compared to conventional data restoration circuits. It is possible to send signals in synchronization with the speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data restoration section showing one embodiment of the present invention, FIGS. 2 and 3 are time charts showing an example of the operation of the data restoration section in FIG. 1, and FIG. 5 is a bit array diagram of the conversion data stored in the memory, FIG. 5 is an array diagram of the MH code written in the memory, and FIG. 6 is a binary diagram output from the restoration table ROM.
FIG. 7 is a block diagram of an image information processing device for a printer using the conventional restoration method, and FIG.
The figure is a time chart showing the operation of the block diagram of FIG. 13a...Black shifter, 13b...White shifter, 1
4a...Black decode table, 14b...White decode table, 15...Selector. Patent Applicant: Minolta Camera Co., Ltd. Agent: Patent Attorney: 2 people (114) Figure 51!1 1116

Claims (1)

[Claims] (1) A memory that encodes and stores the run length of image data, and by appropriately shifting the data output from this memory with a predetermined number of bits, the run length code to be restored next becomes the beginning of the data. A data restoration circuit comprising a shifter circuit that outputs a run length code as described above, and a restoration memory that restores a run length code outputted from the shifter circuit and outputs the run length in a binary code, the data restoration circuit comprising: A data restoration circuit characterized in that two sets of data restoration sections each consisting of a restoration memory connected to a shifter are provided, and data output from the memory is processed in parallel.