JPS628605A - Operational amplifier circuit - Google Patents

Operational amplifier circuit

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Publication number
JPS628605A
JPS628605A JP14861185A JP14861185A JPS628605A JP S628605 A JPS628605 A JP S628605A JP 14861185 A JP14861185 A JP 14861185A JP 14861185 A JP14861185 A JP 14861185A JP S628605 A JPS628605 A JP S628605A
Authority
JP
Japan
Prior art keywords
misfet
transistor
output
output terminal
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14861185A
Other languages
Japanese (ja)
Inventor
Michio Yotsuyanagi
四柳 道夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14861185A priority Critical patent/JPS628605A/en
Publication of JPS628605A publication Critical patent/JPS628605A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To improve a power noise rejection ratio even at a high frequency by connecting a frequency compensating circuit between an output terminal connected to a drain of a MISFET of the output stage and a differential pair output. CONSTITUTION:An input signal inputted to a differential input stage and converted from a differential signal into a single signal is amplified by a common gate transistor (TR) M7, amplified inversely by a TR M10 and outputted to an output terminal 3. TRs M6, M8 act like a load and a constant current source of a TR M7 respectively. A frequency compensation circuit comprising a TR MR and a capacitor Cc is connected between the output terminal 3 and an output terminal of the differential stage comprising TRs M1, M2, but not connected between the gate and drain of a TR M9 being a load of the output stage even when the frequency compensation circuit is a low impedance at a high frequency, the TR M9 is not in the form of diode connection and then ease of invasion of power noise through the TR M9 is avoided.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は演算増幅回路に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to an operational amplifier circuit.

(従来技術とその問題点) 従来、第2図に示すような演算増幅回路(昭和58年度
電子通信学会総合全国大会論文集532石垣等1広帯域
スイッチキャパシタ回路の試作”)が知られている。第
2図に8いて、1は+側の入力端子、2は一側の入力端
子、3は出力端子、4は+側の電源ライン、5は一側の
電源ライン、6゜7はバイアス端子、M1〜M5、Ml
l〜M14、MRはMISFET)ランジスタ、Ccは
容量である。この演算増幅回路に2いては、ソースを共
通に定電流源であるMOSFET)ランジスタM5に接
続したMOSFET)ランジスタM1、M2の入力差動
対で、増幅し差動からシングル信号へ変換した信号をM
O8F’BT)ランジスタMllでしづルーシフトして
MOSFET)ランジスタM14で反転増幅するととも
をこMO8FETトランジスタM13でも反転増幅させ
て合わせて出力端子3へ出力している。また、抵抗とし
て働<MO8FETトランジスタMRと容量Ccとを直
列に接続した周波数補償回路を、出力端子3とMOSF
ET)ランジスタM1、M2の差動対の出力端子との間
に接続して、周波数補償を行なっている。
(Prior art and its problems) Conventionally, an operational amplifier circuit as shown in FIG. 2 (1988 Institute of Electronics and Communication Engineers General Conference Proceedings 532 Ishigaki et al. 1 Prototype of broadband switched capacitor circuit) is known. 8 in Figure 2, 1 is the input terminal on the + side, 2 is the input terminal on one side, 3 is the output terminal, 4 is the power supply line on the + side, 5 is the power supply line on the one side, 6゜7 is the bias terminal , M1-M5, Ml
1 to M14, MR is a MISFET) transistor, and Cc is a capacitance. In this operational amplifier circuit 2, a signal is amplified and converted from a differential to a single signal by a differential input pair of transistors M1 and M2 (MOSFET) whose source is connected to transistor M5 (MOSFET) which is a constant current source. M
O8F'BT) transistor Mll shifts the signal, MOSFET) transistor M14 inverts and amplifies it, and MO8FET transistor M13 also inverts and amplifies it, and outputs the combined signal to output terminal 3. In addition, a frequency compensation circuit in which a MO8FET transistor MR and a capacitor Cc are connected in series, which functions as a resistor, is connected to the output terminal 3 and the MOSFET transistor MR.
ET) It is connected between the output terminals of the differential pair of transistors M1 and M2 to perform frequency compensation.

しかる番と、第2図に示す従来の演算増幅回路では、M
OSFET )ランジスタM13のドレインとゲートの
間に容量と抵抗が直列番こ接続されており、高周波の信
号に対しては低インピーダンスになるのでMOSFET
)ランジスタM13のドレインとゲートの間が低インピ
ーダンスで接続されるので、MOSFET)ランジスタ
M13がダイオード接続とみなせる。従って、tLI!
@電圧の雑音成分のうち、高周波成分はMOSFET)
ランジスタM13を通って出力端子3に現われるように
なり、電源雑音除去比が高周波数で悪化するという欠点
が存在する。
In the conventional operational amplifier circuit shown in FIG.
OSFET) A capacitor and a resistor are connected in series between the drain and gate of the transistor M13, and it has a low impedance for high-frequency signals, so it is a MOSFET.
Since the drain and gate of the transistor M13 are connected with low impedance, the MOSFET transistor M13 can be regarded as diode-connected. Therefore, tLI!
@Among voltage noise components, high frequency components are MOSFET)
It passes through the transistor M13 and appears at the output terminal 3, which has the disadvantage that the power supply noise rejection ratio deteriorates at high frequencies.

この欠点を除くためにMO8FETトランジスタM13
のゲートをMO8PE’l’)ランジスタM1、M2の
差動対の出力端子ζこ接続せずにバイアス点8に接続す
るようにした第3図の演算増幅回路を考えるとMO8F
]18TトランジスタM13は、もはや信号を反転増幅
させるという機能を有しないので、第2図の回路に比べ
ると、MO8PETトランジスタM13が能動素子とし
て動作しない分だけ利得が落ち、出力段の利得はMO8
FETトランジスタM14によるものだけとなり1/2
近く出力段の利得が第2図に示す演算増幅回路に比べ減
少するという欠点が生じる。
To eliminate this drawback, MO8FET transistor M13
Considering the operational amplifier circuit shown in Fig. 3 in which the gate of MO8PE'l') is connected to the bias point 8 without connecting the output terminals of the differential pair of transistors M1 and M2, MO8F
] Since the 18T transistor M13 no longer has the function of inverting and amplifying the signal, the gain is reduced compared to the circuit of FIG. 2 by the amount that the MO8PET transistor M13 does not operate as an active element, and the gain of the output stage is equal to that of the MO8PET transistor M13.
Only due to FET transistor M14, 1/2
A shortcoming occurs in that the gain of the output stage is reduced compared to the operational amplifier circuit shown in FIG.

(本発明の目的) 以上の点に鑑み1本発明の目的は、電源雑音除去比が高
周波数でも良好で、かつ演算増幅回路の利得が高い演算
増幅回路を提供することである。
(Objective of the Present Invention) In view of the above points, one object of the present invention is to provide an operational amplifier circuit that has a good power supply noise rejection ratio even at high frequencies and has a high gain.

(発明の構成) 本発明の演算増幅回路は、ソースを共通に第1の定電流
源に接続されたMISFET差動対と、前記MISFB
T差動対の出力がソース(=接続されたゲート接地形の
第1のMISFETと、前記第1のMI8FETに接続
される第2の定電流源となる第2のMI8FETと、前
記第1のMISFETjこ接続される第1の負荷ζなる
第3のMISFETと、前記第1のMI8FETのドレ
インにゲートを接続されたM4のMI8FETと、前記
第4のMISFBTに接続される第2の負荷となる第5
のMISFETと、前記第4のMISFETのドレイン
に接続された出力端子と前記差動対の出力との間に接続
された周波数補償回路を含んで構成される。
(Structure of the Invention) The operational amplifier circuit of the present invention includes a MISFET differential pair whose sources are commonly connected to a first constant current source, and the MISFET differential pair whose sources are commonly connected to a first constant current source.
The output of the T differential pair is a first MISFET with a grounded gate whose source (=connected), a second MI8FET connected to the first MI8FET and serving as a second constant current source, and a second MISFET connected to the first MI8FET, which is a second constant current source; A third MISFET with a first load ζ connected to the MISFET, an M4 MI8FET whose gate is connected to the drain of the first MI8FET, and a second load connected to the fourth MISFBT. Fifth
and a frequency compensation circuit connected between the output terminal connected to the drain of the fourth MISFET and the output of the differential pair.

(実施例) 次に本発明について図面を参照して説明する。(Example) Next, the present invention will be explained with reference to the drawings.

本発明の一実施例をgi図に示す。第1図において9〜
12はバイアス端子、M6〜MIOはMOSFET)ラ
ンジスタである。差動入力段に入力され、差動からシン
グル信号へ変換された入力信号はゲート接地形のトラン
ジスタM7によりて増幅され、さらにトランジスタMI
Oで反転増幅されて出力端子3へ出力される。トランジ
スタM6、M8はそれぞれトランジスタM7の負荷Bよ
び定電流源として動作する。トランジスタMRと容量C
cからなる1周波数補償回路は第2図と同様に、出力端
子3とトランジスタMl、M2の差動段の出力端子との
間に接続されているが、出力段の負荷となっているトラ
ンジスタM9のゲートとドレインとの間に接続されてい
ないので、高周波数で周波数補償回路が低インピーダン
スとなってもトランジスタM9がダイオード接続の形に
ならず、トランジスタM9を通って電源雑音が混入しや
すくなるということはない。従って高周波数で電源、雑
音除去比が悪化するということはなく、良好な電源雑音
除去比が得られる。
An embodiment of the present invention is shown in the gi diagram. 9~ in Figure 1
12 is a bias terminal, and M6 to MIO are MOSFET transistors. The input signal inputted to the differential input stage and converted from differential to single signal is amplified by transistor M7 with gate grounded, and further amplified by transistor M1.
The signal is inverted and amplified at O and output to output terminal 3. Transistors M6 and M8 operate as a load B and a constant current source for transistor M7, respectively. Transistor MR and capacitance C
As in FIG. 2, the one-frequency compensation circuit consisting of C is connected between the output terminal 3 and the output terminal of the differential stage of transistors Ml and M2, but the transistor M9, which is the load of the output stage, Since the transistor M9 is not connected between the gate and drain of the transistor M9, even if the frequency compensation circuit becomes low impedance at high frequencies, the transistor M9 will not be in a diode-connected form, and power supply noise will easily enter through the transistor M9. That's not the case. Therefore, the power supply and noise rejection ratios do not deteriorate at high frequencies, and a good power supply noise rejection ratio can be obtained.

また、第3図は差動対からの信号をソース・フォロアを
介して出力段へ入力し、トランジスタM14で反転増幅
して出力しているが、第1図に示す実施例では差動対か
らの信号をゲート接地形のトランジスタM7で増幅して
、出力段のトランジスタMl□で再び反転増幅して出力
しているので、利得は第3図の場合と比ベトランジスタ
M7での増幅器だけ高くなるので、数10倍高くするこ
とが可能である。従って第3図の演算増幅器のように、
第2図の演算増幅器と比べて第1図の実施例は利得が減
少するということはなくむしろ増加する。
In addition, in FIG. 3, the signal from the differential pair is input to the output stage via the source follower, inverted and amplified by the transistor M14, and outputted, but in the embodiment shown in FIG. The signal is amplified by the gate-grounded transistor M7, and is inverted and amplified again by the output stage transistor Ml□, so the gain is higher than in the case of Fig. 3 by the amplifier in transistor M7. Therefore, it is possible to increase the cost by several tens of times. Therefore, like the operational amplifier in Figure 3,
Compared to the operational amplifier of FIG. 2, the embodiment of FIG. 1 does not have a reduced gain, but rather an increased gain.

(発明の効果) 以上述べたように本発明の演算増幅器は、電源雑音除去
比が高周波数でも良好で、かつ、利得3十分高(するこ
とができる効果がある。
(Effects of the Invention) As described above, the operational amplifier of the present invention has the advantage that the power supply noise rejection ratio is good even at high frequencies, and the gain is sufficiently high (3).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図、第2図、2よび第
3図はそれぞれ従来の演算増幅器の一例2よび他の一例
の回路図である。 1.2・・・・・・入力端子、3・・・・・・出力端子
、4.5・・・・・・電源ライン、6〜12・・・・・
・バイアス端子、M1〜M14.MR・・・・・・MO
8FETトランジスタ、Cc・・・・・・容量。 牛l 口 第2 じ 第 3 児
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2, 2, and 3 are circuit diagrams of an example 2 and another example of a conventional operational amplifier, respectively. 1.2...Input terminal, 3...Output terminal, 4.5...Power line, 6-12...
・Bias terminal, M1 to M14. MR・・・・・・MO
8FET transistor, Cc... Capacity. Cow's second and third child

Claims (1)

【特許請求の範囲】[Claims] ソースを共通に第1の定電流源に接続されたMISFE
T差動対と、前記MISFET差動対の出力がソースに
接続されたゲート接地形の第1のMISFETと、前記
第1のMISFETに接続される第2の定電流源となる
第2のMISFETと、前記第1のMISFETに接続
される第1の負荷となる第3のMISFETと、前記第
1のMISFETのドレインにゲートを接続された第4
のMISFETと、前記第4のMISFETに接続され
る第2の負荷となる第5のMISFETと、前記第4の
MISFETのドレインに接続された出力端子と前記差
動対の出力との間に接続された周波数補償回路とを含む
ことを特徴とする演算増幅回路。
MISFE whose sources are commonly connected to the first constant current source
T differential pair, a first MISFET with a grounded gate whose source is connected to the output of the MISFET differential pair, and a second MISFET connected to the first MISFET and serving as a second constant current source. , a third MISFET serving as a first load connected to the first MISFET, and a fourth MISFET having a gate connected to the drain of the first MISFET.
a fifth MISFET connected to the fourth MISFET and serving as a second load; and an output terminal connected to the drain of the fourth MISFET and an output of the differential pair. An operational amplifier circuit comprising a frequency compensation circuit.
JP14861185A 1985-07-05 1985-07-05 Operational amplifier circuit Pending JPS628605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14861185A JPS628605A (en) 1985-07-05 1985-07-05 Operational amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14861185A JPS628605A (en) 1985-07-05 1985-07-05 Operational amplifier circuit

Publications (1)

Publication Number Publication Date
JPS628605A true JPS628605A (en) 1987-01-16

Family

ID=15456650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14861185A Pending JPS628605A (en) 1985-07-05 1985-07-05 Operational amplifier circuit

Country Status (1)

Country Link
JP (1) JPS628605A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498874B1 (en) 1997-12-22 2002-12-24 Sumitomo Electric Industries, Ltd. Optical transmission line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498874B1 (en) 1997-12-22 2002-12-24 Sumitomo Electric Industries, Ltd. Optical transmission line

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