JPS6284366A - Microcomputer - Google Patents

Abstract

PURPOSE:To attain freely an access to an external address bus without any change of the hardware even when the width of the external address buses is increased by using plural 8-bit constitution address buffer circuits connected to an internal bus properly. CONSTITUTION:A CPU 1 is provided with an ALU 8 connected to an internal data bus 3 and an internal address bus 2, an I/D counter 7 whose increment/ decrement is controlled by an I/D control signal and making count by a CI control signal and an output of a carry flip-flop, and three registers IPL 4, an IPM 5 and an IPH 6 acting like an instruction pointer, and address buffer circuits ABL 9, ABM 10 and ABH 11 connected to the internal address bus 2 and external address buses 12, 13, 14.

Description

[Detailed Description of the Invention] [Summary] A microcomputer is equipped with an 8-bit internal address bus, an 8-bit address arithmetic circuit, and a plurality of 8-bit address buffer circuits, and is capable of reducing external address bus congestion. When the bus width is increased, a corresponding number of address buffer circuits are used, so that access can be made freely even to an external address bus whose bus width is increased.

[Industrial application field]

The present invention relates to a microcomputer, and more specifically to a microcomputer that allows access to an external address bus without changing the hardware even when the width of the external address bus increases. .

[Conventional technology]

In conventional computers, if the address space is enlarged and the external address bus is increased, the internal address bus width must also be correspondingly increased.For example, if the external address bus congestion is made 18 bits, Internal address bus congestion also needs to be 18 bits.

[Problem that jl is trying to solve] By the way, if the internal address width is made 18 bits, address calculation circuits such as program 1 and counters will also need to be configured in 18 bits, which will increase the circuit scale. It is also complicated because the circuit configuration must be changed every time the bus width changes.

Of course, it is possible to deal with the increase in external address congestion by setting the configuration to 32 bits in advance, but as mentioned above, if 18 bits are sufficient for external address bus congestion, the remaining 1
Four bits are wasted, resulting in extremely low hardware usage efficiency.

The present invention was created in view of the problems of the prior art, and provides a microcomputer with IIT capability that can access an external address bus without increasing hardware even when external address bus congestion increases. For the purpose of providing.

[F-stage to solve problems]

The present invention includes an internal bus having an 8B/1 configuration, an 8-bit address calculation circuit connected to the internal bus, and a plurality of 8-bit address calculation circuits each connected to the internal bus.
1,974,777 circuits, and is characterized in that access to the external address bus can be freely performed by appropriately using a corresponding number of address buffer circuits in response to increases and decreases in external address bus congestion.

[Effect]

If the congestion of the external address bus is 8 bits or less, the external address bus can be accessed by using one address buffer circuit.

If the width of the external address bus exceeds 8 bits and is within 16 bits, the external address bus can be accessed at once by using two address/to-7 buffer circuits. In this case, the external address bus can access 2 bytes at a time, but the internal address bus can access 1 byte at a time. Therefore, it is necessary to access the internal address bus twice for one access to the external address bus, but since data transfer inside the CPU can be performed at high speed, access to the external address bus is particularly delayed. Never.

Furthermore, when the number of external address buses increases, access can be easily achieved by using a corresponding number of address buffer circuits.
There is no need to change or increase the hardware inside the U.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a partial configuration diagram of a microcomputer according to an embodiment of the present invention, where 1 is a CPU and 2 is an 8-bit internal address bus.

3 is an internal data bus also having an 8-bit configuration.

4.5.6 are registers each having an 8-bit configuration,
4 is the instruction pointer (IPL) indicating the lower 4Q 8 bits, 5 is the instruction pointer (IPM) indicating the middle 8 bits, and 6 is the upper 8 bits.
Used as an instruction pointer (IPH) that indicates a bit.

7 is a counter circuit having an input/output configuration of 8 bits, and can add or subtract 1 from the contents of registers 4, 5, and 6. 8 is an ALU circuit having an input/output having an 8-bit configuration, and is used for address calculation.

9, 10, and 11 are 8-bit address per 2 buffer circuits, each connected to the internal address bus 2, and the address buffer circuit (ABL) 9 is connected to the register (IPL) 4.
The address buffer circuit (ABM) 10 transfers the contents of the register (IPM) 5 to the address buffer circuit (ABM) 10.
BH)l1 stores the contents of register (IPH)6. 12, 13, and 14 are address buffer circuits 9, respectively.
This is an 8-bit external address bus connected to 10.11.

FIG. 2 is a circuit diagram of the counter circuit 7 of FIG. 1. 15
is an increment 7/decrement (counter) having an 8-bit human output, and a counting operation is performed when the CI human power is at a low level, and either increment counting or decrement counting is selected by the 1/D control signal.

16 is a carry flip-flop (CF) which detects a carry when a carry occurs in the CO output of the increment/decrement counter 15 and outputs a high level; and 17 is a NOR circuit.

18 is an AND circuit, and 19 is an inverter circuit.

The CI control signal goes low when inputting the contents of the register (IPL) 4 to the counter 15. This allows IPL
When the contents of 4 are input to the counter 15, the CI large input becomes low level, causing a carry to the least significant bit. On the other hand, when the contents of r PH5 and I PH6 are input to the counter 15, the CI large input level state differs depending on whether there is a carry of the previous data. In other words, the previous data has digit 1-
When an error occurs and the output of the carry flip-flop 16 becomes a high level, the output of the NOR circuit 17, that is, the CI large input becomes a low level, causing a carry to the least significant bit.

Note that the I/D control signal and CI control signal are connected to a PLA (not shown).
(program logic array).

Next, the operation of the embodiment of the present invention will be described with reference to the timing chart shown in FIG.

Currently, the address space is large and the congestion of the external address bus is 2.
If 4 bits are required, the lower 8 bits of address data
The bits are placed in register 4, the middle 8 bits are placed in register 5,
The older 8 bits are stored in register 6.

Consider a case where an instruction is decoded by the PLA, and as a result, a RAM (not shown) connected to external address buses 12-14 is accessed using address data in registers 4, 5.6. First, at clock To, the register (IPL
) 4 to the address buffer circuit (ABL) 9 and the I/D counter circuit 7 via the internal AT L/S 2. Since the CI control signal at this time is at a high level, the CI large input of the counter 15 becomes a low level, causing a digit error to the least significant bit of the data (IPL) (the count increases by one during increment operation). ,
As a result, when a shift occurs in the ki Kita Kitakami bit co output), the output of the CF 16 becomes high level.

Next, at T1, data (IPM) is transferred from the register (IPM) 5 to the address buffer circuit (ABM) to and the I/D counter circuit 7 via the internal address bus 2. At the same time, the data in the I/D counter circuit 7 is transferred to the register (
Since the CI control signal is at a low level at this time, the CI input level of the counter 15 changes depending on whether or not there is a carry of the most significant bit of the previous data (IPL). In other words, 1 is added to the least significant bit of the previous data (IPL).
As a result of addition of
When no carry occurs in the 42nd most significant bit of PL), no carry occurs in the least significant bit of the primary data (IPM) (CI power is at a high level).

Next, at T2, the data (IP
H) is transferred to the address buffer circuit (ABH) 11 and the I/D counter circuit 7 via the internal address bus 2. At the same time, the data in the I/D counter circuit 7 (IPM
) is returned to the register (IPM) 5 via the internal data bus 3. Since the CI control signal at this time is at a low level,
The CI level of the counter 15 changes depending on whether or not the most significant bit of the previous data (IPM) has a 1-digit difference. In other words, if there is a carry in the -L bit of the previous data (IPM), the CI input current level becomes low level and the data (IPM)
1 is added to the least significant bit of the data (IPH), and if there is no digit -L, the CI input level becomes high level and the data (IPH
) content remains unchanged.

At T3, data in I/D counter pJ path 7 (IPH)
is returned to the register (IPH) 6 via the internal data/Hess 3. At the 0th time, the address buffer circuits 9 to 1 are sent to the TO-T2.
Address data stored in 1 (I PL , I PM
, I PH) to external address buses 12 to 14 (total 12
bit). As a result, even a RAM with a large address space can be freely accessed.

Also, when the address space is small, for example when 8 bits is sufficient for the external address bus, register data (IPL)
) 4 and an address buffer circuit (ABL) 9, it can be easily accessed.

As described above, according to the embodiment of the present invention, the simple configuration in which a plurality of 8-bit registers and 8-bit address buffer circuits are provided in advance is effective against increases and decreases in bus congestion of the external address bus. can be dealt with. That is, according to this embodiment, even when the address space increases or decreases, the I/D counter circuit 7, internal address bus, etc. can remain in the 8-bit configuration, and the hardware can be greatly simplified.

Although ALU8 was not described in detail in the embodiment,
When using ALU8 as an address calculation circuit, I/D
It is clear that, like the counter circuit 7, an 8-bit configuration is sufficient.

In addition, in the embodiment, it is necessary to transfer data within the CPU three times for one data transfer on the external address bus.
As is well known, data transfer within the CPU can be performed at high speed, so this does not cause processing delays.

〔Effect of the invention〕

As explained above, according to the present invention, access is possible even when external address bus congestion increases or decreases.

By appropriately selecting and using pre-installed 8-bit circuits, you can achieve this without changing the hardware.
External address bus can be accessed.

[Brief explanation of drawings]

The first factor is a partial configuration diagram of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the 1/D power counter circuit 7 of FIG. 1. FIG. 3 is a timing chart for explaining the operation of the embodiment of the present invention shown in FIG. l...CPU 2...Internal address bus 3...Internal data bus 4-6...Register 7...I/D counter circuit 8...ALU 9-11...Address buffer circuit 12 ~14... External address bus 15... Counter 16... Geary flip-flop (CF) 17...
・Noah circuit 18...AND circuit 19...Inverter circuit agent Patent attorney's digit 1'1- N shot ≦S so Y〕of f = (person - Ishi 1]T
≧] No.! figure

Claims (1)

[Scope of Claims] An 8-bit internal bus, an 8-bit address calculation circuit connected to the internal bus, and a plurality of 8-bit address buffer circuits each connected to the internal bus. 1. A microcomputer characterized in that the external address bus can be freely accessed by appropriately using a corresponding number of address buffer circuits as the width of the external address bus increases or decreases.