JPS6284336A - Modulo-3 residue generator - Google Patents

Abstract

PURPOSE:To ensure free constitution for formation of LSI (large scale integration) by obtaining modulo-3 residue of any binary number of multiple digits by repetition of small-scale and simple circuits. CONSTITUTION:When bit of weight of even number power of 2 or bit data x10, x11, x12 of weight of odd number power of 2 are inputted to input lines X10, X11, X12. A modules 130, 140, 150 and 160 output modulo-3 residue of a value obtained by adding all input data to output lines Y10, Y12 at weight 1, 2 respectively, and output logical negation of output lines Y10, Y12 to output lines Y11, Y13. B modules 170, 180 and 190 receive modulo-3 data of weight 2, 1 respectively from input lines X20, X22 and X24, X26 and input logical negation of input lines X20, X22, X24, X26 to input lines X21, X23, X25, X27 respectively, and thereby, output the result of addition of modulo-3 of inputted two modulo-3 data to output lines Y20, Y22 at weight 2, 1 respectively. Logical negation of output lines Y20, Y22 is outputted to output lines Y21, Y23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulo 3 remainder generator in an information processing device, and more particularly to a modulo 3 remainder generator that generates a modulo 3 remainder for given binary data.

[Conventional technology]

Conventionally, this type of modulo-3 remainder generator uses a memory, stores the modulo-3 remainder of an existing address in each memory address in advance, and generates the desired modulo-3 remainder by inputting data to the address of the existing memory. Or, as disclosed in Japanese Patent Publication No. 54-75958, a data bit string is divided into several pairs of bits in an even bundle with a weight of 2 and bits in an odd bundle with a weight of 2. There were some that generated a modulo 3 remainder and then added them together to generate a modulo 3 remainder.

[Problem that the invention seeks to solve]

The conventional modulo-3 remainder generator described above requires memory capacity that increases exponentially as the number of bits of target data increases, so it is difficult to use when the number of bits of data is large. has the disadvantage of being far beyond practical.

Furthermore, in the case of a device using a logic circuit, such as the one disclosed in Japanese Patent Publication No. 54-75958, the bit weight of the supplied data is a mixture of even number bundles of 2 and odd number bundles of 2. It is assumed that you have
In recent years, logic circuits have become more prominent in LSIs, for example, when trying to implement LSIs that handle only bits with weights of even bundles of 2 or odd bundles of 2, the generation of modulo 3 remainders occurs inside the LSI. However, there is a drawback in that it is not always possible to freely integrate logic circuits into LSIs.

In view of the above-mentioned points, an object of the present invention is to provide a modulo-3 remainder generator that is practical and guarantees free implementation of a logic circuit into an LSI.

[Means for solving problems]

A modulo 3 remainder generator of the present invention outputs a modulo 3 remainder of binary data, and has an input line X10+ X+++ X+z and an output line y, , Y+++ Y+t+ Yes, Xz+ Binary data input from X+z x1゜+ "ll+ x, 3' for engineering
+a-3E100X++° to self z+X10°3E++・
xII”X16 ' ” II ' X I!
15' I11+ )'++-Who' W++ ・xB+ 5E, o
HX+t ・X+z+x II ' xII '
X +! +Y ++ respectively to the output lines Y Ior Y ++ *
One or more modulo 3 remainder generating means output from Y + t + Y13, and input line X2゜r Xthr
Xthr Xts+X business 4+ X□+ Xth
r Xzy and output line Y2°.

y,, Yzx+ Y! 3, and said input line X2°.

Xthr Xthr Xthr Xthr
Thr X! 41 Xt? Modulo 3 data inputted from x engineering In X□, xo.

X mushroom 3 + x small 41X! 5l) Cth+X
(for t'l) 'to' Xtz ' Xthr
X small a 0 Xts ゛ XthrX 寞1
'X! 3' x*4+7! ? Y*I-)Cue 'Xthr Xz+' Xzs
' xi, +X 11 ' X 2S ' x
! ? +yg+ respectively to the output line Y7゜r Yz++ Yt
i+Yt3 outputs one or more modulo 3 addition means, and the binary data x1゜+xll+x, □ is input to the input line X of the one or more modulo 3 remainder generation means.
1°.

a first connection means for inputting to Xll+X11;
Output line Yli of the modulo 3 remainder generating means
Y+++ Y, , the modulo 3 data Xtll+ X! output from YI3. I+ Xtz, X! !
+ x14+x2S+ xZ&+ xl? to the input line X ZO+ of said one or more modulo 3 addition means
X ZI+ X zz, X z*+X 24
1 X is, X ff16+ a second connection means for inputting to X tt.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a modulo-3 remainder generator showing an embodiment of the present invention. The modulo-3 remainder generator of this embodiment generates a modulo-3 remainder of a 12-bit unsigned binary number. be. It is assumed that the binary number 110 represents a 12-bit unsigned binary integer, and data of each bit from weight 2° to weight 2 is input to signal lines 111 to 122, respectively.

A modules 130, 140, 150 and 160 are
When data x1゜+ xII+ ! ++ 'xlt+x16' 5
EII ' x, t+x+e 'Xth' XI! + y++”X10・5Ez 'X+z+X++'
X++'Mat+XIe'XII'xIconi9 to output lines Y10 and YB with weights 12 and Y13, respectively
2, and the logical negation y1° of output lines Y1°, Y, and 2 is output on the output line Yll+Y12, respectively.

Output.

B modules 170, 180 and 190 receive modulo 3 data xtar x! with a weight of 2.1 from the input lines X2°, X, and X, , , Xt&, respectively. l
＋Xa10x! th, input line Xz++
Xts+ Xts+ Xtq has input lines X ff1O+ X zt, X tar
Logical negation of zb X□+X! ! +X! Sr.
By inputting xt'J, the modulo 3 addition result of the two input modulo 3 data "!to-Xzo ' Xtb+Xzo '
Xzs' x meaning? +X 2I' x12
'x! 4+7g+-Xzo' Xta+Xz+
'Xx3°xzh+”IR'X @S'
x1? + to the output line Yzo, each with a weight of 2.1,
Outputs Yzz. Also, the output lines Y, , Y,
, has an output line Y2° and a logical negation of Ytt y2°.

Vz+ This outputs the following.

For example, as shown in FIG.
The module can be easily configured as shown in FIG. 3, for example.

Next, the operation of the modulo 3 remainder generator of this embodiment configured as described above will be explained. Here, the binary number 11
Consider the case where 0 is °101101101110'. First, each bit of the binary number 110 is connected to the signal line 111.
A module 130.140.150 via ~122
and 160, the A module 160
Output °01゛, which is the modulo 3 remainder of the base number "101000000000', to the output lines Y1□, Y+.
At the same time, the output line Y l! , Y + I outputs its logical negation.

Similarly, the A module 140 also has a binary number 'oooo.

The modulo 3 remainder "00°" of "0101010" and its logical negation are output to output lines Y10 to YIf.

Furthermore, the A module 150 has the binary number '000101
10゛, which is the modulo 3 remainder of 0ooooo°, is output to the output line Y1゜, Y, , and at the same time, the output line Y10
The logical negation is output to Yl3.

Similarly, the A module 130 also has the binary number 'oooooo
.

Yl the modulo 3 remainder 01° of 00100' and its logical negation. - Output to Ylff.

Next, the B module 180 sends modulo 3 data and its logical negation data 0110° via signal lines 161 to 164, and modulo 3 data and its logical negation data 1001 via signal lines 151 to 154.
”, the two modulo 3 data ゛01°,
"00", which is the Mojello addition result of 10 degrees, is output to the output lines Y10 and Yet, and the output line Y2.

The logical negation of "11" is outputted to Yo.

Similarly, the B module 170 also receives two modulo 3 signals via signal lines 141-144 and signals vA131-134.
Data and its logical negation "0101", '011'
0', modulo 3 data '00°, '01'
The modulo addition result of 01 is outputted to the output lines Y2 and YH, and the logical negation of 10 is outputted to the output lines Y, , Y, and ff.

Finally, the B module 190 connects signal lines 181 to 184.
, 171-174 to B modules 180 and 1
70, two modulo 3 data and their logical negation'
0101'' and '0110', the modulo 3 addition result ``01'' of the modulo 3 data 00° and '01' is outputted to the output lines Y1□ and Ylo as the modulo 3 remainder of the binary number 101010110001°, and the signal line 19
12, Y13192 as a desired value.

Next, the modulo 3 remainder generator of this embodiment is configured with an equalize shifter that adds floating point data with an exponent base of 16 and a mantissa of bits #0 to 31 (# indicates a bit position. The same applies hereinafter). The fourth example shows an example in which an adder is divided into several LSIs and is applied to an error check circuit.
As shown in the figure.

L S I A 410, 420, 430 and 440
is for configuring an equalize shifter that has a function of arithmetic right shift in units of 4 points as a whole, and the signal line 41
1 has bits #0.4.8. . . , 28, the signal line 421 has bits #l 5, 9 . ..., 29,
The signal line 431 has bit #2. 6.10. ...
, 30, and the signal line 441 has bit #3. 7.112,
Each mantissa bit of Y13..., 31 is input, a signal having the same truth value as bit #O is input from the signal line 405 as a sign, and according to the shift count input from the signal line 406, the signal lines 414, 424,434,4
The shifted data is output to 44.

The LSIB 460 compares the modulo 3 remainder of the predicted addition result with the modulo 3 remainder generated from the addition result,
It detects errors.

The LSI C450 is for adding the augend data and the addition data output from the equalize shifter, and generating the result and a modulo 3 remainder of the result.

The shifter 500 performs an arithmetic right shift in 1-bit units according to a shift count input from the signal line 406.

The C module 600 generates a modulo 3 remainder when all the data shifted out from the LSI side by the operation of the shifter 500 is data whose weight is an even power of 2, and generates a modulo 3 remainder through signal lines 412 and 413, respectively. 422
, 423 and signal lines 432, 433 and signal lines 422, 44
3 and output in the form of 3's complement.

The adder 455 receives data to be added from the signal line 451, receives addition data from the signal lines 414, 424, 434, and 444, performs addition, and outputs the result to the signal line 452.

The D module 456 receives the addition result from the signal line 452 and outputs the modulo 3 remainder to the signal line 453.

The modulo 3 adder 465 inputs the modulo 3 remainder of the augend data inputted to the signal line 451 from the signal lines 401 and 402, and receives the signal 411°4 from the signal lines 403 and 404.
212, Y13431, 441 to input the modulo 3 remainder of the addition data input to the equalize shifter, and signal lines 412, 413, signal lines 422, 423, and signal line 4.
32, 433 and the 3's complement of the modulo 3 remainder of the data shifted out from the LSIB 460 by the equalize shifter from the signal lines 442 and 443, and by adding all of them modulo 3, the modulo 3 remainder of the addition result of the adder 455 is obtained. , and outputs the result to the signal line 461.

The comparator 466 receives the modulo 3 remainder of the addition result from the signal line 453, receives the modulo 3 remainder of the predicted addition result from the signal line 461, compares the two, and if they do not match, sends a signal indicating that an error has occurred. It is output to line 462.

〔Effect of the invention〕

As explained above, when generating a modulo 3 remainder, the present invention is completely unaffected by the ratio of the weight bits of two even power powers and the weight bits of two whole power powers, and is small-scale. In addition, it is possible to obtain the modulo 3 remainder of any multi-digit binary number by repeating a simple circuit, which has the effect of guaranteeing more flexible configurations in the LSI implementation of logic circuits, which has become prominent in recent years. be.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a modulo 3 remainder excavated pottery according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of the A modier shown in Fig. 1, and Fig. 3 is shown in Fig. 1. FIG. 4 is a block diagram showing an example in which the modulo 3 remainder generator of the present invention is applied to an error checking circuit. In the figure, 130, 140.150.160...A module, 170, 180,190...B module, 45
5: Adder, 456: D module, 465: Modulo 3 adder, 466: Comparator, 500: Thick, 600: C module. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In a modulo-3 remainder generator that outputs a modulo-3 remainder of binary data, input lines X_1_0, X_1_1, X_1_2 and output lines Y_1_0, Y_1_1, Y_1_2, Y_
1_3, and the input lines X_1_0, X_1_1
, X_1_2 input binary data x_1_0, x
_1_1, x_1_2, y_1_0=@x@_1_0・x_1_1・x_1_2
+x_1_0・@x@_1_1・x_1_2+x_1_
0・x_1_1・@x@_1_2, @y@_1_0, y_1_1=@x@_1_0・@x@_1_1・x_1
_2+@x@_1_0・x_1_1・@x@_1_2+
x_1_0・@x@_1_1・@x@_1_2, @y@
_1_1 to the output lines Y_1_0, Y_1_1, Y
One or more modulo 3 remainder generating means output from _1_2, Y_1_3, and input lines X_2_0, X_2_1, X_2_2, X_
2_3, X_2_4, X_2_5, X_2_6, X_2
_7 and output lines Y_2_0, Y_2_1, Y_2
_2, Y_2_3, and the input line X_2_0,
X_2_1, X_2_2, X_2_3, X_2_4, X
Modulo 3 data input from _2_5, X_2_6, X_2_7 x_2_0, x_2_1, x_2_2, x
_2_3, x_2_4, x_2_5, x_2_6, x_
y_2_0=x_2_2・x_2_6+x for 2_7
_2_0・x_2_5・x_2_7+x_2_1・x_
2_3・x_2_4, @y@_2_0, y_2_1=x_2_0・x_2_4+x_2_1・x
_2_3・x_2_6+x_2_2・x_2_5・x_
2_7, @y@_2_1 to the output lines Y_2_0, Y_2_1, Y
one or more modulo 3 addition means outputting from _2_2, Y_2_3, and the input line
a first connecting means input to _1_0, X_1_1, X_1_2 and output lines Y_1_0, Y_1_1, Y_1_2, Y_1 of the one or more modulo 3 remainder generating means;
The modulo 3 data x_2_0 output from _3
, x_2_1, x_2_2, x_2_3, x_2_4,
x_2_5, x_2_6, x_2_7 to the input lines X_2_0, X_2_ of the one or more modulo 3 addition means
1, X_2_2, X_2_3, X_2_4, X_2_5
, X_2_6, X_2_7.