JPS6284266U - - Google Patents
Info
- Publication number
- JPS6284266U JPS6284266U JP17343485U JP17343485U JPS6284266U JP S6284266 U JPS6284266 U JP S6284266U JP 17343485 U JP17343485 U JP 17343485U JP 17343485 U JP17343485 U JP 17343485U JP S6284266 U JPS6284266 U JP S6284266U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- differentiates
- input signal
- differentiating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004069 differentiation Effects 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
Description
第１図は、この考案の一実施例を示すブロツク
図である。第２図および第３図は、デイテールの
説明図である。第４図はシヤープネスの説明図で
ある。第５図は、従来のシヤープネスの補正回路
の一例である。第６図は、第５図の回路の動作説
明図である。第７図は、従来のシヤープネスの補
正回路の他の例である。第８図は、第７図の回路
の動作説明図である。第９図は、第１図の回路の
動作説明図である。第１０図は、第１図の回路の
具体例を示す回路図である。
３０…デイレイ・ライン、３６，３７，４２…
微分回路、３８…反転アンプ、３４，４２…加算
器。
FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 and FIG. 3 are explanatory diagrams of details. FIG. 4 is an explanatory diagram of sharpness. FIG. 5 is an example of a conventional sharpness correction circuit. FIG. 6 is an explanatory diagram of the operation of the circuit shown in FIG. FIG. 7 shows another example of a conventional sharpness correction circuit. FIG. 8 is an explanatory diagram of the operation of the circuit shown in FIG. 7. FIG. 9 is an explanatory diagram of the operation of the circuit of FIG. 1. FIG. 10 is a circuit diagram showing a specific example of the circuit shown in FIG. 1. 30...Delay line, 36, 37, 42...
Differentiating circuit, 38...inverting amplifier, 34, 42... adder.
Claims (1)
と、 前記入力信号を微分する第２の微分回路と、 （前記遅延回路の出力）＋（前記第１の微分回
路の出力）−（前記第２の微分回路の出力）を演
算する回路と を具備してなる映像信号補正回路。[Claims for Utility Model Registration] A delay circuit that delays an input signal; a first differentiation circuit that differentiates the output of the delay circuit; a second differentiation circuit that differentiates the input signal; 1. A video signal correction circuit comprising: a circuit for calculating (output) + (output of the first differentiating circuit) - (output of the second differentiating circuit).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17343485U JPS6284266U (en) | 1985-11-11 | 1985-11-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17343485U JPS6284266U (en) | 1985-11-11 | 1985-11-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284266U true JPS6284266U (en) | 1987-05-29 |
Family
ID=31110887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17343485U Pending JPS6284266U (en) | 1985-11-11 | 1985-11-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284266U (en) |
-
1985
- 1985-11-11 JP JP17343485U patent/JPS6284266U/ja active Pending
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