JPS6282808A - Phase shifting circuit - Google Patents

Phase shifting circuit

Info

Publication number
JPS6282808A
JPS6282808A JP22528885A JP22528885A JPS6282808A JP S6282808 A JPS6282808 A JP S6282808A JP 22528885 A JP22528885 A JP 22528885A JP 22528885 A JP22528885 A JP 22528885A JP S6282808 A JPS6282808 A JP S6282808A
Authority
JP
Japan
Prior art keywords
emitter
transistor
reduced
transistors
phase shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22528885A
Other languages
Japanese (ja)
Inventor
Yoshiaki Ishizeki
芳明 石関
Masayoshi Kozuka
小塚 昌由
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP22528885A priority Critical patent/JPS6282808A/en
Publication of JPS6282808A publication Critical patent/JPS6282808A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a phase shifting circuit capable of easily changing a phase shifting value appropriate to the formation of an integrated circuit by adopting circuit constitution using the emitter diffusion capacity of a transistor (TR) as a capacitor element. CONSTITUTION:Generally, the emitter diffusion capacity existing in the TR is proportional to an emitter current IE. When potential VC is boosted or dripped, an emitter current IE is increased or reduced and an emitter current CE2 is reduced or increase. In accordance with said change, the emitter diffusion capacity CED1 of a TR 7 is increased or reduced and the emitter diffusion capacity CDE2 is reduced or increased, so that the phase shift of the 1st signal is increased or reduced and that of the 2nd signal is reduced or increased. The phase shift can be continuously changed 0-90 deg. or 90-0 deg. by selecting the potential VR of a reference signal input terminal 14 and the resistance values of the 1st and 2nd resistors 11, 12 properly.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は移相回路に関し、特に集積回路化に適した移相
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase shift circuit, and particularly to a phase shift circuit suitable for integration into an integrated circuit.

〔従来の技術〕[Conventional technology]

従来の集積回路に適用できる移相回路は、固定の定数を
有するインダクタンス、キャパシタンス及び抵抗等の素
子で構成される場合が多い。
Phase shift circuits applicable to conventional integrated circuits are often constructed of elements such as inductance, capacitance, and resistance having fixed constants.

第2図は従来の移相回路の一例を示す回路図であるO この回路は、固定定数の2個のインダクタンスを直列に
接続しその両端を入力端及び出力端とし、この2個のイ
ンダクタンスの接続点と基準電位端との間に固定定数の
コンデンサを接続したT型の回路構成となっている。従
って、信号周波数一定ならば、入力信号と出力信号との
位相差(以下、移相量という)は、使用される素子の定
数により、一定の値に固定されていた。
Figure 2 is a circuit diagram showing an example of a conventional phase shift circuit. This circuit connects two inductances with fixed constants in series, and uses both ends as an input terminal and an output terminal. It has a T-shaped circuit configuration in which a fixed constant capacitor is connected between the connection point and the reference potential end. Therefore, if the signal frequency is constant, the phase difference between the input signal and the output signal (hereinafter referred to as phase shift amount) is fixed to a constant value depending on the constant of the element used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の移相回路では、周波数一定時における移
相量は使用される素子の定数によって固定される構成と
なっているので、移相量を可変とすることは困難である
という問題点があった。
In the conventional phase shift circuit described above, the amount of phase shift when the frequency is constant is fixed by the constant of the element used, so there is a problem that it is difficult to make the amount of phase shift variable. there were.

本発明の目的は、移相量を容易に変えることができ、し
かも集積回路化に適した移相回路を提供することKある
An object of the present invention is to provide a phase shift circuit that can easily change the amount of phase shift and is suitable for integration into an integrated circuit.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の移相回路は、コレクタが共に電源端子に接続す
る第1及び第2のトランジスタと、コレクタが前記第1
のトランジスタのエミッタに接続しペースが前記第1及
び第2のトランジスタのエミッタ電流を制御する制御信
号入力端に接続する第3のトランジスタと、コレクタが
前記第2のトランジスタのエミッタに接続しエミッタが
前記第3のトランジスタのエミッタと接続しベースが基
準信号入力端に接続する第4のトランジスタと、前記第
3及び第4のトランジスタのエミッタ〈接続する定電流
源と、一端がそれぞれ第1及び第2の信号の入力端に接
続し他端がそれぞれ前記第1及び第2のトランジスタの
ベースに接続すると共に前記第1及び第2の信号の出力
端に接続し前記第1及び第2のトランジスタのエミッタ
拡散容量とでCR回路を形成する第1及び第2の抵抗と
を有している。
The phase shift circuit of the present invention includes first and second transistors whose collectors are both connected to a power supply terminal, and whose collectors are connected to the first transistor.
a third transistor whose pace is connected to the emitter of the transistor and whose pace is connected to a control signal input terminal for controlling the emitter currents of the first and second transistors; and whose collector is connected to the emitter of the second transistor and whose emitter is a fourth transistor connected to the emitter of the third transistor and whose base is connected to the reference signal input terminal; the emitters of the third and fourth transistors are connected to the constant current source; The other end is connected to the input end of the second signal, and the other end is connected to the base of the first and second transistors, respectively, and the output end of the first and second signal is connected to the first and second signal input ends of the first and second transistors. It has first and second resistors forming a CR circuit together with an emitter diffusion capacitor.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

この実施例は、コレクタが電源端子6に接続する第1及
び第2のトランジスタ7.8.!:、コレクタが第1の
トランジスタ7のエミッタに接続しベースが第1及び第
2のトランジスタ7.8のエミッタ電流工El * I
E2を制御する制御信号入力端13に接続する第1のト
ランジスタ9と、コレクタが第2のトランジスタ8のエ
ミッタに接続しエミッタが第3のトランジスタ9のエミ
ッタに接続しペースが基準信号入力端!4に接続する第
4のトランジスタ10と、一端が第3及び第4のトラン
ジスタ9,100エミツタに接続し他端が基準電位端3
に接続する定電流源15と、一端がそれぞれ第1及び第
2の信号の入力端1.4に接続し他端がそれぞれ第1及
び第2のトランジスタ7.8のペースに接続すると共に
第1及び第2の信号の出力端2,5に接続し第1及び第
2のトランジスタ7.8のエミッタ拡散容量CDE1*
 COH2とでCR回路を形成する第1及び第2の抵抗
11.12とを含んで構成されている。
This embodiment consists of first and second transistors 7.8., whose collectors are connected to the power supply terminal 6. ! :, the collector is connected to the emitter of the first transistor 7 and the base is the emitter current of the first and second transistors 7.8 El*I
The first transistor 9 is connected to the control signal input terminal 13 that controls E2, the collector is connected to the emitter of the second transistor 8, the emitter is connected to the emitter of the third transistor 9, and the pace is the reference signal input terminal! 4, one end is connected to the emitters of the third and fourth transistors 9, 100, and the other end is connected to the reference potential terminal 3.
a constant current source 15 connected to the first and second signal input terminals 1.4 at one end and connected to the first and second signal input terminals 1.4, respectively, and the other end connected to the paces of the first and second transistors 7.8, respectively; and the emitter diffusion capacitance CDE1* of the first and second transistors 7.8 connected to the output terminals 2 and 5 of the second signal.
It is configured to include first and second resistors 11 and 12 that form a CR circuit with COH2.

次に、この回路の動作について説−する。Next, the operation of this circuit will be explained.

一般に、トランジスタに存在するエミッタ拡散容量CD
Iは次式で表わすことができる。
In general, the emitter diffusion capacitance CD present in a transistor
I can be expressed by the following formula.

q:電子の電荷 1.602xlO”(C’)k:ポル
ツマy定数 1.384 X l o−2” (Jlo
K)T:絶対温度〔0K〕 W:ベース幅〔m〕 D:拡散定数(m”/8〕 IE:エミッタ電流(A〕 (1)式に示すように、エミッタ拡散容量CDIはエミ
ッタ電流I、と比例関係にある。本実施例においては、
このエミッタ電流I、は定電流源15の電流Isを第3
及び第4のトランジスタ9,10により第1及び第2の
トランジスタ7.8に分流したエミッタ電流”El +
 工12であり、この分流量は、基準信号入力端14の
電位vRに対し制御信号入力端13の電位vcを変える
ことにより差動的に変えることができる。従って、電位
■cを上昇(又は下降)させると、エミッタ電流IEI
は増加(又は減少)してエミッタ電流工E2は減少(又
は増加)シ、これに伴い、第1のトランジスタ7のエミ
ッタ拡散容量CD!!1は増加(又は減少)して第2の
トランジスタ8のエミッタ拡散容量CDE2は減少(又
は増加)するので、gtの信号の移相量力端14の電位
vRと第1及び第2の抵抗の抵抗値を適正に選ぶことに
より、移相量を00付近から90’付近まで(又は90
°付近から00付近まで)連続的に変えることができる
q: Electron charge 1.602xlO"(C') k: Porzmey constant 1.384 X l o-2" (Jlo
K) T: Absolute temperature [0K] W: Base width [m] D: Diffusion constant (m”/8) IE: Emitter current (A) As shown in equation (1), emitter diffusion capacitance CDI is equal to emitter current I There is a proportional relationship with .In this example,
This emitter current I is the third current Is of the constant current source 15.
and the emitter current "El + shunted to the first and second transistors 7.8 by the fourth transistors 9 and 10.
This diversion amount can be changed differentially by changing the potential vc of the control signal input terminal 13 with respect to the potential vR of the reference signal input terminal 14. Therefore, when the potential ■c is raised (or lowered), the emitter current IEI
increases (or decreases), the emitter current E2 decreases (or increases), and along with this, the emitter diffusion capacitance CD! of the first transistor 7! ! 1 increases (or decreases) and the emitter diffusion capacitance CDE2 of the second transistor 8 decreases (or increases), so that the potential vR of the phase shift amount terminal 14 of the signal gt and the resistance of the first and second resistors By choosing the value appropriately, the amount of phase shift can be changed from around 00 to around 90' (or 90').
It can be changed continuously (from around 00° to around 00).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、キャパシタンス素子とし
てトランジスタのエミッタ拡散容量を使用した回路構成
とすることにより、移相量を容易に変えることができ、
しかも集積回路化に適した移相回路を得ることができる
効果がある。
As explained above, the present invention has a circuit configuration that uses the emitter diffusion capacitance of a transistor as a capacitance element, so that the amount of phase shift can be easily changed.
Moreover, there is an effect that a phase shift circuit suitable for integration can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2図は従来
の移相回路の一例を示す回路図である。 1・・・・・・第1の信号の入力端、2・・・・・・第
1の信号の出力端、3・・・・・・基準電位端、4・・
・・・・第2の信号の入力端、5・・・・・・第2の信
号の出力端、6・・・・・・電源端子、7,8,9.1
0・・・・・・トランジスタ、11.12・・・・・・
抵抗、13・・・・・・制御信号入力端、14・・・・
・・基準信号入力端、15・・・・・・定電流源、16
.17・・・・・・インダクタンス、18・・・・・・
コンデンサ。 代理人 弁理士  内 原   晋 酪を図 82図
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional phase shift circuit. 1... Input end of the first signal, 2... Output end of the first signal, 3... Reference potential end, 4...
...Second signal input terminal, 5...Second signal output terminal, 6...Power supply terminal, 7, 8, 9.1
0...Transistor, 11.12...
Resistor, 13... Control signal input terminal, 14...
...Reference signal input terminal, 15... Constant current source, 16
.. 17...Inductance, 18...
capacitor. Figure 82 depicts agent patent attorney Shinro Uchihara.

Claims (1)

【特許請求の範囲】[Claims] コレクタが共に電源端子に接続する第1及び第2のトラ
ンジスタと、コレクタが前記第1のトランジスタのエミ
ッタに接続しベースが前記第1及び第2のトランジスタ
のエミッタ電流を制御する制御信号入力端に接続する第
3のトランジスタと、コレクタが前記第2のトランジス
タのエミッタに接続しエミッタが前記第3のトランジス
タのエミッタと接続しベースが基準信号入力端に接続す
る第4のトランジスタと、前記第3及び第4のトランジ
スタのエミッタに接続する定電流源と、一端がそれぞれ
第1及び第2の信号の入力端に接続し他端がそれぞれ前
記第1及び第2のトランジスタのベースに接続すると共
に前記第1及び第2の信号の出力端に接続し前記第1及
び第2のトランジスタのエミッタ拡散容量とでCR回路
を形成する第1及び第2の抵抗とを有することを特徴と
する移相回路。
first and second transistors whose collectors are both connected to a power supply terminal; whose collectors are connected to the emitter of the first transistor and whose bases are connected to a control signal input terminal that controls emitter currents of the first and second transistors; a fourth transistor whose collector is connected to the emitter of the second transistor, whose emitter is connected to the emitter of the third transistor, and whose base is connected to the reference signal input terminal; and a constant current source connected to the emitter of the fourth transistor, one end connected to the input terminals of the first and second signals, and the other end connected to the bases of the first and second transistors, respectively. A phase shift circuit comprising first and second resistors connected to the output terminals of the first and second signals and forming a CR circuit with the emitter diffusion capacitances of the first and second transistors. .
JP22528885A 1985-10-08 1985-10-08 Phase shifting circuit Pending JPS6282808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22528885A JPS6282808A (en) 1985-10-08 1985-10-08 Phase shifting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22528885A JPS6282808A (en) 1985-10-08 1985-10-08 Phase shifting circuit

Publications (1)

Publication Number Publication Date
JPS6282808A true JPS6282808A (en) 1987-04-16

Family

ID=16826981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22528885A Pending JPS6282808A (en) 1985-10-08 1985-10-08 Phase shifting circuit

Country Status (1)

Country Link
JP (1) JPS6282808A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344303U (en) * 1989-09-04 1991-04-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344303U (en) * 1989-09-04 1991-04-24

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