JPH01183907A - Filter circuit - Google Patents

Filter circuit

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Publication number
JPH01183907A
JPH01183907A JP894088A JP894088A JPH01183907A JP H01183907 A JPH01183907 A JP H01183907A JP 894088 A JP894088 A JP 894088A JP 894088 A JP894088 A JP 894088A JP H01183907 A JPH01183907 A JP H01183907A
Authority
JP
Japan
Prior art keywords
filter
circuit
phase
oscillator
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP894088A
Other languages
Japanese (ja)
Inventor
Jun Koyama
潤 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP894088A priority Critical patent/JPH01183907A/en
Priority to US07/297,426 priority patent/US5023491A/en
Publication of JPH01183907A publication Critical patent/JPH01183907A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain an automatic adjustment by controlling the interruption frequency of the filter of a shifting circuit with the loop of an oscillator, a shifting circuit and a phase comparing circuit. CONSTITUTION:A filter circuit connects the output of an oscillator 1 through a filter 59 to the inverting input of an amplifier 56, connects one edge of resistances 44 and 45 into the non-inverting input of the amplifier 56, connects the input of the filter 59 and other edge of the resistance 44 and the input is executed. The output signal of the oscillator 1 is dislocated to 90 deg. progress (or delay) phase by a shifting circuit 2, the phase comparison is executed for the output signal of the oscillator 1 and the output signal (output signal of 90 deg. progress (or delay) phase of the output signal of the oscillator 1) of the shifting circuit 2 by a phase comparing circuit 3, the output signal of the shifting circuit 2 always becomes the 90 deg. progress (or delay) phase of the output signal of the oscillator and like that, the interruption frequency of the filter 59 is controlled. In the same way, the output signal of the shifting circuit 2 controls the interruption frequency of filters 4 and 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、フィルタの遮断周波数の無調整化に関し、特
に集積回路に内蔵した複数のフィルタの遮断周波数を自
動的に調整制御することにより無調整化を行ったフィル
タ回路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to eliminating the need to adjust the cut-off frequency of a filter, and in particular to eliminating the need to adjust the cut-off frequency of a filter by automatically adjusting and controlling the cut-off frequencies of a plurality of filters built into an integrated circuit. This invention relates to a filter circuit that has been adjusted.

〔従来の技術〕[Conventional technology]

第2図を用いて従来使用されているフィルタ回路につい
て説明する。
A conventionally used filter circuit will be explained with reference to FIG.

従来の2つのフィルタを内蔵するフィルタ回路60は各
入力端6,8から入力された信号をそれぞれのフィルタ
4,5を介して各出力端7,9に出力する。各フィルタ
4,50制御入力端に電圧制御回路10の出力を接続し
、電圧制御回路100制御入力端より可変抵抗11を介
して基準電位に接続して構成している。
A conventional filter circuit 60 incorporating two filters outputs signals inputted from input terminals 6 and 8 to respective output terminals 7 and 9 via respective filters 4 and 5. The output of the voltage control circuit 10 is connected to the control input terminal of each of the filters 4 and 50, and the control input terminal of the voltage control circuit 100 is connected to a reference potential via a variable resistor 11.

この構成のフィルタ4,5は電圧(又は電流)を可変し
て遮断周波数を変える。電圧(又は電流)制御型フィル
タで、可変抵抗11を可変させることで電圧制御回路1
0の出力の電圧を変化させることにより、電圧制御回路
10の出力に接続されているフィルタ4,5の制御入力
端の電圧を変え、各フィルタ4,5の遮断周波数の調整
を行う。
Filters 4 and 5 having this configuration change the cutoff frequency by varying the voltage (or current). A voltage (or current) controlled filter that controls the voltage control circuit 1 by varying the variable resistor 11.
By changing the voltage at the output of the voltage control circuit 10, the voltage at the control input terminals of the filters 4 and 5 connected to the output of the voltage control circuit 10 is changed, and the cutoff frequency of each filter 4 and 5 is adjusted.

第3図は、従来使用しているフィルタ回路6゜の具体例
である。第2図の2つのフィルタを内蔵するフィルタ回
路60で、入力端6からNPN)ランジスタ120ベー
スに接続し、コレクタをPNP)ランジスタ14のベー
スとコレクタとPNPトランジスタ15のベースに接続
し、PNP)ランジスタ15のコレクタをNPN)ラン
ジスタ13のコレクタとNPN)ランジスタ16のベー
スとコンデンサ57の一端に接続し、NPN)ランジス
タ16のエミッタはNPN)ランジスタ13のベースと
抵抗25の一端と出力端7に接続し、NPNトランジス
タ12.13のエミッタとNPNトランジスタ17のコ
レクタを接続しNPN)ランジスタ17のエミッタから
抵抗24を介して低電位端に接続し、PNP)ランジス
タ14.15のエミッタとNPN)ランジスタ16のコ
レクタを高電位端に接続し、コンデンサ57の他端と抵
抗25の他端と低電位端に接続して成るフィルタ4とフ
ィルタ4と同一構成のフィルタ5と高電位端より抵抗2
8と可変抵抗11を介して低電位端に接続して成る室圧
制御回路10と抵抗28と可変抵抗11の接続点よりN
PN)ランジスタ17゜23のベースに接続して構成し
ている。
FIG. 3 shows a specific example of a conventionally used filter circuit 6°. In the filter circuit 60 shown in FIG. 2, which has two built-in filters, the input terminal 6 is connected to the base of the NPN) transistor 120, the collector is connected to the base and collector of the PNP transistor 14, and the base of the PNP transistor 15, The collector of the transistor 15 is connected to the collector of the NPN transistor 13, the base of the NPN transistor 16, and one end of the capacitor 57, and the emitter of the NPN transistor 16 is connected to the base of the NPN transistor 13, one end of the resistor 25, and the output terminal 7. Connect the emitter of the NPN transistor 12.13 and the collector of the NPN transistor 17, connect the emitter of the NPN transistor 17 to the low potential end via the resistor 24, and connect the emitter of the PNP transistor 14.15 to the NPN transistor 17. 16 is connected to the high potential end, and the other end of the capacitor 57, the other end of the resistor 25, and the low potential end are connected to the filter 4, the filter 5 has the same configuration as the filter 4, and the resistor 2 is connected to the high potential end.
N from the connection point of the room pressure control circuit 10 which is connected to the low potential end via the variable resistor 11 and the resistor 28 and the variable resistor 11.
PN) is connected to the base of transistor 17゜23.

次にフィルタ4の遮断周波数の調整について説明する。Next, adjustment of the cutoff frequency of the filter 4 will be explained.

フィルタ4の遮断周波数fLは 2kT    r・ コンデンサ57:Cst、抵抗24.28 ;R24,
1R21、可変抵抗11:Ru、高電位端と低電位端間
の電位;VCClNPN)ランジスタQl?のペースエ
ミッタ間電圧; VBE (Ql?) 、相互コンダク
タンス;g□、電子の電荷: g=6.o 2X 10
−”(c)、ポルツマン定数: k= 1.38 X 
10−23[W−S/” k〕、絶対温度;T で表わせ可変抵抗11を変えることでgmが変化し、そ
の結果フィルタ4の遮断周波数fLが変化する。
The cutoff frequency fL of the filter 4 is 2kTr. Capacitor 57: Cst, resistance 24.28; R24,
1R21, variable resistor 11: Ru, potential between high potential end and low potential end; VCClNPN) transistor Ql? Pace emitter voltage; VBE (Ql?), mutual conductance; g□, electron charge: g=6. o 2X 10
−”(c), Portzmann constant: k= 1.38 X
10-23 [W-S/''k], absolute temperature; expressed as T. By changing the variable resistor 11, gm changes, and as a result, the cutoff frequency fL of the filter 4 changes.

又、フィルタ4とフィルタ5はコンデンサ57゜58や
抵抗24.26を変えることで遮断周波数の異なるフィ
ルタが得られる。
Filters 4 and 5 with different cutoff frequencies can be obtained by changing the capacitors 57 and 58 and the resistors 24 and 26.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のフィルタ回路は、複数のフィルタの内ど
れか一つのフィルタの遮断周波数に着目し、その希望周
波数に成る様に可変抵抗11を調整する必要があり、自
動調整が行われていないという欠点があった。
In the conventional filter circuit described above, it is necessary to focus on the cutoff frequency of one of a plurality of filters and adjust the variable resistor 11 so that the desired frequency is achieved, and automatic adjustment is not performed. There were drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のフィルタ回路は、電圧(又は電流)を可変して
、フィルタの遮断周波数を変える複数の電FE(又は電
流)制御型フィルタ(以下、フィルタと略す)を有し、
発振器の出力を、電圧(又は電流)を可変して入力信号
の位相を変える移相回路の信号入力端と位相比較回路3
の第一の入力に接続し、移相回路の信号出力端を上記位
相比較回路3の第二の入力に接続し、位相比較回路の出
力を前記複数のフィルタの制御入力端に接続しているこ
とを有している。
The filter circuit of the present invention has a plurality of electric FE (or current) controlled filters (hereinafter abbreviated as filters) that vary the voltage (or current) and change the cut-off frequency of the filter,
The signal input terminal of a phase shift circuit that changes the phase of the input signal by varying the voltage (or current) of the output of the oscillator and the phase comparator circuit 3
The signal output terminal of the phase shift circuit is connected to the second input of the phase comparison circuit 3, and the output of the phase comparison circuit is connected to the control input terminals of the plurality of filters. It has that.

〔実施例〕〔Example〕

次に本発明について第1図を用いて説明する。 Next, the present invention will be explained using FIG.

本発明のフィルタ回路は、発振器1の出力をフィルタ5
9を介して増幅器56の反転入力に接続し、抵抗44.
45の一端を増幅器56の非反転入力に接続し、フィル
タ590入力と抵抗44の他端を接続して入力とし、抵
抗45の他端と増幅器56の出入を接続して出力とする
移相回路2において、該移相回路20入力と位相比較回
路3の第一の入力に接続し、移相回路2の出力を位相比
較回路3の第二の入力に接続し、位相比較回路3の出力
を移相回路20制御入力端とフィルタ4.5の制御入力
端に接続する構成で、発振器lの出力信号を移相回路2
にて90°進み(又は遅れ)位相にずらし、位相比較回
路3にて発振器lの出力信号と移相回路2の出力信号(
発振器1の出力信号の90”進み(又は遅れ)位相の出
力信号)とを位相比較を行い、常に移相回路2の出力信
号が発振器の出力信号の90°進み(又は遅れ)位相と
成る様にフィルタ59の遮断周波数を制御を行う。同様
に移相回路2の出力信号がフィルタ4,5の遮断周波数
を制御する。
The filter circuit of the present invention converts the output of the oscillator 1 into the filter 5.
9 to the inverting input of amplifier 56 and resistor 44 .
45 is connected to the non-inverting input of the amplifier 56, the filter 590 input and the other end of the resistor 44 are connected as an input, and the other end of the resistor 45 is connected to the input/output of the amplifier 56 as an output. 2, the input of the phase shift circuit 20 is connected to the first input of the phase comparison circuit 3, the output of the phase shift circuit 2 is connected to the second input of the phase comparison circuit 3, and the output of the phase comparison circuit 3 is connected. The configuration is such that the control input terminal of the phase shift circuit 20 is connected to the control input terminal of the filter 4.5, and the output signal of the oscillator l is connected to the phase shift circuit 20.
The output signal of the oscillator l and the output signal of the phase shift circuit 2 are shifted in phase by 90 degrees in the phase comparator circuit 3 and the output signal of the phase shift circuit 2 (
The output signal of the oscillator 1 is phase-compared with the output signal that is 90 degrees ahead (or behind) of the output signal of the oscillator, so that the output signal of the phase shift circuit 2 is always in the phase that is 90 degrees ahead (or behind) of the output signal of the oscillator. The cutoff frequency of the filter 59 is controlled.Similarly, the output signal of the phase shift circuit 2 controls the cutoff frequency of the filters 4 and 5.

次に第4図の具体的実施例を用いて、フィルタ4.5の
遮断周波数の制御について説明する。
Next, control of the cutoff frequency of the filter 4.5 will be explained using the specific embodiment shown in FIG.

発振器1の出力を移相回路2のNPN)ランジスタ31
のベースと抵抗44を介して増幅器56の非反転入力と
位相比較回路3のNPN)ランジスタ40のベースに接
続し、NPNトランジスタのコレクタはPNP )ラン
ジスタ29のベース・コレクタとPNP )ランジスタ
30のベースに接続し、PNP)ランジスタ30のコレ
クタをNPNトランジスタ32のコレクタとNPN)ラ
ンジスタ33のベースとコンデンサ52の一端に接続し
、NPN)ランジスタ33のエミッタをNPNトランジ
スタ32のベースと増幅器560反転入力と抵抗43の
一端に接続し増幅器56の出力から抵抗45を介して増
幅器56の非反転入力に接続し、NPN)ランジスタ3
1.32のエミッタとNPN)ランジスタ34のコレク
タを接続し、NPN)ランジスタ34のエミッタを抵抗
42を介して低電位端に接続し、NPN)ランジスタ4
0のコレクタにNPN)ランジスタ35.36のエミッ
タを接続し、NPN)ランジスタ35.37のコレクタ
と抵抗46の一端を接続し、NPN)ランジスタ36.
38のコレクタと抵抗47の一端とPNP )ランジス
タ39のベースとコンデンサ53の一端を接続し、NP
N)ランジスタ37゜38のエミッタとNPN)ランジ
スタ41のコレクタを接続しNPN)ランジスタ4oの
エミッタとNPN)ランジスタ41のエミッタ間に抵抗
41を挿入し、NPN)ランジスタ40.41の各エミ
ッタと低電位端間に抵抗48.50を挿入し、NPN)
ランジスタ35.38のベースと増幅器56の出力に接
続しNPN)ランジスタ36.37とバイアス電源54
を接続し、NPN)ランジスタ41のベースにバイアス
電源55を接続し、PNPトランジスタ39のコレクタ
かろ抵抗51を介して低電位端に接続し、PNP)ラン
ジスタ39と抵抗51の接続点からNPN)ランジスタ
34゜17.23のベースに接続し、PNP)ランジス
タ29.30のエミッタとNPN)ランジスタ33のコ
レクタと抵抗46.47の他端を高電位端に接続し、抵
抗43を低電位端に接続して成る移相回路2と位相比較
回路3と従来例(第3図)と同様にフィルタ4,5を接
続して成るフィルタ回路において移相回路の位相特性β
(ω)は β(、)=2jan−’  ω/ω、 で与
えられ、はNPN)ランジスタ31.32から成る差動
増幅器の相互コンタクタンスg。とコンデンサ53(C
aりより決定される遮断周波数ω、で Ca =g m
/ C53である。
The output of the oscillator 1 is transferred to the NPN transistor 31 of the phase shifting circuit 2.
The base of the NPN transistor is connected to the non-inverting input of the amplifier 56 and the base of the NPN) transistor 40 of the phase comparator circuit 3 via the resistor 44, and the collector of the NPN transistor is connected to the base and collector of the PNP) transistor 29 and the base of the PNP) transistor 30. The collector of the PNP transistor 30 is connected to the collector of the NPN transistor 32, the base of the NPN transistor 33, and one end of the capacitor 52, and the emitter of the NPN transistor 33 is connected to the base of the NPN transistor 32 and the inverting input of the amplifier 560. It is connected to one end of the resistor 43 and connected from the output of the amplifier 56 to the non-inverting input of the amplifier 56 via the resistor 45.
1. Connect the emitter of 32 and the collector of NPN) transistor 34, connect the emitter of NPN) transistor 34 to the low potential end via resistor 42, and
The emitters of NPN) transistors 35 and 36 are connected to the collectors of NPN) transistors 35 and 36, and the collectors of NPN) transistors 35 and 37 are connected to one end of a resistor 46.
38 and one end of the resistor 47 and the base of the transistor 39 and one end of the capacitor 53 are connected.
N) Connect the emitters of transistors 37 and 38 and the collector of NPN) transistor 41, insert a resistor 41 between the emitter of NPN) transistor 4o and the emitter of NPN) transistor 41, and connect the emitters of NPN) transistor 40 and 41 to each other. Insert a resistor 48.50 between the potential terminals, NPN)
Connect the bases of transistors 35 and 38 and the output of amplifier 56 (NPN) transistors 36 and 37 and bias power supply 54
A bias power supply 55 is connected to the base of the NPN) transistor 41, and the collector of the PNP transistor 39 is connected to the low potential end via the resistor 51. 34° Connect to the base of 17.23, connect the emitter of PNP) transistor 29.30, the collector of NPN) transistor 33, and the other end of resistor 46.47 to the high potential end, and connect the resistor 43 to the low potential end. In the filter circuit formed by connecting the phase shift circuit 2, the phase comparison circuit 3, and the filters 4 and 5 as in the conventional example (Fig. 3), the phase characteristic β of the phase shift circuit is
(ω) is given by β(,)=2jan-' ω/ω, where is NPN) The mutual contactance g of the differential amplifier consisting of transistors 31 and 32. and capacitor 53 (C
At the cutoff frequency ω, determined from a, Ca = g m
/ C53.

発振器lの出力を移相回路2を介して位相比較回路3に
90°位相遅れの信号をNPN)ランジスタ35.36
のベースに入力し、もう一方の入力(NPN)ランジス
タ40のベース)に発振器1の信号を入力し、この2信
号の位相を比較しその差分をコンデンサ53にて平滑し
てPNP )ランジスタ39を介して移相回路2、フィ
ルタ4゜5のNPN)ランジスタ34,17,23のベ
ースに入力し各フィルタのg。を変化させ、移相回路2
の出力が発振器1の出力信号の90゛位相と成る種制御
し、その時のg、、にて、他のフィルタ4.50g。も
(1)式と同様決定され各フィルタ4,5の遮断周波数
f u41r f L(51は、f L+a = g 
m / 2πC5,。
The output of the oscillator l is sent to the phase comparator circuit 3 via the phase shift circuit 2, and a signal with a 90° phase delay is sent to the NPN) transistor 35.36.
The signal from the oscillator 1 is input to the other input (the base of the NPN transistor 40), and the phases of these two signals are compared and the difference is smoothed by the capacitor 53. G of each filter is input to the base of the NPN) transistors 34, 17, and 23 through the phase shift circuit 2 and the filter 4°5. The phase shift circuit 2
The output of the oscillator 1 is 90° in phase with the output signal of the oscillator 1. At that time, g, the other filter 4.50g. is also determined in the same way as equation (1), and the cutoff frequency of each filter 4, 5 is f u41r f L (51 is f L+a = g
m/2πC5,.

fL(5+:gIIl/2πaSS  と成る。fL(5+:gIIl/2πaSS).

各フィルタ4,50gゆは、抵抗42,24.26に比
をもたせることにより各フィルタ4,5の遮断周波数を
変えられるだけでなく、コンデンサ57゜58.52に
比をもたせることで同様に遮断周波数を変えられ、希望
のフィルタ特性が得られる。
For each filter 4 and 50g, not only can the cutoff frequency of each filter 4 and 5 be changed by setting a ratio between the resistors 42 and 24.26, but also the cutoff frequency of each filter 4 and 5 can be changed by setting a ratio between the capacitors 57 and 58.52. You can change the frequency and get the desired filter characteristics.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、発振器1と移相回路2と位
相比較回路3のループにて移相回路2のフィルタ59と
フィルタ4,5の遮断周波数を制御することにて、従来
は、可変抵抗11を調整して遮断周波数を合わせていた
が、その調整を自動調整とすることが可能になった。
As explained above, the present invention controls the cut-off frequencies of the filter 59 of the phase shift circuit 2 and the filters 4 and 5 using the loop of the oscillator 1, the phase shift circuit 2, and the phase comparison circuit 3. The cutoff frequency was previously matched by adjusting the variable resistor 11, but now it is possible to do this automatically.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成図、第2図は従来の構
成図、第3図は従来の具体的実施例、第4図は第1図の
具体的実施回路図である。 1・・・・・・発振器、2・・・・・・移相回路、3・
・・・・・位相比較回路、4,5.59・・・・・・フ
ィルタ、6,8・・・・・・フィルタの入力、7.9・
・・・・・フィルタの出力、10・・・・・・電圧制御
回路、11・・・・・・可変抵抗、57.58゜52.
53・・・・・・コンデンサ、12,13,16゜17
.18,19,22,23,31,32,33゜34.
35,36,37,38,40.41・・・・・・NP
N)ランジスタ、14,15,20,21,29,30
゜39・・・・・・PNP トランジスタ、54.55
・・・・・・バイアス電源、24.25.26.27.
28.42.43゜44、45.46.47.48.4
9.50.51・・・・・・抵抗、56・・・・・・増
幅器、60・・・・・・従来のフィルタ回路。 代理人 弁理士  内 原   音 〉 3    第1旧
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a conventional block diagram, FIG. 3 is a specific conventional embodiment, and FIG. 4 is a specific implementation circuit diagram of FIG. 1... Oscillator, 2... Phase shift circuit, 3.
...Phase comparator circuit, 4,5.59...Filter, 6,8...Filter input, 7.9.
... Filter output, 10 ... Voltage control circuit, 11 ... Variable resistor, 57.58°52.
53... Capacitor, 12, 13, 16゜17
.. 18, 19, 22, 23, 31, 32, 33° 34.
35, 36, 37, 38, 40.41...NP
N) Transistor, 14, 15, 20, 21, 29, 30
゜39...PNP transistor, 54.55
...Bias power supply, 24.25.26.27.
28.42.43°44, 45.46.47.48.4
9.50.51...Resistor, 56...Amplifier, 60...Conventional filter circuit. Agent Patent Attorney Oto Uchihara〉 3 1st Old

Claims (1)

【特許請求の範囲】[Claims] フィルタの遮断周波数が変わる制御型フィルタを有し、
発振器の出力を移相回路の信号入力端と位相比較回路の
第一の入力とに接続し、上記移相回路の信号出力端を上
記位相比較回路の第二の入力に接続し、上記位相比較回
路の出力を上記複数の制御型フィルタの制御入力端と前
記移相回路の制御入力端とに接続したことを特徴とする
フィルタ回路。
It has a control type filter that changes the cut-off frequency of the filter,
The output of the oscillator is connected to the signal input terminal of the phase shift circuit and the first input of the phase comparison circuit, and the signal output terminal of the phase shift circuit is connected to the second input of the phase comparison circuit. A filter circuit characterized in that an output of the circuit is connected to control input terminals of the plurality of control type filters and a control input terminal of the phase shift circuit.
JP894088A 1988-01-18 1988-01-18 Filter circuit Pending JPH01183907A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP894088A JPH01183907A (en) 1988-01-18 1988-01-18 Filter circuit
US07/297,426 US5023491A (en) 1988-01-18 1989-01-17 Filter circuit arrangements with automatic adjustment of cut-off frequencies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP894088A JPH01183907A (en) 1988-01-18 1988-01-18 Filter circuit

Publications (1)

Publication Number Publication Date
JPH01183907A true JPH01183907A (en) 1989-07-21

Family

ID=11706667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP894088A Pending JPH01183907A (en) 1988-01-18 1988-01-18 Filter circuit

Country Status (1)

Country Link
JP (1) JPH01183907A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03173217A (en) * 1989-12-01 1991-07-26 Matsushita Electric Ind Co Ltd Automatic adjusting device for filter
JPH0490210A (en) * 1990-08-02 1992-03-24 Sharp Corp Active filter circuit
JPH0467818U (en) * 1990-10-24 1992-06-16

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60126908A (en) * 1983-12-13 1985-07-06 Sony Corp Filter device
JPS60214617A (en) * 1984-04-11 1985-10-26 Hitachi Ltd Filter integrated circuit
JPS61281613A (en) * 1985-05-20 1986-12-12 Sanyo Electric Co Ltd Automatic adjusting device for active filter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60126908A (en) * 1983-12-13 1985-07-06 Sony Corp Filter device
JPS60214617A (en) * 1984-04-11 1985-10-26 Hitachi Ltd Filter integrated circuit
JPS61281613A (en) * 1985-05-20 1986-12-12 Sanyo Electric Co Ltd Automatic adjusting device for active filter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03173217A (en) * 1989-12-01 1991-07-26 Matsushita Electric Ind Co Ltd Automatic adjusting device for filter
JPH0490210A (en) * 1990-08-02 1992-03-24 Sharp Corp Active filter circuit
JPH0467818U (en) * 1990-10-24 1992-06-16

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