JPS6282715A - Cmos gate circuit - Google Patents

Abstract

PURPOSE:To prevent generation of a waveform distortion between input and output by adjusting the width and length of a gate pattern of each channel element so as to make the leading time and trailing time equal to each other. CONSTITUTION:When common power supplies VDD, VSS are given to a P-channel MOS-FET1 and an N-channel MOS-FET2, the width W/length L of gates Gp1, Gn1 are set in response to values K', Vth of each channel element so as to make the operating current IDS equal to each other. Thus, the leading and trailing time are made equal and generation of waveform distortion is prevented in applications such as jitter absorption in a video disc reproducing device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a binary signal delay circuit using a CMOS gate circuit, which eliminates waveform distortion (delay time distortion) of an output signal with respect to an input signal. related to what was done.

Lt9 appetizer] As shown in Figure 2, the CMOS gate circuit consists of P-channel MO8-FET12 and N-channel MO8-FET1.
4 are connected between the gates and the drains are connected to each other, and the source is connected to the power supply voltage ■8. .

VSS is applied to each, a signal is input to the gate via the input terminal 13, and an inverted signal of the input signal is taken out from the drain to the output terminal 15.

In this CMOS gate circuit 10, a delay time occurs between the input and the output. As shown in FIG. 3, this delay time is equal to the power supply voltage ■. o 'ss depends on the supply voltage V
. The smaller o'ss is, the larger the delay time is, and the larger the rate of change thereof. This is because the conductance of the element changes depending on the M source voltage 00-VSS. Therefore, by utilizing this property, it is possible to control the delay time to an arbitrary value by adjusting the magnitude of the power supply voltage vDD-VS8. Further, by connecting the CMOS gate circuits 10 in multiple stages as shown in FIG. 4, a long delay time can be obtained.

According to a signal delay circuit using such a CMOS gate circuit 10, for example, a technique for delaying a pulse frequency modulation signal containing analog information on the time axis, for example, a technique for delaying a jitter (time delay) in a reproduced video signal in a video disc reproduction device. It can be used to absorb shaft fluctuations. this is,
A reproduced video signal containing jitter is input to a CMOS gate circuit, a color burst signal is extracted from the video signal output from this CMOS gate circuit, and this is converted into a 3.58M1lz crystal oscillation signal corresponding to the subcarrier of the color burst. Compare the phase with the clock and adjust the CM according to the phase error.
By controlling the power supply voltage V[1O-v88 of the OS gate circuit, the CMOS gate circuit outputs a video signal in which jitter has been absorbed.

By the way, when converting the CMOS gate circuit 10 of FIG. 2 into an IC, an IC pattern has conventionally been constructed so that the P channel side and the N channel side are symmetrical, as shown in FIG. 5, for example.

However, when the CMOS gate circuit 10 with such an IC pattern is used as a delay element, as will be explained below, there will be a difference in the rise and fall characteristics of the output, which makes it difficult to use the CMOS gate circuit 10 for jitter absorption in video disc playback as described above. In this case, the duty ratio of the input/output pulse waveform changes, making it difficult to faithfully reproduce information recorded on the disc.

That is, as shown in FIG. 6, in the CMOS gate circuit 10, due to the load capacitor ff1C formed on the output side, a charging/discharging current flows when the output is inverted, and a delay characteristic is obtained by this charging/discharging.

By the way, the current characteristics of a MOS-FET are expressed by Shockley's equation, and can be divided into a non-saturation region and a saturated region depending on the magnitude relationship between the MOS and (68-2th).

In other words, ■. 8 is (1) IoS-K (2(Vo8-V,, > ■os-vas
)...l V l < l VoS-V
thl...(1,1)(2) When in the saturated region! , 8-K (V68-Vth) 2 -・-・-I V, 81 ≧l Vas-vth'-(
1, 2). Here, K is the type of gate metal, the type and thickness of gate insulator, and the impurity concentration in the silicon substrate.
It is a constant determined by the potential difference between the source and the substrate, the size of the gate, etc., and can be expressed as K--'...-(1,3>).

When the structure and pattern arrangement of the MOS-FET are designed as shown in Fig. 5, L and W are the channel length and width of the MOS-FET, ε and t are the dielectric constant and thickness of the gate oxide ox ox film, and μ is the It is the mobility of carriers in the channel. Further, vth in the above formula is given as: Here, φH3 is the work function difference between metal and silicon, QS
S is the surface state charge density, and the substrate is P (N-channel MO
S-FET), the board is N (P channel MOS
-FET), -1φ is the Fermi unit of the substrate.

In the above equation (1, 1) (1, 3), K'vth is
This is a value that is uniquely determined at the time of IC creation (however, the pressure conditions are different for P channel and N channel, and - is a variable element. Therefore, the conventional CMOS gate circuit 10 of FIG. like,
Assuming that the P channel and the N channel have the same voltage, the 'DS' of the P channel and the N channel are different under the same voltage condition. i.e. capacity charging/
The discharging time is different (generally, since the P channel's is small, ■ os decreases and the capacitance charging time (rise TR)
is long, and the capacitance discharge time (falling T,) is short. ).

Therefore, when the CMOS gate circuits 10 are connected in cascade as shown in FIG. 7(a), if TR=T, then FIG.
However, in the conventional IC pattern shown in FIG. 5, since TR>TF, the pattern becomes as shown in FIG. 7 <C>. As a result, as shown in FIG. 8, the duty of the output signal becomes smaller with respect to the input signal, and in applications such as the jitter absorption of the video disk playback signal mentioned above,
This results in waveform distortion (lack of information on the time axis), resulting in distortion of the immediate playback output. In particular, as the input signal approaches the operable upper limit frequency, the asymmetry in the operation of each stage increases (at the end of charging or discharging, the power supply voltage
(because it becomes impossible to reach the target), causing even greater distortion.

[Problem that the invention seeks to solve]

The present invention solves the problems in the conventional technology and prevents waveform distortion between input and output by making the rise time T and fall time TF equal.
It is intended to provide an OS gate circuit.

[Means for solving problems]

In this invention, the width and length of the gate pattern of each channel element are adjusted so that the operating current value of each channel element becomes equal when the same external voltage condition is applied to each channel element. It is.

[For production]

According to the solution of the present invention, by adjusting the width and length of the gate pattern of each P1N channel element, the rise time and fall time can be made equal, thereby preventing the occurrence of waveform distortion. be able to.

〔Example〕

An embodiment of the invention is shown in FIG. This cascades a CMOS gate circuit 20-1 composed of a P-channel MO8-FET1 and an N-channel MO8FET2, and a CMOS gate circuit 20-2 composed of a P-channel MO8-FET3 and an N-channel MOS-FET4. The connected electrical circuit is shown in Figure 9.

In FIG. 1, the input signal is input from the terminal 22,
The gates a, 1. of the first stage 20-1 are connected via the wiring 24. G
applied to nl. The power source ■Do is supplied via the electrode 26,
It is applied to source Sp1. The electrode vSS connects to the source S via the electrode 28. 1. The output signals of the drains Dp1 and Dnl are transmitted from the terminal 30 to the gate Gp2 of the second stage 20-2 via the wiring 31. Applied to Gn2.

In the second stage 20-2, the power supply V. 0 is applied to the source Sp2 via the electrode 26. The power supply VSS is connected to the electrode 28
Source S via. 2 is applied. And drain D
The output signal of D is outputted via terminal 32 p2 and n2.

P-channel MOS-FET1 gate G, 1 and N-channel MO8-FET2 (1) gate G,, (7)
An enlarged view is shown in FIG.

P channel MO8-FET1 and N channel MO8-
Power supply common to FET2 ■. o, ■ When given 88, ■
The width of the gate Gp1°Gol (W
)/length (L) of each channel element, Vth
Set according to the value of As a result, N channel MO8
-FETI W/L is P channel MO8-FET2
It becomes smaller than W/L of.

Gate Gp1. An example of the dimensions of Go1 is shown in the table below.

However, W,' is an effective length, which becomes shorter than the design values W, L due to the manufacturing process as shown by the following equation.

w=W-1,5 41=L-1,0 Configure the CMOS gate circuit 20 with the above design values,
FIGS. 11 and 12 show input and output waveforms when three of these are connected in cascade as shown in FIG. 10.

Figure 11 shows the input waveform at the rising edge, and Figure 12 shows the input waveform at the rising edge.
This is at the falling edge of the input waveform. It can be seen that the rise time and fall time of each stage output are equal in both cases.

Note that in FIGS. 11 and 12, the delay time is one stage.

〔Effect of the invention〕

As explained above, according to the present invention, when the width and length of the gate pattern of each channel element are adjusted and the same external voltage condition is applied to each channel element, the operating current value of each channel element is The rise time and the fall time can be set to be equal, thereby making it possible to prevent the generation of waveform distortion even in applications such as jitter absorption in video disc playback devices.

[Brief explanation of drawings]

FIG. 1 is an IC pattern showing an embodiment of the present invention. FIG. 2 is a diagram showing a CMOS gate circuit. FIG. 3 is a diagram showing power supply voltage-delay time characteristics in a CMOS gate circuit. FIG. 4 is a diagram showing a delay circuit configured by connecting CMOS gate circuits in multiple stages. FIG. 5 shows an IC pattern of a conventional CMOS gate circuit. FIG. 6 is an equivalent circuit of a CMOS gate circuit. FIG. 7 is a waveform diagram showing signal delay operation by the CMOS gate circuit. FIG. 8 shows the rise time TR and the fall time T. FIG. 3 is a waveform diagram showing distortion of the output waveform due to a difference in the output waveform. FIG. 9 is an electrical circuit diagram of the IC pattern of FIG. 1. FIG. 10 is a circuit diagram showing a state in which three CMOS gate circuits according to the present invention are connected in cascade. 11 and 12 are waveform diagrams of various parts in the circuit of FIG. 10, with FIG. 11 showing the waveform at the time of input rising, and FIG. 12 showing the waveform at the time of input falling. 20.20-1.20-2...CMOS gate circuit,
1.3...P channel MO8-FET. 2.4...Channel MO8-FET, Gp1. G.D.
3゜Gol, Gn2...gate. SS Figure 4

Claims (1)

[Claims] In a CMOS gate circuit formed by cascading N-channel and P-channel MOS transistors, the width and length of the gate pattern of each channel element are adjusted, and the same gate pattern is applied to each channel element. A CMOS characterized in that the operating current values of each channel element are set to be equal when an external voltage condition is applied.
gate circuit. 2. The CMOS gate circuit according to claim 1, wherein (width/length) of the N-channel element gate pattern is smaller than (width/length) of the P-channel element gate pattern.