JPS6281203U - - Google Patents

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Publication number
JPS6281203U
JPS6281203U JP17312985U JP17312985U JPS6281203U JP S6281203 U JPS6281203 U JP S6281203U JP 17312985 U JP17312985 U JP 17312985U JP 17312985 U JP17312985 U JP 17312985U JP S6281203 U JPS6281203 U JP S6281203U
Authority
JP
Japan
Prior art keywords
output
calculation means
zero
reset
manipulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17312985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17312985U priority Critical patent/JPS6281203U/ja
Publication of JPS6281203U publication Critical patent/JPS6281203U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す構成図、第2
図は従来技術の一例を示す構成図、第3図、第4
図はその動作説明図である。 14……調節計、142……比例演算手段、1
43……積分演算手段、144……リセツトリミ
ター手段、145……加算手段、146……クラ
ンプ手段。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figures are block diagrams showing an example of conventional technology, Figures 3 and 4.
The figure is an explanatory diagram of the operation. 14...Controller, 142...Proportional calculation means, 1
43... Integral calculating means, 144... Reset limiter means, 145... Adding means, 146... Clamping means.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 設定値と測定値の偏差を比例および積分演算す
る演算手段と、積分演算手段の出力がゼロ以下に
なるのを制限するリセツトリミター手段と、この
リセツトリミタ手段よりの出力と上記比例演算手
段の出力を加算して操作出力を発信する加算手段
と、上記操作出力がゼロのとき上記積分演算手段
の出力を強制的にゼロにするクランプ手段とより
なるリセツトリミター付き調節計。
a calculation means for proportionally and integrally calculating the deviation between the set value and the measured value; a reset limiter means for limiting the output of the integral calculation means from going below zero; and an output from the reset limiter means and an output from the proportional calculation means. A controller with a reset limiter comprising an addition means for adding and transmitting a manipulated output, and a clamp means for forcibly setting the output of the integral calculation means to zero when the manipulated output is zero.
JP17312985U 1985-11-11 1985-11-11 Pending JPS6281203U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17312985U JPS6281203U (en) 1985-11-11 1985-11-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17312985U JPS6281203U (en) 1985-11-11 1985-11-11

Publications (1)

Publication Number Publication Date
JPS6281203U true JPS6281203U (en) 1987-05-23

Family

ID=31110299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17312985U Pending JPS6281203U (en) 1985-11-11 1985-11-11

Country Status (1)

Country Link
JP (1) JPS6281203U (en)

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