JPS6278864A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6278864A JPS6278864A JP60219395A JP21939585A JPS6278864A JP S6278864 A JPS6278864 A JP S6278864A JP 60219395 A JP60219395 A JP 60219395A JP 21939585 A JP21939585 A JP 21939585A JP S6278864 A JPS6278864 A JP S6278864A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- chip
- frame
- decoupling capacitor
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置に関し、特に表面実装型半導体装
置に外付けする電源電圧平滑用コンデンサの該表面実装
型半導体装置のパッケージ内への組み込みに関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly relates to incorporating a power supply voltage smoothing capacitor externally attached to a surface-mounted semiconductor device into a package of the surface-mounted semiconductor device. It is something.
［従来の技術］
ダイナミック型、スタティック型をはじめとするＭＯＳ
ＲＡＭは、微細化技術の発展とともにメモリ容量の
大容量化が進んでいる。最近では、１Ｍピット／チップ
のダイナミックメモリや２５６にビット／チップのスタ
ティックメモリが発表され、既に４Ｍビット／チップの
開発も始まっている。これらの高密度化は機器の小型化
、低消費電力化に非常に効果的であり、今後も従来同種
の開発スピードで大容量メモリが開発されると推定され
る。[Conventional technology] MOS including dynamic type and static type
The memory capacity of RAM is increasing with the development of miniaturization technology. Recently, dynamic memory with 1M bits/chip and static memory with 256 bits/chip have been announced, and development of 4M bits/chip has already begun. These higher densities are extremely effective in reducing the size and power consumption of devices, and it is estimated that large-capacity memories will continue to be developed at the same development speed as before.
一方、最近は、与えられた半導体チップを用いていかに
高密度実装するかが大きな技術課題としてクローズアッ
プされてきた。そのため、ＳＭＤ（Ｓ ｕｒｆａｃｅ
ｌｙｌ ｏｕｎｔ Ｑ ｅｖｉｃｅ ）と呼ばれる
表面実装型パッケージ技術が進んできている。On the other hand, recently, the issue of how to implement high-density packaging using a given semiconductor chip has been highlighted as a major technical issue. Therefore, SMD (Surface
A surface mount packaging technology called lyl mount Qevice is progressing.
第３図（ａ）、（ｂ）は、高密度実装のために製品化さ
れたメモリモジュールの例を示す外形図であり、パッケ
ージ内にメモリチップを封入したｐ ＣＣ（ｐ １ａｓ
ｔｉｃ ｌ ｅａｄｅｄ Ｃｈｉｐ Ｃａｒｒ！
ｅｒ ）と呼ばれる表面実￥ｉ型半導体デバイスを基板
の上に並べてＸ４．Ｘ８．ｘ９などのメモリ構成のモジ
ュールを作り、高田度実装を行なっている。ざらに詳細
に説明すると、第３図（ａ ）において、基板１に１ｍ
個のＰＣＣ３がリード２を介し設けられており、デカッ
プリングコンデンサ４が基板１の裏面に取付けられてい
る。また、第３図（ｂ）において、基板１に複数個のＰ
ＣＣ３がリード２を介して設けられており、デカップリ
ングコンデンサ４がＰＣＣ３の下に入り込むような形で
基板１の表面に取付けられている。FIGS. 3(a) and 3(b) are outline drawings showing an example of a memory module commercialized for high-density packaging.
Tic l eaded Chip Carr!
X4. X8. We are creating modules with memory configurations such as x9, and implementing Takada. To explain in more detail, in FIG. 3(a), a 1 m long
PCCs 3 are provided via leads 2, and a decoupling capacitor 4 is attached to the back surface of the substrate 1. In addition, in FIG. 3(b), a plurality of P
A CC3 is provided via a lead 2, and a decoupling capacitor 4 is attached to the surface of the substrate 1 so as to fit under the PCC3.
第４図は、第３図（ａ）、（ｂ）のＰＣＣの構造を示す
断面図である。図において、ＰＣＣ３はモールド型Ｄ
Ｉ Ｐ （Ｄｕａｌ Ｉ ｎ１ｉｎｅ ｐａｃｋ
ａｇｅ）製品と同様にアセンブリされる。すなわち、Ｐ
ＣＣ専用のフレーム５に対してチップ（メモリＬＳＩ＞
６をダイボンドした後、このフレーム５とチップ６間を
ＡＵワイヤ７でワイヤボンドする。次に、モールド開所
８によりチップ６をコートし、最後にリードをカットし
て曲げるとＰＣＣ３ができ上がる。ここで、２は曲げら
れた状態のリードである。このようなＰＣＣ３において
は、フレーム５の厚みは０．１５１１１１１．チップ６
の厚みは０゜５ＩＩＩｌｌ、パッケージの高さが約３Ｉ
ＩＩＩＩｌであるので、チップ６上のモールド樹脂８の
厚みおよびフレーム５下のモールド樹脂８の厚みが十分
にある、すなわちパッケージの高さ方向に対する余裕が
ある。FIG. 4 is a sectional view showing the structure of the PCC shown in FIGS. 3(a) and 3(b). In the figure, PCC3 is mold type D
I P (Dual I n1ine pack)
age) is assembled in the same way as the product. That is, P
A chip (memory LSI>
6 is die-bonded, the frame 5 and the chip 6 are wire-bonded using an AU wire 7. Next, the chip 6 is coated using the mold opening 8, and finally the leads are cut and bent to complete the PCC 3. Here, 2 is a lead in a bent state. In such a PCC 3, the thickness of the frame 5 is 0.1511111. chip 6
The thickness of the package is 0°5IIIll, and the height of the package is about 3I.
Therefore, the thickness of the molding resin 8 on the chip 6 and the thickness of the molding resin 8 under the frame 5 are sufficient, that is, there is sufficient margin in the height direction of the package.
このメモリモジュールの製造における最大の課題は、デ
カップリングコンデンサ４の取付けである。メモリＬＳ
Ｉ、特にダイナミックＲＡＭでは、チップの動作により
瞬時に大電流が流れ、その電流によるノイズが電源ライ
ンの電圧変動を起こし、メモリモジュールやメモリボー
ドの誤動作を引き起こすことがある、そのためＶＣＣと
Ｖｓｓ間にデカップリングコンデンサを挿入して電源電
圧の変動を吸収させる必要があり、第３図（ａ）。The biggest challenge in manufacturing this memory module is the attachment of the decoupling capacitor 4. Memory LS
I. Particularly in dynamic RAM, large currents flow instantaneously due to chip operation, and the noise caused by this current may cause voltage fluctuations in the power supply line, causing malfunctions of memory modules and memory boards. It is necessary to insert a decoupling capacitor to absorb fluctuations in the power supply voltage, as shown in Figure 3(a).
＜ｂ＞のようにデカップリングコンデンサ４を取付けて
いる。一般的には、デカップリングコンデンサ４として
０．１μＦ以上のコンデンサが用いられており、その取
付個数は１コンデンサ／デバイスである。A decoupling capacitor 4 is attached as shown in <b>. Generally, a capacitor of 0.1 μF or more is used as the decoupling capacitor 4, and the number of capacitors installed is one capacitor/device.
［発明が解決しようとする問題点］
ところで、第１図（ａ ）のメモリモジュールでは、デ
カップリングコンデンサ４を基板］の裏面に取付けてい
るため、ハンドリング時に他の物体に接触してデカップ
リングコンデンサ４にクラックが発生したり、またＶ
Ｐ Ｓ （Ｖａｐｅｒ ｐｈａｓｅ３ ｏｌｄｔｒｉ
ｎａ）装置が使いにくいという問題点があり、ざらにメ
モリモジュールの厚みが増すなどの問題点があった。一
方、第３図（ｂ）のメモリモジュールでは、デカンブリ
ングコンデンサ４がＰＣＣ３の下に入り込んでおり、メ
モリモジュールの厚みおよびデカップリングコンデンサ
４のクラックに対する対策はとられているが、デカップ
リングコンデンサ４がＰＣＣ３の下に表面実装されるた
め、デカップリングコンデンサ４の目視検査がしにくく
、またデカップリングコンデンサ４の基板１への接着の
良否を電気的に測定してチェックできないという欠点が
あり、信頼性確認上重大な問題点があった。これらの問
題点は、ＰＣＣをメモリモジュールに用いる場合だけで
なく、ＰＣＣをメモリボードに直付けする場合にも起こ
ると考えられる。[Problems to be Solved by the Invention] By the way, in the memory module shown in FIG. 1(a), since the decoupling capacitor 4 is attached to the back side of the substrate, the decoupling capacitor may come into contact with other objects during handling. Cracks may occur in 4, or V
P S (Vaper phase3 oldtri
na) There were problems in that the device was difficult to use, and the thickness of the memory module increased. On the other hand, in the memory module shown in FIG. 3(b), the decoupling capacitor 4 is inserted under the PCC 3, and although measures have been taken against the thickness of the memory module and cracks in the decoupling capacitor 4, the decoupling capacitor 4 Since the decoupling capacitor 4 is surface-mounted under the PCC 3, it is difficult to visually inspect the decoupling capacitor 4, and the adhesion of the decoupling capacitor 4 to the substrate 1 cannot be checked electrically. There were serious problems with gender confirmation. These problems are thought to occur not only when a PCC is used in a memory module, but also when a PCC is directly attached to a memory board.
この発明は上記のような問題点を解消するためになされ
たもので、実装方法が非常に簡単になるとともに、実装
密度および信頼性を向上させることができる半導体装置
を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can be mounted very simply and has improved packaging density and reliability.
［問題点を解決するための手段］
この発明に係る半導体装置は、表面実装型半導体装置の
実装時にこの表面実装型半導体装置に必ず外付けしなけ
ればならない電源電圧平滑用コンデンサを、この表面実
装型半導体装置のパッケージ内に組み込むようにしたも
のである。[Means for Solving the Problems] The semiconductor device according to the present invention has a power supply voltage smoothing capacitor that must be externally attached to the surface mount type semiconductor device when the surface mount type semiconductor device is mounted. The device is designed to be incorporated into a package of a type semiconductor device.
［作用］
この発明においては、電源電圧平滑用コンデンサが表面
実装型半導体装置の中に組み込まれているので、この表
面実装型半導体装置のみを実装すればよい。[Function] In the present invention, since the power supply voltage smoothing capacitor is built into the surface mount type semiconductor device, it is only necessary to mount this surface mount type semiconductor device.
［実価例］ 以下、この発明の実施例を図について説明する。[Actual value example] Embodiments of the present invention will be described below with reference to the drawings.
なお、この実施例の説明において、従来の技術の説明と
重複する部分については適宜その説明を省略する。In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.
第１図は、この発明の実施例であるＰＣＣの構造を示す
断面図である。このＰＣＣのアセンブリについて説明す
ると、図において、ＰＣＣ専用のフレーム５を用意する
。このときフレーム５の表面および裏面をダイボンドで
きるようにしておく。FIG. 1 is a sectional view showing the structure of a PCC that is an embodiment of the present invention. To explain the assembly of this PCC, as shown in the figure, a frame 5 dedicated to the PCC is prepared. At this time, the front and back surfaces of the frame 5 are made ready for die bonding.
次に、チップ〈メモリＬＳＩ）６を従来と同様にはんだ
ダイボンドなどの導電性材料によりフレーム５の表面に
ダイボンドする。導電性材料を用いるのは、メモリＬＳ
ＩがＶｌｌ＆電圧を内部発生させフレーム５が負電圧と
なるため、導電性を重視する必要があるからである。次
に、フレーム５の裏面にチップ（デカップリングコンデ
ンサ）１０をエポキシボンディングなど熱部えなくても
良い方法によりダイボンドする。このとき、エポキシは
非導電性のものがよい。メモリＬＳＩで発生する負電圧
がチップ（デカップリングコンデンサ）１０に影響を及
ぼすことを避けるためである。しかし、負電圧の影響が
大きな問題にならなければ、エポキシは導電性材料であ
ってもよい。次に、従来と同様に、チップ６とフレーム
５とを超音波などを用いてＡＵワイヤ７によりワイヤボ
ンディングする。このあと、フレーム５を逆に、チップ
１０とフレーム５とを超音波などを用いてＡＬＩワイヤ
７によりワイヤボンディングする。このとき、ワイヤボ
ンディングはチップ１０のＶｃｃとＶｓ、に対して行な
えばよい。この工程以降は、従来と同様にモールド樹脂
８によりチップ６，１ｏをコートし、リードをカットし
て曲げると従来のＰＣＣと同一形状でかつデカップリン
グコンデンサが組み込まれたＰＣＣ３０ができ上がる。Next, the chip (memory LSI) 6 is die-bonded to the surface of the frame 5 using a conductive material such as solder die-bonding as in the conventional method. Memory LS uses conductive materials
This is because I internally generates the Vll&voltage and the frame 5 becomes a negative voltage, so it is necessary to place emphasis on conductivity. Next, a chip (decoupling capacitor) 10 is die-bonded to the back surface of the frame 5 by a method such as epoxy bonding that does not require heating. At this time, the epoxy should preferably be non-conductive. This is to prevent negative voltage generated in the memory LSI from affecting the chip (decoupling capacitor) 10. However, the epoxy may be a conductive material if the effects of negative voltage are not a major problem. Next, as in the prior art, the chip 6 and the frame 5 are wire-bonded with the AU wire 7 using ultrasonic waves or the like. Thereafter, the frame 5 is reversed, and the chip 10 and the frame 5 are wire-bonded with the ALI wire 7 using ultrasonic waves or the like. At this time, wire bonding may be performed to Vcc and Vs of the chip 10. After this step, the chips 6 and 1o are coated with molding resin 8 in the same manner as before, and the leads are cut and bent to create a PCC 30 that has the same shape as a conventional PCC and incorporates a decoupling capacitor.
ここで、２は曲げられた状態のリードを示している。Here, 2 indicates a lead in a bent state.
第２図は、第１図のチップ（デカップリングコンデンサ
）１０の構造の一例を示す断面図である。FIG. 2 is a sectional view showing an example of the structure of the chip (decoupling capacitor) 10 shown in FIG.
図において、チップ１０は、０．１μＦ以上の容量値と
なるようなコンデンサでよいので微細加工の必要性はな
い。チップ１０は、Ｐ形シリコン基板１１と、この基板
上に形成される素子間分離領ｌｉｔ！１２と、この基板
上に形成され電極となるＮ＋形拡散履１３と、このＮ＋
形拡散層上に形成される第１醒化膜１４と、この第１酸
化膜上に形成され電極となる第１ポリシリコン膜１５と
、この第１ポリシリコン膜上に形成される第２酸化膜１
６と、この第２酸化幌上に形成され電極となる第２ポリ
シリコン摸１７とから構成されており、たとえば、第１
ポリシリコン１１５の電極はＶ、。In the figure, the chip 10 may be a capacitor having a capacitance of 0.1 μF or more, so there is no need for microfabrication. The chip 10 includes a P-type silicon substrate 11 and an element isolation region formed on this substrate. 12, an N+ type diffusion layer 13 formed on this substrate and serving as an electrode, and this N+
A first oxide film 14 formed on the shaped diffusion layer, a first polysilicon film 15 formed on this first oxide film and serving as an electrode, and a second oxidation film 15 formed on this first polysilicon film. Membrane 1
6 and a second polysilicon pattern 17 formed on the second oxide hood and serving as an electrode.
The electrode of polysilicon 115 is V,.
（電源）に接続され、Ｎ＋形拡散＠１３の電極と第２ポ
リシリコン膜１７の電極とはＶ３．（グランドレベル）
に接続されている。このような構造により、Ｖ、ｓｃと
ｖ９．に大きな容量を作ることができる。ここで、たと
えば第１酸化Ｍ！Ａ１４の膜厚を１００Ａ、その面積を
４ ｎ＋＋ａｘ Ｂ ｍｍとすれば、約０．１５μＦの
容量のデカップリングコンデンサを作ることができる。(power supply), and the electrode of the N+ type diffusion@13 and the electrode of the second polysilicon film 17 are connected to V3. (ground level)
It is connected to the. With this structure, V, sc and v9. can create a large capacity. Here, for example, the first oxidation M! If the film thickness of A14 is 100 A and its area is 4 n++ax B mm, a decoupling capacitor with a capacitance of about 0.15 μF can be made.
以上のようにして得られたＰＣＣ３０は、外形上は従来
のＰＣＣと全く同様であり、かつ外付けのデカツブリン
グコデンサを必要としないので、表面実装型半導体装置
の実装方法が非常に簡単になるばかりでなく、実装密度
もより向上し信頼性の向上も期待できる。The PCC 30 obtained as described above has the same external shape as a conventional PCC and does not require an external decoupling capacitor, making it extremely easy to mount a surface-mounted semiconductor device. Not only will it be possible to improve the packaging density, but it can also be expected to improve reliability.
なお、上記実施例においてフレーム５の裏面に取付ける
チップ１０は、半導体チップに限定されるものではなく
、市販されているコンデンサであってもよい。In addition, in the above embodiment, the chip 10 attached to the back surface of the frame 5 is not limited to a semiconductor chip, but may be a commercially available capacitor.
また、上記実施例では、表面実装型デバイスとしてＰＣ
Ｃを用いる場合について示したが、この発明はＰＣＣを
用い゛る場合に限定されるものではなく、表面実装型デ
バイスであれば、ＳＯＪ、ＳＯＰなどのようなパッケー
ジにも適用できることは言うまでもない。In addition, in the above embodiment, a PC is used as a surface-mounted device.
Although the case where C is used has been described, it goes without saying that the present invention is not limited to the case where PCC is used, and can also be applied to packages such as SOJ and SOP as long as it is a surface mount type device.
［弁明の効果］
以上のようにこの発明によれば、表面実装型半導体装置
において、該表面実装型半導体装置に外付けする電源電
圧平滑用コンデンサを該表面実装型半導体装置のパッケ
ージ内に組み込むようにしたので、実装方法が非常に簡
単になるとともに、実装密度および信頼性を向上させる
ことができる半導体装置を得ることができる。[Effect of explanation] As described above, according to the present invention, in a surface-mounted semiconductor device, a power supply voltage smoothing capacitor externally attached to the surface-mounted semiconductor device is incorporated into the package of the surface-mounted semiconductor device. Therefore, it is possible to obtain a semiconductor device whose mounting method is extremely simple and whose mounting density and reliability can be improved.
第１図は、この発明の実施例であるＦＣＣの構造を示す
断面図である。
第２図は、第１図のチップ〈デカップリングコンデンサ
）の構造の一例を示す断面図である。
第３図（ａ＞、（ｂ）は、高！度実装のために製品化さ
れたメモリモジュールの例を示す外形図である。
第４図は、従来のＰＣＣの構造を示す断面図である。
図において、１は基板、２はリード、３．３０はＰＣＣ
１４はデカップリングコンデンサ、５はフレーム、６．
１０はチップ、７はＡｕワイヤ、８はモールド樹脂、１
１はＰ形シリコン！！仮、１２は素子量分Ｎｉ領域、１
３はＮ＋形形成散層１４は第１１化膜、１５は第１ポリ
シリコン膜、１６は第２酸イし膜、１７は第２ポリシリ
コン膜である。
なお、各図中同一符号は同一または相当部分を示す。
第１図
第２図FIG. 1 is a sectional view showing the structure of an FCC according to an embodiment of the present invention. FIG. 2 is a sectional view showing an example of the structure of the chip (decoupling capacitor) shown in FIG. 1. 3(a) and 3(b) are outline drawings showing an example of a memory module commercialized for high-level packaging. FIG. 4 is a sectional view showing the structure of a conventional PCC. In the figure, 1 is the board, 2 is the lead, and 3.30 is the PCC.
14 is a decoupling capacitor, 5 is a frame, 6.
10 is a chip, 7 is an Au wire, 8 is a mold resin, 1
1 is P-type silicon! ! Temporarily, 12 is a Ni region corresponding to the element amount, 1
Reference numeral 3 designates the N+ type formation diffusion layer 14 as an eleventh dioxide film, 15 as a first polysilicon film, 16 as a second oxide film, and 17 as a second polysilicon film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 2
Claims (3)
導体装置に外付けする電源電圧平滑用コンデンサを該表
面実装型半導体装置のパッケージ内に組み込んだことを
特徴とする半導体装置。(1) A surface-mounted semiconductor device, characterized in that a power supply voltage smoothing capacitor externally attached to the surface-mounted semiconductor device is incorporated into a package of the surface-mounted semiconductor device.
ンドし、前記コンデンサを前記フレームの他方面にダイ
ボンドする特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the semiconductor memory chip is die-bonded to one side of the frame, and the capacitor is die-bonded to the other side of the frame.
らなる電極と、拡散層とを含む特許請求の範囲第２項記
載の半導体装置。(3) The semiconductor device according to claim 2, wherein the capacitor includes an oxide film, an electrode made of a polysilicon film, and a diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60219395A JPS6278864A (en) | 1985-09-30 | 1985-09-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60219395A JPS6278864A (en) | 1985-09-30 | 1985-09-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6278864A true JPS6278864A (en) | 1987-04-11 |
Family
ID=16734740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60219395A Pending JPS6278864A (en) | 1985-09-30 | 1985-09-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6278864A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001094040A (en) * | 1999-09-22 | 2001-04-06 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
-
1985
- 1985-09-30 JP JP60219395A patent/JPS6278864A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001094040A (en) * | 1999-09-22 | 2001-04-06 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1331221C (en) | Chip ball grid array packaging structure | |
| JP2708191B2 (en) | Semiconductor device | |
| JP3768744B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2891692B1 (en) | Semiconductor device | |
| JP2000133767A (en) | Laminated semiconductor package and its manufacture | |
| US6703691B2 (en) | Quad flat non-leaded semiconductor package and method of fabricating the same | |
| JPS6278864A (en) | Semiconductor device | |
| JPH04144269A (en) | Hybrid integrated circuit device | |
| KR100635386B1 (en) | Semiconductor chip package with high speed signal processing | |
| CN218160365U (en) | Packaging structure | |
| CN215731686U (en) | Novel SOD-323T packaging structure | |
| JPH11111750A (en) | Semiconductor device | |
| CN212848403U (en) | SOT packaging structure based on SIP | |
| JPH01286342A (en) | Surface mounting ultrathin type semiconductor device | |
| KR950005457B1 (en) | Float capacitor semiconductor device | |
| JPS6329960A (en) | Lead frame for resin seal type semiconductor device | |
| JPH03278561A (en) | Hybrid integrated circuit device | |
| JP2001135668A (en) | Semiconductor device and its manufacturing method | |
| KR950014116B1 (en) | Semiconductor device and the manufacture method | |
| JPH11195743A (en) | Semiconductor device and manufacture thereof | |
| JPS6095958A (en) | Semiconductor device | |
| JP2004228259A (en) | Semiconductor device and electronic equipment using the same | |
| JPS62210661A (en) | Semiconductor device | |
| CN112103280A (en) | Chip packaging structure, chip packaging method and digital isolator | |
| JP3514516B2 (en) | Method for manufacturing semiconductor device |