JPS6278818A - Method of judgement for circuit patterning - Google Patents

Abstract

PURPOSE:To easily give a decision on a circuit patterning by a method wherein a resist pattern crossing a stepping is formed on the prescribed region of a wafer as a circuit patterning judgement region. CONSTITUTION:A patterning judgement region 1 is provided on a wafer, and among the steppings to be formed in each manufacturing process, at least a stepping whereon resist patterns 9 and 10 are susceptible to defects is formed on said patterning judgement region 1. The resist patterns 9 and 10 are formed in such a manner that they are crossing the above-mentioned stepping. When the region 1 is inspected, if the pattern gets out of shape, it is defective and a photolithographic process and the like is performed again.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for determining circuit patterning consisting of fine patterns formed on a wafer.

(Prior art) When manufacturing semiconductor devices, a photorin process is required.
As disclosed in Japanese Patent Publication No. 34 or Japanese Patent Publication No. 59-134831, a turn is formed by Lennost, and the base is processed using this pattern as a mask. So(F
Therefore, if the resist/turn has defects such as breaks or poor resolution, the processing of the base/turn will also be defective. In order to discover such defects, inspections such as Lennost and Turn are carried out, and if defects are discovered,
Countermeasures will be taken, such as redoing the photorin process and redoing the missing parts.

As shown in Figure 3, such turn defects caused by errors in exposure setting are caused by aggregations of semiconductor chips (usually several hundred to several dozen pieces) that should be divided into each semiconductor device. This circuit] and turning judgment are important because it affects the turning of all chinogs on Taru Ueno 31.

Therefore, the circuit patterning was determined by scanning the entire surface of the semiconductor chinograph using a microscope or the like.

(Problem to be solved by the invention) However, in this method of determining circuit patterning, the entire chip cannot fit within the field of view of the microscope, and defects and setbacks cannot be detected by moving and scanning the semiconductor chip. It takes a lot of effort to determine the patterning.

Even if the entire chip is within the field of view, turn defects usually occur, and even when they do occur, they occur at irregular positions for each circuit pattern, but it is difficult to detect them. It takes a lot of effort to discover it.

Because such labor is required, it has been difficult to judge circuit patterning in a short time. Considering that this is likely to occur, a circuit/zoo turning judgment area is provided on the top of the wall, and a step/turn is formed here.
A resist pattern 7 is formed across this step/gutter to serve as a monitor, and the resist pattern here is inspected.

(Function) In the present invention, a resist pattern is formed in a predetermined area on a wafer as a circuit/setting determination area on a step and crosses this, so defects are less likely to occur here. Determination of patterning becomes easy.

(Embodiment) An embodiment of the present invention will be described below using a memory semiconductor device as an example. FIG. 1 is an enlarged view of a case where a memory cell for patterning judgment is formed in the patterning judgment area on semiconductor chip 7'J, ) of the wafer shown in FIG. 3, and patterning judgment of a wiring pattern is performed. and (a
) is a plan view, and (b) is its A, -A2 sectional view.

A gap in the memory cell is formed in the turning determination area. This includes steps where turn defects are most likely to occur. As shown in (b), a gate oxide layer 3 and a field oxide layer 4 are formed on a wafer 2, a polyrecon layer 5 on which a gate oxide layer 2 is formed is formed, and a polyrecon layer 5 is formed on top of this. PSG layer 6 as interlayer insulation layer
is formed, an At layer 7 serving as a wiring layer is formed thereon, and a renocyst layer 8 is formed thereon.

In the process of forming the wiring layer of the semiconductor device, the patterning determination area is also exposed to pattern the renost layer 8.

(9) The pattern of the resist layer 8 in the turning determination area is preferably formed in a striped shape that traverses a plurality of steps and has different pattern widths and pitches, as shown in (a). In particular, this resist pattern is designed to include the most difficult part to form a turn among the wiring and turns of the memory semiconductor device. For example, if wiring with a line width of 2 .mu.m at intervals of 2 .mu.m is the finest pattern for this semiconductor device, this pattern 9 is formed above the patterning determination area. Further, it is better to form several mother turns 10 which are finer than the pattern 9 for patterning determination because the limits of fine turns can be determined.

Since the fine zigzag turns are formed so as to cross over the step, pattern defects are more likely to occur on the step, making it easier to judge.

When inspecting this patterning judgment area, as shown in Fig. 1 (b
If the pattern is distorted as shown in ), it is defective and it is necessary to take measures such as repairing the IJ process.

Further, as shown in the plan view of another embodiment of FIG. 2, the resist pattern provided in the turning determination area may be formed so that each line becomes narrower at a predetermined pitch. Such a pattern is preferable for determining the status of F) IJ and S.

By researching in advance several conditions exposed by changing the focus during exposure and several conditions exposed by changing the exposure time, it is possible to
It becomes possible to determine whether the currently inspected semiconductor device has a focus setting error, an exposure time setting error, and the degree of deviation.

A specific example of a pattern for this determination is as follows.

For example, in the case of a reduction projection exposure apparatus with a minimum resolution of 0.6 μm, one pattern with a line width of 2 lines is set so that the distance between the patterns (line width) is the minimum of 0183 m.
The space is formed to become narrower in steps of 0.5 μm. This step is not limited to 0.5 .mu.m depending on the type of resist at that time and the exposure apparatus, but may be any preferable value up to 1 .mu.rrL.

Incidentally, if there is no space to form the patterning determination area on the semiconductor chip 32 shown in FIG. 3, it may be provided within the skip pattern chip 33 on the wafer.

Furthermore, as a modification of the second embodiment, instead of changing the area, the line width of the resist may be changed. Here, the choice of whether to change the line width of one pass or the line width of resist turns is determined depending on whether the resist used is a pollenost or a negative resist. Also, Rennost of semiconductor equipment! Turn is 49
It is a good idea to consider whether there is enough space with other resists that will fit.

(Effects of the Invention) As explained above, in the present invention, the resist pattern in the process is formed in a turning determination area with a preset step, so that the following effects can be obtained.

(2) Since patterning can be determined by inspecting only the patterning determination area, the time required for inspection can be shortened.

■ By comparing the condition of the patterning judgment area investigated in advance with the patterning judgment area of the inspection target, it is possible to judge the focus or exposure time, and to take more appropriate measures. Become.

[Brief explanation of drawings]

FIG. 3 is a plan view of another resist pattern in the wafer. L... Patterning determination area, 2... Sea urchin..., 3
... Dirt oxide layer, 4... Field oxide layer, 5.
...Polysilicon layer, 6...PSG layer, 7...At
Layer 8...Resist layer, 9-11...Turn to resist layer. Daikihiiku 1jII I did 21 in Kotoi ^・A1~
A2 disconnection: N] Figure 1

Claims (6)

[Claims] (1) (a) Provide a patterning determination area on the wafer,
Here, a step of forming at least a step where resist pattern defects are likely to occur among the steps formed in each manufacturing process, (b) a step of forming a resist pattern across the step, and (c) the judgment area. A circuit patterning determination method comprising the step of inspecting a resist pattern above. (2) The circuit patterning determination method according to claim 1, wherein the resist pattern is formed so as to cross over the step in plurality. (3) The circuit patterning determination method according to claim 2, wherein a plurality of resist patterns that cross the step are formed to have different thicknesses depending on the location where the resist pattern crosses the step. (4) The circuit patterning determination method according to claim 2, wherein a plurality of resist patterns that cross the step are formed with different spaces depending on the locations where the resist patterns cross the step. (5) The circuit patterning determination method according to claim 3, wherein the resist pattern having different thicknesses depending on the location across the step is formed in regular steps so as to have different thicknesses. (6) The circuit patterning determination method according to claim 4, wherein the resist pattern having different spaces depending on the location across the step is formed with regular steps so that the spaces are different.