JPS6278780U - - Google Patents
Info
- Publication number
- JPS6278780U JPS6278780U JP17074285U JP17074285U JPS6278780U JP S6278780 U JPS6278780 U JP S6278780U JP 17074285 U JP17074285 U JP 17074285U JP 17074285 U JP17074285 U JP 17074285U JP S6278780 U JPS6278780 U JP S6278780U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- mounting type
- spacers
- stage mounting
- circuit boards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 125000006850 spacer group Chemical group 0.000 claims description 7
Description
第１図は上部回路基板のリードピンの縦列にス
ペーサーを挾ませた状態の低面図、第２図は多段
実装式回路基板の断面図、第３図、第４図、第５
図は、スペーサーを他の方法によつてリードピン
に挾んだ状態の上部回路基板の低面図、第６図は
他の実施例のスペーサーを設けた上部回路基板の
低面図、第７図は他の実施例のスペーサーを設け
た多段実装式回路基板の断面図、第８図は従来の
多段実装式回路基板の一部省略断面図である。
尚、図中、Ａ……多段実装式回路基板本体、Ｍ
……回路基板、３……スペーサー、７……リード
ピン、７ａ……縦列、７ｂ……横列、を夫々示す
。
Figure 1 is a bottom view of the upper circuit board with spacers sandwiched between the vertical rows of lead pins, Figure 2 is a cross-sectional view of the multi-stage circuit board, Figures 3, 4, and 5.
The figures are a bottom view of the upper circuit board with the spacer sandwiched between the lead pins by another method, FIG. 6 is a bottom view of the upper circuit board with spacers of another embodiment, and FIG. 8 is a cross-sectional view of a multi-stage mounting type circuit board provided with spacers according to another embodiment, and FIG. 8 is a partially omitted cross-sectional view of a conventional multi-stage mounting type circuit board. In addition, in the figure, A...Multi-stage mounting type circuit board main body, M
. . . circuit board, 3 . . . spacer, 7 . . . lead pin, 7 a .
Claims (1)
式回路基板本体において、前記対応する回路基板
におけるリードピンの縦横列の間隙にスペーサー
を挾持させて形成したことを特徴とする多段実装
式回路基板。 1. A multi-stage mounting type circuit board, characterized in that a multi-stage mounting type circuit board main body is formed in which circuit boards are formed in correspondence with each other, and spacers are formed by sandwiching spacers between vertical and horizontal rows of lead pins on the corresponding circuit boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17074285U JPS6278780U (en) | 1985-11-05 | 1985-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17074285U JPS6278780U (en) | 1985-11-05 | 1985-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6278780U true JPS6278780U (en) | 1987-05-20 |
Family
ID=31105740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17074285U Pending JPS6278780U (en) | 1985-11-05 | 1985-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6278780U (en) |
-
1985
- 1985-11-05 JP JP17074285U patent/JPS6278780U/ja active Pending
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