JPS6278090U - - Google Patents

Info

Publication number
JPS6278090U
JPS6278090U JP16838085U JP16838085U JPS6278090U JP S6278090 U JPS6278090 U JP S6278090U JP 16838085 U JP16838085 U JP 16838085U JP 16838085 U JP16838085 U JP 16838085U JP S6278090 U JPS6278090 U JP S6278090U
Authority
JP
Japan
Prior art keywords
output
inverter
voltage
covers
variation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16838085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16838085U priority Critical patent/JPS6278090U/ja
Publication of JPS6278090U publication Critical patent/JPS6278090U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例のインバータを示すブ
ロツク図、第2図は従来例のインバータのブロツ
ク図である。 1……インバータ、2……検出回路、3……調
整ボリユーム、4……加算器、5……制御回路、
6……直流電源、7……10Vインバータ、8…
…490Vインバータ、9,10……加算器、1
1,12……制御回路。
FIG. 1 is a block diagram showing an inverter according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional inverter. 1... Inverter, 2... Detection circuit, 3... Adjustment volume, 4... Adder, 5... Control circuit,
6...DC power supply, 7...10V inverter, 8...
...490V inverter, 9,10...adder, 1
1, 12...control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 商用周波数の入力を高周波の出力に変換するイ
ンバータ手段と、高周波出力を低減して負の直流
電圧とする検知手段と正の標準直流電圧供給手段
と、前記検出手段の出力と、前記標準直流電圧供
給手段の出力を加算する加算手段と、該加算手段
出力をOVにするように前記インバータ手段を調
整する制御手段とから成るインバータの出力安定
装置において、前記インバータ手段を少なくとも
2系統設け、1系統は定格出力電圧より変動分を
カバーする電圧だけ低い出力のインバータ手段と
、他はその変動分をカバーする電圧の出力電圧の
インバータ手段とし、それに伴い少なくとも2系
統の加算手段と制御手段を備えたことを特徴とす
るインバータの出力安定装置。
an inverter means for converting a commercial frequency input into a high frequency output, a detection means for reducing the high frequency output to a negative DC voltage, a positive standard DC voltage supply means, an output of the detection means, and the standard DC voltage. In an inverter output stabilizing device comprising an adding means for adding the outputs of the supply means, and a control means for adjusting the inverter means so that the output of the adding means becomes OV, at least two systems of the inverter means are provided, and one system is provided. is an inverter means with an output voltage lower than the rated output voltage by a voltage that covers the variation, and the other is an inverter means with an output voltage that covers the variation, and is equipped with at least two systems of addition means and control means. An inverter output stabilizer characterized by:
JP16838085U 1985-10-30 1985-10-30 Pending JPS6278090U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16838085U JPS6278090U (en) 1985-10-30 1985-10-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16838085U JPS6278090U (en) 1985-10-30 1985-10-30

Publications (1)

Publication Number Publication Date
JPS6278090U true JPS6278090U (en) 1987-05-19

Family

ID=31101207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16838085U Pending JPS6278090U (en) 1985-10-30 1985-10-30

Country Status (1)

Country Link
JP (1) JPS6278090U (en)

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