JPS627776B2 - - Google Patents
Info
- Publication number
- JPS627776B2 JPS627776B2 JP56021875A JP2187581A JPS627776B2 JP S627776 B2 JPS627776 B2 JP S627776B2 JP 56021875 A JP56021875 A JP 56021875A JP 2187581 A JP2187581 A JP 2187581A JP S627776 B2 JPS627776 B2 JP S627776B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- overvoltage
- circuit
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 30
- 238000010586 diagram Methods 0.000 description 6
- 238000009499 grossing Methods 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Supply And Distribution Of Alternating Current (AREA)
- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
Description
【発明の詳細な説明】
本発明はスイツチングレギユレータ方式安定化
電源装置に関するもので、特に並列運転時に過電
圧異常機を容易に判別しうる機能を備えた電源装
置を提供するものである。以下図面を用いて説明
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching regulator type stabilized power supply device, and particularly to a power supply device having a function of easily identifying an overvoltage abnormality during parallel operation. This will be explained below using the drawings.
第1図はこの種の従来例を示すブロツク図で図
においてA1,A2は単位スイツチングレギユレ
ータ(以下電源ユニツト)B1,B2は夫々電源
ユニツトA1,A2に内蔵された過電圧検出回路
で、夫々電源ユニツトA1,A2の過電圧を検出
して対応する電源ユニツトA1,A2に過電圧検
出(電源停止)信号S1,S2を送出して対応す
る電源ユニツトの運転停止を計ると同時に該信号
S1,S2を共通線S3により互いに入り込ませ
て他方の電源ユニツトA1又はA2の運転停止を
行う。Rは電源ユニツトA1,A2の共通負荷で
ある。なお電源ユニツトA1,A2は図示しない
電圧制御回路を有し夫々安定化出力Eoを負荷に
給電する如く構成されている。 FIG. 1 is a block diagram showing a conventional example of this type. In the figure, A1 and A2 are unit switching regulators (hereinafter referred to as power supply units). B1 and B2 are overvoltage detection circuits built into the power supply units A1 and A2, respectively. Detects overvoltage in power supply units A1 and A2, respectively, and sends overvoltage detection (power supply stop) signals S1 and S2 to the corresponding power supply units A1 and A2 to stop operation of the corresponding power supply units, and simultaneously outputs the signals S1 and S2. are inserted into each other via the common line S3, and the operation of the other power supply unit A1 or A2 is stopped. R is a common load of power supply units A1 and A2. The power supply units A1 and A2 each have a voltage control circuit (not shown) and are configured to supply a stabilized output Eo to the load.
そこで今電源ユニツトA1,A2の並列運転時
において過電圧検出回路B1が過電圧を検出する
と該検出回路B1は信号S1を出力して該電源ユ
ニツトA1を運転停止せしめ、又同時に共通線S
3を介して電源ユニツトA2も運転を停止せしめ
る。 Therefore, when the overvoltage detection circuit B1 detects an overvoltage when the power supply units A1 and A2 are operated in parallel, the detection circuit B1 outputs a signal S1 to stop the operation of the power supply unit A1, and at the same time, the common line S
3, the power supply unit A2 is also stopped.
即ち出力電圧Eoは2つの過電圧検出機能を有
することになり装置の信頼性の向上を計ることが
できる。又電源ユニツトの並列台数をN台に設定
すれば、N重の過電圧検出機能を備えることがで
き、又電源外部で共通線S3の信号を監視すれば
電源装置が過電圧により運転停止に到つたことが
判別できる。しかし乍らこの回路では過電圧発生
電源ユニツトがいづれであるか判別できない。 That is, since the output voltage Eo has two overvoltage detection functions, it is possible to improve the reliability of the device. In addition, by setting the number of power supply units in parallel to N, it is possible to have an N-fold overvoltage detection function, and by monitoring the signal on the common line S3 from outside the power supply, it is possible to detect when the power supply unit has stopped operating due to overvoltage. can be determined. However, this circuit cannot determine which power supply unit is generating the overvoltage.
即ち過電圧検出回路B1,B2は同一負荷ライ
ンに接続されているために共に出力電圧Eoの電
圧が印加される。従つて過電圧の原因が電源ユニ
ツトA1又はA2のいづれかにあるかに係わりな
く出力電圧Eoが過電圧の範囲まで上昇すると過
電圧検出回路B1,B2のうち検出電圧設定値の
低い方が過電圧を検出して信号を出力するためで
ある。従つて信号S1又は、S2を外部から監視
しても故障機の判別は不可能である。そこで従来
第1図中点線で示す如く夫々電源ユニツトA1又
はA2の出力回路にオア用ダイオードD1又はD
2を設けて夫々廻り込みを防止せしめることによ
つて故障機の判別を行つていた。しかし乍らこの
場合には夫々電源ユニツトの出力電流が大きい場
合には該ダイオードD1又はD2による電力損失
が大きく不経済であるばかりか熱処理実装面から
装置の大型化を招く等の欠点がある。 That is, since the overvoltage detection circuits B1 and B2 are connected to the same load line, the output voltage Eo is applied to both of them. Therefore, regardless of whether the overvoltage is caused by either power supply unit A1 or A2, when the output voltage Eo rises to the overvoltage range, the overvoltage detection circuit B1 or B2, whichever has the lower detection voltage setting value, will detect the overvoltage. This is to output a signal. Therefore, even if the signal S1 or S2 is monitored from the outside, it is impossible to identify a faulty machine. Therefore, conventionally, as shown by the dotted line in FIG.
2 was provided to prevent each machine from turning around, thereby identifying a faulty machine. However, in this case, when the output current of each power supply unit is large, the power loss due to the diode D1 or D2 is large and it is uneconomical, and there are disadvantages such as an increase in the size of the device due to heat treatment and mounting.
本発明は係る欠点を解消し安価、経済的にして
容易に故障機の判別の可能な電源装置を提供する
ものである。本発明は各々電源ユニツトに出力パ
ルス検出回路と過電圧信号及び出力パルス信号と
の論理をとる論理回路を設けると共に、過電圧信
号を共通線によつて接続するようにしたことを特
徴とするものである。以下図面を用いて説明す
る。第2図、第3図は本発明の一実施例回路図及
びその各部動作波形図で、従来例と同一符号は同
等部分を示す。第2図においてA1,A2はスイ
ツチングレギユレータ(電源ユニト)で、1は交
流電源、2は全波整流回路、3はスイツチングト
ランジスタ、4は出力トランス、5は整流平滑回
路で、トランジスタ3のオン・オフ動作によつて
出力トランス4に交互に電流を流し、矩形波状の
交流出力e0を送出させ整流平滑回路5はこれを
直流化して負荷Rに加える周知の動作を行う。C
は電圧制御回路で出力電圧と基準電圧を比較して
トランジスタ3の導通巾を制御して負荷電圧を安
定化させる周知の動作を行う。次にB1は過電圧
検出回路で第2図bに示すように出力電圧E0を
抵抗R1及び定電圧ダイオードDZで検出し、所
定電圧に達するとトランジスタQ1及びサイリス
タSCRを導通せしめて過電圧(又は運転停止)
信号S1を出力する。F1は出力パルス検出(判
別)回路で同図bに示す如く出力トランス4に出
力パルス検出巻線ndを設け、該検出パルスをコ
ンデンサC1を介して充放電せしめてこれを比較
器COPにおいて基準電源ESと比較するようにし
たもので、該充放電々圧は定常時(パルス有)は
基準電源ESより高電位に設定され、これにより
比較器COPはロウレベルの出力信号S5を出力
する。G1は論理回路で前記過電圧信号S1と出
力信号S5の論理をとり、故障機判別信号S4―
1を送出する。以上で本発明回路を構成する。 The present invention eliminates such drawbacks and provides a power supply device that is inexpensive, economical, and allows easy identification of a faulty device. The present invention is characterized in that each power supply unit is provided with an output pulse detection circuit, a logic circuit that takes logic between the overvoltage signal and the output pulse signal, and the overvoltage signals are connected through a common line. . This will be explained below using the drawings. FIGS. 2 and 3 are circuit diagrams of an embodiment of the present invention and operation waveform diagrams of each part thereof, in which the same reference numerals as in the conventional example indicate equivalent parts. In Fig. 2, A1 and A2 are switching regulators (power supply units), 1 is an AC power supply, 2 is a full-wave rectifier circuit, 3 is a switching transistor, 4 is an output transformer, and 5 is a rectifier and smoothing circuit. A current is alternately passed through the output transformer 4 through the on/off operation of step 3, and a rectangular waveform alternating current output e0 is sent out.The rectifying and smoothing circuit 5 converts this into direct current and applies it to the load R in a well-known operation. C
The voltage control circuit compares the output voltage with the reference voltage, controls the conduction width of the transistor 3, and performs the well-known operation of stabilizing the load voltage. Next, B1 is an overvoltage detection circuit that detects the output voltage E0 using a resistor R1 and a constant voltage diode DZ as shown in Figure 2b. When a predetermined voltage is reached, the transistor Q1 and thyristor SCR are turned on to detect the overvoltage (or stop operation). )
A signal S1 is output. F1 is an output pulse detection (discrimination) circuit, which is provided with an output pulse detection winding nd in the output transformer 4 as shown in FIG. The charging/discharging voltage is set to a higher potential than the reference power source ES during steady state (with pulses), so that the comparator COP outputs a low level output signal S5. G1 is a logic circuit that takes the logic between the overvoltage signal S1 and the output signal S5, and generates a failure machine determination signal S4-
Sends 1. The circuit of the present invention is configured as described above.
次に動作について第3図を参照して説明する。
先ず正常時においては電源ユニツトA1,A2は
安定出力E0を負荷に供給する。(第3図a)そ
こで時間t1において電源ユニツトA1に過電圧
原因が生じるとこれにより出力電圧は上昇する。
そして時間t2において該電圧が電源ユニツトA
2の電圧E0′以上に達すると該ユニツトA2は
出力を供給しない。従つて電源ユニツトA2はパ
ルス検出回路F2においては出力パルスが検出さ
れない。(第3図c)そこで該検出回路F2の比
較器においては基準電源が高電位になり、信号S
5は送出を停止する。(第3図d)(なお第3図d
においては信号S5は出力パルスの停止から時限
t2′をもつて信号停止となる例を示している。)
一方電源ユニツトA1の出力電圧は更に上昇して
時間t3において過電圧検出電圧値E0″に達す
ると過電圧検出回路B1(又はB2)のトランジ
スタQ1及びサイリスタSCRが導通(時間t
4)して過電圧検出信号S1を出力する。(第3
図f)該信号S1は論理回路G1及び線S3を介
して他の電源ユニツトの論理回路G2にも入力さ
れる。そこで電源ユニツトA1のパルス検出回路
F1においては第3図bに示す如く時間t4まで
パルス出力を検出するため、この間比較器COP
は第3図eの如く信号S5を送出して論理回路G
1に入力する。 Next, the operation will be explained with reference to FIG.
First, under normal conditions, power supply units A1 and A2 supply a stable output E0 to the load. (Fig. 3a) Then, when an overvoltage cause occurs in the power supply unit A1 at time t1, the output voltage increases.
Then, at time t2, the voltage changes to power supply unit A.
2, the unit A2 will not provide any output. Therefore, no output pulse is detected in the pulse detection circuit F2 of the power supply unit A2. (Fig. 3c) Therefore, in the comparator of the detection circuit F2, the reference power supply becomes high potential, and the signal S
5 stops sending. (Fig. 3 d) (Fig. 3 d)
In this example, the signal S5 stops after a time limit t2' from the stop of the output pulse. )
On the other hand, when the output voltage of power supply unit A1 further increases and reaches the overvoltage detection voltage value E0'' at time t3, transistor Q1 and thyristor SCR of overvoltage detection circuit B1 (or B2) become conductive (at time t
4) and outputs the overvoltage detection signal S1. (3rd
Figure f) The signal S1 is also input to the logic circuit G2 of the other power supply unit via the logic circuit G1 and the line S3. Therefore, in the pulse detection circuit F1 of the power supply unit A1, in order to detect the pulse output until time t4 as shown in FIG. 3b, the comparator COP
sends the signal S5 as shown in Fig. 3e to the logic circuit G.
Enter 1.
従つて論理回路G1においては時間t4〜t5
間において論理が成立して故障判別信号S4―1
を送出する(第3図g)。他方電源ユニツトA2
においては論理が成立せず信号S4―2は送出さ
れない。つまり判別信号S4―1又はS4―2を
監視すれば過電圧故障機が容易に判別できる。 Therefore, in the logic circuit G1, the time t4 to t5
A logic is established between the two and the failure determination signal S4-1
(Figure 3g). The other power supply unit A2
In this case, the logic is not established and the signal S4-2 is not sent out. In other words, by monitoring the discrimination signal S4-1 or S4-2, it is possible to easily identify an overvoltage failure machine.
以上実施例は電源ユニツト2台並列運転の例に
ついて説明したが、更に増設しても同様に実施で
きることは明白である。以上の説明から明らかな
ように、本発明によれば過電圧故障機の判別が容
易であるので正常な予備機との交換が速やかに実
施できる等装置の保持操作が円滑であると共に装
置の電力損失が少く、小型、経済的である等、実
用上の効果は大きい。 In the above embodiment, an example in which two power supply units are operated in parallel has been described, but it is clear that the same implementation can be carried out even if more power units are installed. As is clear from the above description, according to the present invention, it is easy to identify an overvoltage malfunctioning machine, so it can be quickly replaced with a normal spare machine, and the holding operation of the machine is smooth, as well as the power loss of the machine. It has great practical effects, such as being small in size, economical, etc.
第1図は従来回路図。第2図a,b及び第3図
は本発明の一実施例回路図及びその各部動作波形
図である。
図においてA1,A2はスイツチングレギユレ
ータ(電源ユニツト)、B1,B2は過電圧検出
回路、Rは負荷、D1,D2はダイオード、Cは
電圧制御回路、F1はパルス検出回路、1は交流
電源、、2は全波整流回路、3はスイツチングト
ランジスタ、4は出力トランス、5は整流平滑回
路、G1は論理回路、ndはパルス検出巻線、
COPは比較器、Esは基準電源、Dzは定電圧ダイ
オード、Q1はトランジスタ、SCRはサイリス
タ、S1,S2は過電圧検出(停止)信号、S3
は共通線、S4―1,S4―2は判別信号、S5
はパルス検出信号、Eoは出力(負荷)電圧であ
る。
Figure 1 is a conventional circuit diagram. FIGS. 2a and 2b and 3 are circuit diagrams of an embodiment of the present invention and operation waveform diagrams of each part thereof. In the figure, A1 and A2 are switching regulators (power supply units), B1 and B2 are overvoltage detection circuits, R is load, D1 and D2 are diodes, C is voltage control circuit, F1 is pulse detection circuit, and 1 is AC power supply. ,, 2 is a full-wave rectifier circuit, 3 is a switching transistor, 4 is an output transformer, 5 is a rectifier and smoothing circuit, G1 is a logic circuit, nd is a pulse detection winding,
COP is a comparator, Es is a reference power supply, Dz is a constant voltage diode, Q1 is a transistor, SCR is a thyristor, S1 and S2 are overvoltage detection (stop) signals, S3
is a common line, S4-1, S4-2 are discrimination signals, S5
is the pulse detection signal and Eo is the output (load) voltage.
Claims (1)
イツチングレギユレータを複数台並列運転するよ
うにした安定化電源装置において、前記各スイツ
チングレギユレータに出力パルス検出回路と前記
過電圧検出回路の検出信号及び前記出力パルス検
出回路のパルス信号との論理をとる論理回路を設
けると共に前記検出信号を共通線で接続し、過電
圧発生時に前記論理回路の出力信号により当該ス
イツチングレギユレータを判別せしめると共に各
スイツチングレギユレータを電源停止せしめるよ
うにしたことを特徴とするスイツチングレギユレ
ータ式安定化電源装置。1. In a stabilized power supply device in which a plurality of switching regulators equipped with a voltage control circuit and an overvoltage detection circuit are operated in parallel, each of the switching regulators has an output pulse detection circuit and a detection circuit for the overvoltage detection circuit. A logic circuit is provided to take logic between the signal and the pulse signal of the output pulse detection circuit, and the detection signal is connected through a common line, and when an overvoltage occurs, the switching regulator is identified by the output signal of the logic circuit. A switching regulator type stabilized power supply device characterized in that each switching regulator is configured to stop the power supply.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56021875A JPS57136230A (en) | 1981-02-17 | 1981-02-17 | Switching regulator type stabilized power supply device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56021875A JPS57136230A (en) | 1981-02-17 | 1981-02-17 | Switching regulator type stabilized power supply device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57136230A JPS57136230A (en) | 1982-08-23 |
JPS627776B2 true JPS627776B2 (en) | 1987-02-19 |
Family
ID=12067296
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56021875A Granted JPS57136230A (en) | 1981-02-17 | 1981-02-17 | Switching regulator type stabilized power supply device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57136230A (en) |
-
1981
- 1981-02-17 JP JP56021875A patent/JPS57136230A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57136230A (en) | 1982-08-23 |
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