JPS6277652A - Interruption processing system - Google Patents

Abstract

PURPOSE:To accept plural requests for interruption processing without altering an existent interruption processing program by supplying an address of interruption processing to an interruption processing part with the signal from an interruption control scheduler. CONSTITUTION:When a request for interruption is generated, control is passed to the interruption control scheduler KS through an actual interruption vector part VT 1 to check whether the interruption processing part FP is already used or not. When so, it is put in a queue and the processing is finished. When not, on the other hand, a flag is set to an in-use state and an interruption vector in a dummy interruption vector part VT 2 is started and the interruption processing part FP performs the interruption processing. When this interruption processing is finished, the control returns to a next instruction in the vector part VT 2, the in-use flag is turned off, and it is checked whether or not there is a request in the queue; when there is the request, the in-use flag is set again to repeat said procedure and when not,the processing is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt processing method in a computer system.

(Prior Art) Conventionally, 81 computer systems have an interrupt control system called I! There are 10 pins. FIG. 5 is a conceptual diagram of the structure of normal simple interrupt processing. The interrupt request is given to the interrupt processing section FP via the interrupt vector section VT. In the interrupt vector section VT, the address of the corresponding interrupt processing is set, and the address of the interrupt processing section FP is specified.

(Problems to be Solved by the Invention) In the interrupt processing system configured as described above, if the next request is made during interrupt processing, it is not known whether the operation will be executed reliably. In order to ensure that the operation is executed reliably, it is necessary to change the operating conditions of the interrupt processing so that it can accept multiple interrupt requests, and the existing interrupt processing 811 (hardware or The problem is that the software must be modified.

The present invention was made in view of these problems, and
The purpose is to provide an interrupt processing method that can accept multiple interrupt processing requests without modifying an existing interrupt processing program that is designed to process only one request at a time. It's about doing.

Means for Solving the Problems The present invention solves the problems described above. The method includes a real interrupt vector block that receives an interrupt request, an interrupt management scheduler that receives a signal from the real interrupt vector block, and an interrupt processing section that receives a signal from the interrupt management schedule caller. and a pseudo-interrupt vector section that gives an address for interrupt processing, and when an interrupt request occurs, the interrupt management scheduler checks whether the interrupt processing section is already in use, and if it is in use. If the interrupt processing unit is not in use, the interrupt vector in the pseudo interrupt vector unit is activated.

This system is characterized in that the interrupt processing is executed in the interrupt 98 management department.

(Embodiment) FIG. 1 is a conceptual diagram of the configuration of an embodiment of the present invention. In the present invention, the actual interrupt hexes 1 to /L that receive the interrupt request,
an interrupt management scheduler KS which receives a signal from this real interrupt vector part VT1, and an interrupt processing part FP which receives a signal from this interrupt management scheduler KS.
Pseudo interrupt vector section VT that gives the address of interrupt processing to
2 was established. Here, the address of the interrupt management scheduler KS is set in the real interrupt vector part VT1, and the address of the interrupt processing part FP is set in the pseudo interrupt vector part VT2. The interrupt processing unit FP has a structure that cannot process multiple requests at the same time, and the interrupt management schedule caller KS is designed to be able to accept multiple requests for interrupt processing.

FIG. 2 is a flowchart showing an example of the operation of the interrupt management scheduler KS in FIG. 1.

First, when an interrupt request occurs, the actual interrupt vector section VT1
#llI control is passed to the interrupt management scheduler KS via. This interrupt management scheduler KS includes an interrupt processing unit FP.
Checks whether it is already in use, and if so, queues it in the queue and exits. If the interrupt processing unit FP is not in use, the flag is set to in use (on), the interrupt vector in the pseudo interrupt control unit VT2 is activated, and the interrupt processing unit FP handles the interrupt. Execute processing. In FIG. 2, the portion surrounded by broken lines is created by flJ with no interruptions.

When this interrupt processing is finished, the process returns to the next instruction in the interrupt vector section VT2, so turn off the in-use flag, and then check whether there is anything waiting for processing.
If there is, turn on the in-use flag again and repeat the above procedure. If there is none, the process ends.

By performing the operations described above, the interrupt management scheduler KS can operate without modifying the interrupt processing unit FP.
It is possible to accept multiple requests for interrupt processing. Also, ze [
By creating a matrix, it is possible to prioritize usage and control the execution order, such as on a first-come, first-served basis.

FIG. 3 shows a configuration R Kuraguchi showing an embodiment of the present invention. In this embodiment, two interrupt management schedulers KS1 and KS2 are provided via a pseudo-interrupt vector section VT3 to improve the response time of the interrupt processing section FP. Here, the interrupt processing unit FP can process multiple function requests, some of which can be processed within a certain period of time, and some which cannot be completed until an event occurs, such as synchronous type requests. input) are mixed. In such interrupt processing, normally some of the former processing requests can be processed during the latter processing, but they are still held and become a factor that worsens the response time. Ta.

This embodiment is an improvement on such a problem, and a flowchart of the operation of the interrupt management scheduler KS2 is shown in the v84 diagram.

All interrupt requests once enter the interrupt vector section VTI,
From here, control passes to the interrupt management scheduler KS2. This interrupt management scheduler KS2 (J) uses methods such as lookahead to check whether the processing can be completed for the functions that are a factor in reducing the response time.If the processing is not possible at this point, If an event occurs and the state is ready for processing, the next interrupt management scheduler KSI is activated via the pseudo interrupt vector unit VT3.
-6ru. If the interrupt processing unit FP is not in use, it is activated immediately by the interrupt management scheduler KSI.When this interrupt processing is completed, the process returns to the interrupt management scheduler KS1, and then the interrupt processing unit FP is activated. Return to the interrupt management scheduler KS2.In the interrupt management scheduler KS2, if there are other items waiting to be processed, they are activated using the same procedure.Furthermore, for functions that are not related to events, the pseudo interrupt vector unit VT3 is activated immediately. Control is passed to the interrupt management scheduler KS1 via the interrupt management scheduler KS1.The subsequent operations are the same as those in the embodiment of FIG.

As described above, the interrupt management scheduler 1-RA KS2 preferentially processes only those that can be processed, and can eliminate unlimited deterioration of response time.

In the above description, the interrupt scheduler KS can be realized by either software or hardware. Furthermore, the scheduling method used by the management scheduler is the most appropriate one depending on the intended system configuration for interrupt processing.

(Effects of the Invention!!) As explained above, according to the present invention, by adding an interrupt management scheduler, multiple interrupts can be handled without modifying the existing interrupt processing section. Processing requests can be accepted.Furthermore, when interrupt processing supports multiple functions, processing performance can be improved by scheduling in units of functions.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of the configuration of one embodiment of the present invention, FIG. 2 is a flowchart showing an example of the operation of the interrupt management scheduler in the J-1 area, and FIG. 3 is a conceptual diagram of the configuration of another embodiment of the present invention. Figure 4 is a flowchart showing an example of the operation of the interrupt management scheduler KS2 similar to that shown in Figure 3, and Figure 5 is a conceptual diagram of the configuration of conventional interrupt processing. Interrupt vector part VT2... Pseudo interrupt vector part KS... Interrupt management scheduler FP... Interrupt processing part FP; A VT2 i Pseudo-interrupt vector part S; Interrupt scheduler FP; 'A door 4.

Claims (1)

[Claims] In an interrupt processing method in a computer system having an interrupt processing unit configured to process only one interrupt request at a time, an actual interrupt vector unit that receives an interrupt request;
An interrupt management scheduler that receives a signal from this real interrupt vector section and a pseudo interrupt vector section that receives a signal from this interrupt management scheduler and gives an interrupt processing address to the interrupt processing section are provided. When an interrupt request occurs, the interrupt management scheduler checks whether the interrupt processing section is already in use, and if it is in use, it queues it in the queue, and if the interrupt processing section is not in use, it queues it in the queue. An interrupt processing method characterized in that an interrupt vector in a pseudo interrupt vector section is activated, and the interrupt processing is executed in an interrupt processing section.