JPS6276972A - Horizontal deflection circuit - Google Patents

Horizontal deflection circuit

Info

Publication number
JPS6276972A
JPS6276972A JP21675785A JP21675785A JPS6276972A JP S6276972 A JPS6276972 A JP S6276972A JP 21675785 A JP21675785 A JP 21675785A JP 21675785 A JP21675785 A JP 21675785A JP S6276972 A JPS6276972 A JP S6276972A
Authority
JP
Japan
Prior art keywords
correction
capacitor
coil
modulation
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21675785A
Other languages
Japanese (ja)
Other versions
JPH0638633B2 (en
Inventor
Kiyoshi Ishihata
石幡 潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP21675785A priority Critical patent/JPH0638633B2/en
Publication of JPS6276972A publication Critical patent/JPS6276972A/en
Publication of JPH0638633B2 publication Critical patent/JPH0638633B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To sufficiently correct intermediate pin distortion while securing the dynamic range of right-and-left pin distortion correction by using a transformer structure to a modulation coil and supplying a deflection current to a correction coil which is a secondary coil. CONSTITUTION:The secondary winding 20b of the transformer 20 is connected to the first S-shaped correction capacitor 11 in series. The other end of said winding is connected to a connection point between the second S-shaped correction capacitor 13 and the primary winding 20a of the transformer 20. When a deflection current (iy) is large, a modulation current i' can be made in small value even if the S-shaped voltage of the capacitor 13 by said current (iy) goes to a large value. Therefore, even when the capacity of the capacitor 13 is made smaller for the intermediate pin distortion correction, the dynamic range of the right-and-left pin distortion correction can be made wide. As a result, a sufficiently practical right-and-left pin correction distortion correction circuit can be formed.

Description

【発明の詳細な説明】 発明のilT綱な説明 〔産業上の利用分野〕 この発明はテレビ受像機の水平偏向回路に関し、特に左
右ピン歪補正を良好に行えるものに関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Description of the Invention [Field of Industrial Application] The present invention relates to a horizontal deflection circuit for a television receiver, and particularly to one that can effectively correct left and right pin distortion.

〔発明の概要〕[Summary of the invention]

この発明は、左右ピン歪?1IiIFを水平偏向コイル
に直列に変調用コイルを設け、この変調用コイルに垂直
周期の補止電圧を加えるごとによってな1−ようにする
ことによってピン歪補1ピの変凋による西圧の変動がな
く、良好な特性をネオ水平偏向回路において、陰極線管
の大型化、画面のフラット化に伴って特に画面の水平方
向の中間部に残留する左右ピン歪を良好に補IEできる
ようにしたものである。
Is this invention a left and right pin distortion? 1IiIF is provided with a modulating coil in series with the horizontal deflection coil, and by applying a vertical period compensation voltage to this modulating coil, the pin distortion is compensated for. The Neo horizontal deflection circuit is designed to effectively compensate for the left and right pin distortion that remains in the horizontal middle of the screen, especially as cathode ray tubes become larger and screens become flatter. It is.

〔従来の技術〕[Conventional technology]

従来、水平偏向回路の左11ビン走袖止回路としてri
J飽和リアクタを水平偏向コイルに直列にト妾続し、こ
れに垂直周期のパラボラ波を供給するものが良く知られ
°ζいる。ところが、このピン歪補正の方法は偏向回路
のインダクタンス値を変えるものであるので、垂直周期
のインダクタンス値の変化に応じて高圧に垂直周期の変
動が生じるという欠点があった。
Conventionally, ri was used as the left 11-bin running arm stop circuit of the horizontal deflection circuit.
It is well known that a J saturation reactor is connected in series to a horizontal deflection coil, and a vertically periodic parabolic wave is supplied to the reactor. However, since this pin distortion correction method involves changing the inductance value of the deflection circuit, it has the drawback that vertical period fluctuations occur in the high voltage in response to changes in the vertical period inductance value.

これに対し、このようなピン歪補正の変調による晶化の
変すリjがない左右ビン歪補正回路が提案さね、た(特
公昭57−39102号公報参照)。
In contrast, a left and right bin distortion correction circuit has been proposed in which there is no change in crystallization due to such modulation of pin distortion correction (see Japanese Patent Publication No. 57-39102).

第3図はこの種の左右ピン歪補正回路の一例をボし、(
1)は水平出力トランジスタである。
Figure 3 shows an example of this type of left and right pin distortion correction circuit.
1) is a horizontal output transistor.

くの水平出力トランジスタ(1)のベースには水平ドラ
イブ回路よりの水平周期のドライブ信号が供給され、コ
レクタには、直流電源(2)よりの電圧がフライバック
トランス(3)の1次巻線を介して供給されている。そ
して、エミッタは接地される。
A drive signal with a horizontal period from the horizontal drive circuit is supplied to the base of the horizontal output transistor (1), and a voltage from the DC power supply (2) is supplied to the collector of the primary winding of the flyback transformer (3). Supplied via. The emitter is then grounded.

フライバックトランス(3)の2次巻線側には面圧整流
回路(4)が接続され、端子(5)に高圧出力電圧E 
HVが取り出される。
A surface pressure rectifier circuit (4) is connected to the secondary winding side of the flyback transformer (3), and a high voltage output voltage E is connected to the terminal (5).
HV is taken out.

そして、ダンパーダイオード(6)と共1辰コンデンサ
(7)とが並列に接続されて第1の並列回路が構成され
るとともにダンパーダイオード(8)と共1辰コンデン
ザ(9)とが並列に接続されて第2の並列回路が構成さ
れ、これら第1及び第2の並列回路が直列に接続され、
その直列回路がトランジスタ(1)のコレクターエミッ
タ間に並列に接続される。
The damper diode (6) and the common 1-volt capacitor (7) are connected in parallel to form a first parallel circuit, and the damper diode (8) and the common 1-volt capacitor (9) are connected in parallel. to configure a second parallel circuit, and these first and second parallel circuits are connected in series,
The series circuit is connected in parallel between the collector and emitter of transistor (1).

また、(10)は水平偏向コイル、(11)は第1の8
字補止コンデンサ、(12)は変Jim用コイルで、こ
れら水平偏向コイル(10)、コンデンサ(11)、変
調用コイル(12)は直列に接続され、その直列回路が
トランジスタfilのコレクターエミッタ間に並列に接
続される。
(10) is the horizontal deflection coil, (11) is the first 8
The horizontal deflection coil (10), capacitor (11), and modulation coil (12) are connected in series, and the series circuit is connected between the collector and emitter of the transistor fil. connected in parallel.

そして、8字補正コンデンサ(11)と変調用コイル(
12)との接続点と、第1及び第2の並列回路の接続点
との間に第2の8字補正コンデンサ(13)が接続され
、このコンデンサ(13)トml及び第2の並列回路の
接続点との接続点に、変調源(14)よりの垂直周期の
電圧VMがコイル(15)を介して供給される。変調源
(14)とコイル(15)との接続点はコンデンサ(1
6)を介して接地される。
Then, the figure 8 correction capacitor (11) and the modulation coil (
A second figure-eight correction capacitor (13) is connected between the connection point with 12) and the connection point of the first and second parallel circuits, and this capacitor (13) and the second parallel circuit A vertically periodic voltage VM from a modulation source (14) is supplied via a coil (15) to the connection point with the connection point of the modulation source (14). The connection point between the modulation source (14) and the coil (15) is connected to the capacitor (1
6).

ごの場合、変調源り工4)より供給される電圧VMは第
4図に示すような下向きのパラボラ波である。
In this case, the voltage VM supplied by the modulation source 4) is a downward parabolic wave as shown in FIG.

このとき水平偏向コイル(lO)を介して図の矢印の向
きに偏向電流iyが流れるとき、変調用コイル(12)
には電圧VMによる変調電流1′が図のように流れる。
At this time, when the deflection current iy flows through the horizontal deflection coil (lO) in the direction of the arrow in the figure, the modulation coil (12)
A modulated current 1' by the voltage VM flows as shown in the figure.

したがって、水平偏向電流iyはトランジスタfilの
コレクタ電圧Vaと変調電圧VMとの差に応じたパラボ
ラ波電圧によって垂直周期で変調されたものとなり、左
右ピン歪が補正される。
Therefore, the horizontal deflection current iy is modulated with a vertical period by a parabolic wave voltage corresponding to the difference between the collector voltage Va of the transistor fil and the modulation voltage VM, and the left and right pin distortion is corrected.

この場合に、水平出力トランジスタ(11のコレクタ側
の電圧Vaは、変調電圧VMの影響を受けることはない
ので、端子(5)に導出されるdli I上出力奄圧E
 HVにも電圧VMによる変動はなく、良好な特性を示
すものである。
In this case, since the voltage Va on the collector side of the horizontal output transistor (11) is not affected by the modulation voltage VM, the output voltage E on the dli I led out to the terminal (5)
There is also no variation in HV due to voltage VM, indicating good characteristics.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

とごろで、電子ビームが水平方向に走査するとき、画面
の中央部と画面の左右端部とでは偏向中心からの距離が
異なるため、同し偏向角でも電子ビームの走査距離が異
なる。これを補正するため水平偏向電流波形である鋸歯
状波の傾斜部分は直線状ではなくS字状になるようにさ
れており、コンデンサ(11)  (第3図の例ではコ
ンデンサ(11)とコンデンサ(13)との直列容量)
はこのS字袖止のためのものである。
When the electron beam scans in the horizontal direction, the distance from the center of deflection is different between the center of the screen and the left and right edges of the screen, so the scanning distance of the electron beam is different even at the same deflection angle. In order to correct this, the slope part of the sawtooth wave, which is the horizontal deflection current waveform, is made to have an S-shape instead of a straight line. (13) Series capacitance)
is for this S-shaped armrest.

ここで、画商の垂直方向の上、1・とその中間部位とで
偏向中心からの距離が等しければ8字補正量は一定でよ
い。
Here, if the distances from the center of deflection are equal between 1 and the intermediate part in the vertical direction of the art dealer, the 8-character correction amount may be constant.

ところが、一般には偏向中心からの距離は内向の上下端
で遠く、中央部で最も近くなる。このため、8字補正量
が一定であると、第5図に不ずように画面の水平方向の
左右端で左右ピン歪が零になるように補正した場合、逆
に中間部において左右ピン歪が生じてくる。
However, in general, the distance from the center of deflection is far at the upper and lower ends of the inward direction, and closest at the center. Therefore, if the character-8 correction amount is constant, if the left and right pin distortion is corrected to zero at the left and right ends of the screen in the horizontal direction as shown in Figure 5, on the contrary, the left and right pin distortion will be reduced at the middle part. will arise.

近年、陰極線管は大型化するとともに画面がフラット化
してきており、このため、偏向中心からの画面の上下端
までの距離と、中央との距ntは画面が曲面の場合より
もより大きく、また偏向角も大きくなるので中間部の左
右ビン歪量が人き(なリ、その補正が重要な問題となっ
てきている。
In recent years, cathode ray tubes have become larger and their screens have become flatter, and for this reason, the distances from the center of deflection to the top and bottom edges of the screen and the distance nt from the center are larger than when the screen is curved. Since the deflection angle also increases, the amount of left and right bin distortion in the intermediate area increases (and its correction has become an important issue).

ところで、第3図の回路においてはこの中間左右ピン歪
の補正はある程度までF=J能である。すなわち、この
例の場合、8字補正は第1の8字補正コンデンサのめで
なく第2の8字補止コンデンサ(13)によってもなさ
れ、第20)8字軸止コンデンサ(■3)には変調電流
1′が流れるので、8字補正電圧は変aII11電圧V
Mによって画面の上Fと中央部とで異ならされ、これに
より中間ビン歪が補止される。
By the way, in the circuit shown in FIG. 3, this intermediate left and right pin distortion can be corrected to a certain extent by the F=J function. That is, in this example, the figure-8 correction is performed not only by the first figure-8 correction capacitor but also by the second figure-8 correction capacitor (13), and the 20th figure-8 correction capacitor (■3) Since the modulation current 1' flows, the figure 8 correction voltage is the variable a II 11 voltage V.
The upper F and center portions of the screen are made different by M, thereby correcting intermediate bin distortion.

この場合に、有効に補正するには両コンデンザ(11)
  (13)のシリーズ容量を一定にした状態でコンデ
ンサ(13)の容量を小さくすればよい。すなわち、第
2の8字軸止コンデンサ(13)には偏向電流iyと変
調電流i′が互いに逆向きに流れているので、このコン
デンサ(13)の容量が小さいほど、このコンデンサ(
■3)の両端の8字補止電圧が大きくなる。そして、第
6図Bに示すように画面の上下端と中央部での8字電圧
の差を大きくすることができ、中間ビン歪が補正される
。ごの場合、第6図へにボすように画面のhト端でS字
補正小、中央部でS″′f−1市正大となるようにされ
る。
In this case, to effectively correct both capacitors (11)
The capacitance of the capacitor (13) may be reduced while keeping the series capacitance of (13) constant. In other words, since the deflection current iy and the modulation current i' flow in the second figure-8 capacitor (13) in opposite directions, the smaller the capacitance of this capacitor (13), the more
■3) The figure-8 compensation voltage at both ends increases. Then, as shown in FIG. 6B, the difference between the figure-8 voltages between the upper and lower ends and the center of the screen can be increased, and the intermediate bin distortion can be corrected. In this case, as shown in FIG. 6, the S-shape correction is small at the h-edge of the screen, and the S-shape correction is large at the center.

以上のことから、第2の8字軸止コンデンサ(13)の
容量を、第1の8字補正コンデンサ(11)とこのコン
デンサ(13)とのシリーズ容量一定の条件の下に、よ
り小さくできれば、陰極線管の大型化及びフラン1−化
にも対応して中間ピン歪のない左右ビン歪陣正金行うこ
とができる。
From the above, if the capacitance of the second figure-8 fixed capacitor (13) can be made smaller under the condition that the series capacity of the first figure-8 correction capacitor (11) and this capacitor (13) is constant. In response to the increase in the size of cathode ray tubes and the use of fluorine tubes, it is possible to create left and right bin distortion lines without intermediate pin distortion.

ところが、偏向電流iyが大きくなると、この電流iy
により第2の8字補正コンデンサ(13)に生ずるS¥
亀圧が大きくなりすぎて、変6周電圧VMによる変調能
率が下がる現象があることが確かめられた。すなわち、
第3図の従来回路ではピン歪補正として変調電圧VMを
動かして変調電流i′をコントロールしていたので、電
流i′がある程度小さくなると、変調電流i′のループ
と偏向電流iyのループに共通に入っている8字軸止コ
ンデンサ(13)の偏向電流iyによる8字電圧が大き
くなって、変δIM’1lfl流i′を小さくする方向
(偏向電流!yが大きくなる方向)の制御が不ロJ能に
なってしまうのである。
However, when the deflection current iy increases, this current iy
S¥ generated in the second 8-figure correction capacitor (13) due to
It was confirmed that there is a phenomenon in which the tortoise pressure becomes too large and the modulation efficiency by the variable 6-cycle voltage VM decreases. That is,
In the conventional circuit shown in Fig. 3, the modulation current i' was controlled by moving the modulation voltage VM to correct pin distortion, so when the current i' becomes small to a certain extent, the loop of the modulation current i' and the loop of the deflection current iy are common. The figure 8 voltage due to the deflection current iy of the figure 8 capacitor (13) contained in the figure 8 shaft capacitor (13) increases, and the control in the direction of decreasing the variable δIM'1lfl flow i' (the direction in which the deflection current !y increases) becomes impossible. It becomes RoJ Noh.

このため、左右ビン歪補正の変調のダイナミックレンジ
が極端に狭(なり、左右ピン歪補正が実質上不tiJ能
になってしまう不都合がある。
As a result, the dynamic range of modulation for left and right bin distortion correction becomes extremely narrow, resulting in a disadvantage that left and right pin distortion correction becomes virtually impossible.

したがって、従来の回路では第2の8字補正コンデンサ
(13)の容量は、その両端に生じる8字電圧が大きく
なりすぎないような値にまでしか小さくすることはでき
ず、中間ビン歪はある程度までしか補正をできず、大型
かつ画面フラットの陰極線管の場合には不十分であった
Therefore, in the conventional circuit, the capacitance of the second figure-8 correction capacitor (13) can only be reduced to a value that prevents the figure-8 voltage generated across it from becoming too large, and the intermediate bin distortion is reduced to a certain extent. This was insufficient for large cathode ray tubes with flat screens.

〔問題点を解決するための手段〕[Means for solving problems]

この発明においては、水平出力スイッチング素子(11
と、それぞれダンパーダイオード+6) f81と共振
コンデンサ(71(91とが並列に接続されて構成され
た第1及び第2の並列回路と、水平偏向コイル(10)
と、第1及び第2の8字補正コンデンサ(11)(13
)と、変調用コイル(20a )と、この変調用コイル
(20a )とトランス結合された補止:Jイル(20
b )とを設け、」−記第1及び第2の並列回路を直列
に接続して水平出力スイッチング素子(1)に並列に接
続し、水平偏向コイル(10)と第1の8字補正コンデ
ンサ(11)と補iEコイル(20b )と変調用コイ
ル(20a)とを直列接続して水平出力スイッチング素
子(1)に並列に接続し、−上記第1及び第2の並列回
路の接続点と補止コイル(20t+)及び変調用コイル
(20a )の接続点間に第2の8字補正コンデンサ(
13)を接続し、上記第1及び第2の並列回路の接続点
に垂直周期のパラボラ波を供給する。
In this invention, the horizontal output switching element (11
and a damper diode +6, respectively), first and second parallel circuits configured by connecting f81 and a resonant capacitor (71 (91) in parallel, and a horizontal deflection coil (10).
and the first and second figure 8 correction capacitors (11) (13
), a modulation coil (20a), and an auxiliary coil (20a) connected to the modulation coil (20a) by a transformer.
b), the first and second parallel circuits are connected in series and connected in parallel to the horizontal output switching element (1), and the horizontal deflection coil (10) and the first figure-eight correction capacitor are connected in series. (11), the auxiliary iE coil (20b), and the modulation coil (20a) are connected in series and connected in parallel to the horizontal output switching element (1), and - the connection point of the first and second parallel circuits is connected in series. A second figure-8 correction capacitor (
13) to supply a vertically periodic parabolic wave to the connection point of the first and second parallel circuits.

〔作用〕[Effect]

変調用コイル、をトランス構造として、このトランス(
20)の2次コイルである補正コイル(20b )に偏
向電流を流すことにより、トランス結合による起電力で
変調電流i′を小さく (偏向電流iyを大きく)する
ことができるため、第2のS?補正コンデンサ(13)
の容量を小さくしても左右ビン歪補正として十分なダイ
ナミックレンジを得るごとができる。
This transformer (
By passing a deflection current through the correction coil (20b), which is the secondary coil of the second S ? Correction capacitor (13)
Even if the capacitance of is made small, a sufficient dynamic range can be obtained for right and left bin distortion correction.

〔実施例〕〔Example〕

201図はこの発明の一実施例をボし、この発明におい
ては従来1す1路の変調用コイル(12)をトランス構
造とするものである。
FIG. 201 shows an embodiment of the present invention, in which the conventional one-way modulation coil (12) has a transformer structure.

すなわち、第1図においてトランス(20)がそれで、
このトランス(20)の1次巻線(20a )が従来回
路の変調用コイル(12)に相当するものである。そし
て、この1−ランス(20)の2次巻線(20b )は
第1の8字補正コンデンサ(11)に直列に接続される
とともに、その一端は第2の8字補正コンデンサ(13
)とトランス(20)の1次巻線(20a)との接続点
に接続される。つまり、2次イ8線(20b)は偏向電
流iyが流れるループ内に(小人されることになる。こ
の場合、トランス(20)の極性は図のように同極性と
されている。
That is, in FIG. 1, the transformer (20) is
The primary winding (20a) of this transformer (20) corresponds to the modulation coil (12) of the conventional circuit. The secondary winding (20b) of this 1-lance (20) is connected in series to the first figure-8 correction capacitor (11), and one end of it is connected to the second figure-8 correction capacitor (13).
) and the primary winding (20a) of the transformer (20). In other words, the secondary A8 wire (20b) is placed in the loop through which the deflection current iy flows.In this case, the polarity of the transformer (20) is the same as shown in the figure.

以上の回路において、変i!J!d ?’41圧v8を
−1・げ“ζ偏向電流iyを大きく、変調電流i′を小
さくしてゆくと、偏向電流iyがトランス(20)の2
次巻!! (20b )を通じ゛(流れるので、このト
ランスの極性が同極性であるため1次巻線(20a)に
は電/Jlf、1′を小さくする方向の起電力が生じる
。したがって、偏向電流iyが大きいとき、第2のS字
?4i +Eコンデンサ(13)のこの電流iyによる
S字電用が大きくなっても、変調電流i′を小さくする
ことができるため、この電流i′を小さくする方向での
ダイナミックレンジが非常に広くなる。
In the above circuit, change i! J! d? '41 When the voltage v8 is increased by -1 and the deflection current iy is increased and the modulation current i' is decreased, the deflection current iy increases to 2 of the transformer (20).
Next volume! ! Since the polarity of this transformer is the same, an electromotive force is generated in the primary winding (20a) in the direction of decreasing the electric current /Jlf,1'. Therefore, the deflection current iy When it is large, even if the S-curve current iy of the second S-curve capacitor (13) becomes large, the modulation current i' can be made small, so the direction in which this current i' is made small is The dynamic range becomes extremely wide.

このため、中間ピン歪補止のため、この第2のS′¥補
正コンデンザ(13)の容量を小さくしても左右ピン歪
補正のダイナミックレンジは広くと咋、実用上十分ii
J能な左右ピン歪補正回路が実現できる。
Therefore, in order to compensate for intermediate pin distortion, even if the capacitance of this second S' correction capacitor (13) is reduced, the dynamic range of left and right pin distortion correction is wide enough for practical use.
A highly efficient left and right pin distortion correction circuit can be realized.

この場合、トランス(20)の2次巻線(20b )の
挿入によりコンデンサ(13)の電流iyによる8字電
圧は第2図Aにボず従来のものに比べ゛(同図Bにボず
ように小さくなるが、画面中央でのS字電圧IF、 C
と画面の上下端でのS字電圧IEcO差は変わらないこ
とが実験的に確かめられた。
In this case, due to the insertion of the secondary winding (20b) of the transformer (20), the figure 8 voltage due to the current iy of the capacitor (13) does not appear in Figure 2A, and is lower than in the conventional case (it does not appear in Figure 2B). However, the S-curve voltage IF at the center of the screen, C
It was experimentally confirmed that the S-curve voltage IEcO difference between the top and bottom edges of the screen remains unchanged.

したがって、中間ピン歪も十分に補止されることがごれ
からもわかる。
Therefore, it can be seen from the dirt that the intermediate pin distortion is also sufficiently compensated.

以上のようにコンデンサ(13)の容量を、コンデンサ
(11)と(13)とのシリーズ容量を一定に保った状
態で小さくして、中間ピン歪を十分に補正するようにし
た場合においても左右ピン歪補正が十分にダイナミック
レンジの広い状態で行えることは実験的にも確かめられ
た。
As described above, even if the capacitance of capacitor (13) is made small while keeping the series capacitance of capacitors (11) and (13) constant, and the intermediate pin distortion is sufficiently corrected, It has been experimentally confirmed that pin distortion correction can be performed with a sufficiently wide dynamic range.

すなわち、偏向コイル(10)のインダクタンス値を0
.82m1l、トランス(20)の巻線比を7’7:2
0.1次巻線のインダクタンス値を0.4m)I 、第
1のS字?Ji止コンデンサ(11)の容量を2.0μ
F 、 第20s 7−補正J1ンデン’1(13)の
容♀を0.56μFとしたとき、2B型陰穫線管で中間
ピン歪の残留は1%になった。
In other words, the inductance value of the deflection coil (10) is set to 0.
.. 82ml, transformer (20) winding ratio 7'7:2
0. The inductance value of the primary winding is 0.4 m)I, the first S-curve? The capacitance of the Ji stop capacitor (11) is 2.0μ.
F, 20th 7-Correction J1 Den'1 (13) When the capacitance ♀ was 0.56 μF, the residual intermediate pin distortion was 1% in the 2B type negative ray tube.

なお、ダイナミックレンジをこれを同一の条件のトで従
来の回路において、コンデンサ(11)の容量を1.0
μF、コンデンサ(13)の容量を1.0μmtとした
とき、1iilじ人きさの陰+・!18線管において残
留する中間ピン歪量は3%であったのご、この発明によ
れば中間ピン中を従来の 1/3にすることができたこ
とになる。
In addition, in the conventional circuit under the same dynamic range conditions, the capacitance of the capacitor (11) is 1.0.
μF, when the capacitance of the capacitor (13) is 1.0 μmt, 1iiiil the shadow of humanity +・! The amount of distortion in the intermediate pin remaining in the 18-wire tube was 3%, but according to this invention, the amount of distortion in the intermediate pin could be reduced to 1/3 of the conventional amount.

なお、巻線比の2次側の値は5〜30の間であれば実用
上十分であることも実験]1確かめられた。
It was also confirmed through experiment 1 that a value on the secondary side of the winding ratio between 5 and 30 is practically sufficient.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、変調用コイルをトランス構造とする
だけの簡単な構成により、左右ビン1″V補IEのダイ
ナミックレンジを(准保した状態で中間ピン歪を十分に
補正できる。
According to the present invention, with a simple configuration in which the modulation coil has a transformer structure, it is possible to sufficiently correct the intermediate pin distortion while maintaining the dynamic range of the left and right bin 1'' V supplementary IE.

したがって、この発明は大型で、画商のソラノトな陰極
線管の水平偏向回路とし゛ζ非常に有益なものであり、
その効果は実用」−著しいものがある。
Therefore, this invention is very useful as a horizontal deflection circuit for large-scale cathode ray tubes used by art dealers.
Its effects are significant in practical use.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例の回路図、第2図はその要
部の説明のための波形図、第3図は従来回路の一例の回
路図、第4図はその要部の説明のための波形図、第5図
は従来回路による補正画面を説明するための図、第6し
1はそのべ1明のための波形図である。 (1)は水平出力トランジスタ、(6)及び(8)ばダ
ンバ−ダイオード、(7)及び(9)は共振コンデンサ
、(109は偏向コイル、(11)は第1の8字補正コ
ンデンサ、(13)は第2の8字補正コンデンサ、(1
4)は変調源、(20)はトランス、(20a )は変
d周用コイルとなるI−ランス(20)の1次巻線、(
20b )は抽市コイルとなるトランス(20)の2次
巻線で1bる。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining its main parts, Fig. 3 is a circuit diagram of an example of a conventional circuit, and Fig. 4 is an explanation of its main parts. FIG. 5 is a diagram for explaining the correction screen by the conventional circuit, and FIG. 6 is a waveform diagram for the first part. (1) is a horizontal output transistor, (6) and (8) are damper diodes, (7) and (9) are resonance capacitors, (109 is a deflection coil, (11) is the first figure-8 correction capacitor, ( 13) is the second figure 8 correction capacitor, (1
4) is the modulation source, (20) is the transformer, (20a) is the primary winding of the I-lance (20) which becomes the variable d frequency coil, (
20b) is the secondary winding of the transformer (20) which serves as the lottery coil.

Claims (1)

【特許請求の範囲】 水平出力スイッチング素子と、それぞれダンパーダイオ
ードと共振コンデンサとが並列に接続されて構成された
第1及び第2の並列回路と、水平偏向コイルと、第1及
び第2のS字補正コンデンサと、変調用コイルと、この
変調用コイルとトランス結合された補正コイルとを有し
、 上記第1及び第2の並列回路が直列に接続されて上記水
平出力スイッチング素子に並列に接続され、上記水平偏
向コイルと上記第1のS字補正コンデンサと上記補正コ
イルと上記変調用コイルとが直列接続されるとともにそ
の直列回路が上記水平出力スイッチング素子に並列に接
続され、上記第1及び第2の並列回路の接続点と上記補
正コイル及び上記変調用コイルの接続点間に上記第2の
S字補正コンデンサが接続され、上記第1及び第2の並
列回路の接続点に垂直周期のパラボラ波が供給されるよ
うにされてなる水平偏向回路。
[Claims] A horizontal output switching element, first and second parallel circuits configured by connecting a damper diode and a resonant capacitor in parallel, a horizontal deflection coil, and first and second S The first and second parallel circuits are connected in series and connected in parallel to the horizontal output switching element. The horizontal deflection coil, the first S-shaped correction capacitor, the correction coil, and the modulation coil are connected in series, and the series circuit is connected in parallel to the horizontal output switching element, and the first and second S-shaped correction capacitors are connected in series. The second S-shaped correction capacitor is connected between the connection point of the second parallel circuit and the connection point of the correction coil and the modulation coil, and the second S-shaped correction capacitor is connected to the connection point of the first and second parallel circuits. A horizontal deflection circuit that is supplied with parabolic waves.
JP21675785A 1985-09-30 1985-09-30 Horizontal deflection circuit Expired - Lifetime JPH0638633B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21675785A JPH0638633B2 (en) 1985-09-30 1985-09-30 Horizontal deflection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21675785A JPH0638633B2 (en) 1985-09-30 1985-09-30 Horizontal deflection circuit

Publications (2)

Publication Number Publication Date
JPS6276972A true JPS6276972A (en) 1987-04-09
JPH0638633B2 JPH0638633B2 (en) 1994-05-18

Family

ID=16693439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21675785A Expired - Lifetime JPH0638633B2 (en) 1985-09-30 1985-09-30 Horizontal deflection circuit

Country Status (1)

Country Link
JP (1) JPH0638633B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02308675A (en) * 1989-05-23 1990-12-21 Totoku Electric Co Ltd Horizontal deflection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02308675A (en) * 1989-05-23 1990-12-21 Totoku Electric Co Ltd Horizontal deflection circuit

Also Published As

Publication number Publication date
JPH0638633B2 (en) 1994-05-18

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