JPS6276874A - Driving method for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To process an picture signal at a high speed by setting the even- number-line selecting pulse input terminals and the odd-number-line selecting pulse input terminals of an interlace circuit to the H-state for all the field periods. CONSTITUTION:Even in the second field, the switches 35 and 36 of the interlace circuit 25 are closed because of the high level of pulses F1 and F2, and the same pulses phiV1 and phiV2 as the first field are inputted. Accordingly, the signal charges from the photodiodes in the same combination of odd/even-number lines are mixed with each other, and sequentially outputted. By making the pulse input terminal of the interlace circuit be in H-state for all the field periods the signal charges from the photodiodes in the same combination of odd-even- number lines are mixed, then outputted in order, signal charges which are the mixture of charges from photodiodes in the same combination are obtained in each field. Accordingly, in a use real time processing is necessary, the number of data is decreased to half and the data is made of more effective constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) 1. The present invention relates to a method for driving a solid-state image sensor.

(Prior Art) Solid-state image sensors have various features not found in conventional image pickup tubes, such as small size, light weight, and long life, and are used not only for home video cameras, but also for surveillance and robot vision sensors. It is expected to be used as an industrial camera.

When used as a robot visual sensor or for industrial measurement, image processing and signal processing by a computer is a prerequisite, and in particular, real-time processing is often required, and the processing speed is an issue.

Hereinafter, a conventional method for driving a solid-state image sensor will be described with reference to the drawings.

FIG. 2 is an example of a circuit diagram schematically showing a solid-state image sensor. In FIG. 2, reference numeral 21 denotes a photodiode for photoelectric conversion, and a number of photodiodes corresponding to the number of scanning lines of a monitor TV are lined up in the vertical direction. 22 is a MOS switch for transferring the signal charge accumulated in the photodiode 21 to the vertical signal line 26; 23-^, 23-n, 23;
-C, . . . are vertical scanning pulse input lines connected to the gates of MOS switches 22 for each horizontal row, 24 is a vertical shift 1 register, and 25 is a photo signal for scanning pulses output from vertical shift 1 to registers 24. M connected to diode
Even-numbered rows and odd-numbered rows of vertical scanning pulse input lines 23 -A are connected to the OS switch 22 .

23-Skin 23-C..., 26 is a vertical signal line, 27 is for horizontally transferring signal charges of even and odd columns of two-dimensionally arranged photodiodes 21, respectively. horizontal CCr), 28 is a transfer gate that transfers the signal charge transferred from the photodiode 21 to the vertical signal line 26 to the horizontal CCD 27.

FIG. 3 shows an example of a circuit diagram of a vertical scanning section comprised of the vertical shift register 24 and interlace circuit 25 shown in FIG. In Figure 3, 3], 3
2 are input terminals for the first pulse φv2 and the second pulse φv1 for driving the vertical shift register 24, respectively; 33.
34 are input terminals of the third pulse [Pa1 and the fourth pulse F2 for driving the interlacing circuit 25, respectively. Note that the pulses Fl and F2 are pulses for selecting photodiodes, respectively, as will be described later. Also, 341.3/12,・
....

346 is the name of the vertical shift register 24, and the pin 1- is used to shift the vertical shift register 1 to register 2 every pulse φv1 or φv2.
4 data is shifted one bit at a time. However, φv2
When is input, the data is transferred from the odd numbered bits 341, 343, 345, . . . to the even numbered bits 342, 344, 346, . When input, vertical shift 1 to even number of registers [1 bits 342, 344.3116...
Odd numbers [341, 343, 345 to 1 of 1]
・Head data is transferred. The outputs of vertical shift 1 to even-numbered bits of register 24: (42, 314, 346, . . . are connected to interlace circuit 26, and switch 3
Vertical scan pulse input line 23-A through 5.36.

It is connected to 23-B, 23-C, . The pulses Fl and F2 input to the pulse input terminals 33 and 34 of the inter-1 north circuit 25 are transmitted to the switch 35 and
:(connected to switch 35 by the input of pulses F I and F 2.

36 to open and close the output of the vertical shift register 24 to the vertical scanning pulse input lines 23-A, 23-13, 23-C, .
・It is configured to send to.

FIG. 4 shows a timing chart of conventional drive pulses for the solid-state image sensor shown in FIGS. 2 and 3. FIG. FIG. 4 shows pulses φ■1, φv2 input to the vertical shift register 24.
, the pulse I・' input to the interlacing circuit 25
I, F2, and vertical scanning pulse input lines 23-A, 23-B, 23- from the interlacing circuit 25.
It shows pulses φA, φB, φC, . . . output to C...

However, each pulse is output during the horizontal blanking period.

The operation of the solid-state image sensor configured as above will be explained.

First, during the first horizontal blanking period of the first field,
Each bit of the vertical shift register 24 is reset to the rLJ level, and only the first bit 341 is set to the rHJ level. Further, in the first field, the input pulse F1 of the interlacing circuit 25 is at the old level, the pulse F2 is at the "I4" level, the switch 35 is in the closed state, and the switch 36 is in the open state. When one pulse φv2 is input in the next horizontal blanking period, the data of bit 341 (roll level) moves to Phi:(42 by 1 bit,
Via the switch 35, the vertical scanning pulse input line 23-A
becomes the "11" state (pulse φA), and the signal charge of the photodiode 21 in the column connected to the vertical scanning pulse input line 23-A is transferred to the vertical signal line 26 through the MOS switch 22, and transferred to the transfer gate 28 and the horizontal CCD 27. is output to the outside of the solid-state image sensor.

Subsequently, when pulse φv1 is input and one pulse φv2 is input during the next horizontal blanking period, the data of bit 342 (rllJ state) is transferred to bit 344, and in the same way, vertical scanning pulse The input line 23-c is “
It becomes open state (pulse φC) and vertical scanning pulse input line 2
The signal charge of the photodiode 21 connected to 3-C is output.

Similarly, from then on, the vertical scanning pulse input line 23-E becomes open (pulse φ), and the signal charges of the odd-numbered photodiodes 1 are sequentially output in the first field. I'm going to go.

On the other hand, in the second field, the pulse F1 is “1”.
．． '' level and the pulse signal 2 is at the ``H'' level, so this time, the switch 35 is open and the switch 36 is closed, and the vertical scanning pulse input line 23-8.

23-D, 23-F, . . . , the even-numbered vertical scanning pulse input lines sequentially become "11" (pulse φB).

φD, φF), the signal charges of the even-numbered photodiodes are sequentially output.

As shown in I- below, the signal voltage loads of the photodiodes in odd-numbered rows in the first field and in even-numbered rows in the second field are sequentially output, resulting in interlaced scanning in the first and second fields.

(Problems to be Solved by the Invention) However, with the above-described method of driving a solid-state image sensor, there is no problem at all when using it for a normal surveillance camera, but when it is used as a visual sensor for robots 1~ or an industrial For applications that require real-time processing, such as measurement and automatic control,
Interlaced scanning complicates signal processing, and unless two fields are waited, all information cannot be obtained, which hinders high-speed processing.

SUMMARY OF THE INVENTION In view of the drawbacks mentioned in -1-, the present invention provides a method for driving a solid-state image sensor suitable for applications requiring high-speed processing of image signals.

(Means for Solving the Problems) In order to solve the above problems, a method for driving a solid-state image sensor according to the present invention includes a group of photoelectric conversion elements arranged two-dimensionally,
A vertical shift register with a MOS type structure, a vertical signal line,
A horizontal CCD, a switch element made of MOSj7II for transferring the signal charge accumulated in the photoelectric conversion element to the vertical signal line, and an even row selection pulse input terminal using a pulse generated from the vertical shift register. and an interlace circuit that selects an even row or an odd row of the photoelectric conversion element group depending on a state of an odd row selection pulse input terminal, the even row selection pulse input terminal of the interlace circuit; The odd row selection pulse input terminal is kept open during the entire field period.

(Function) With this configuration, all image information of the solid-state image sensor can be obtained in one field period, and since it is not interlaced scanning,
Image processing is easy, and the number of image information data is halved.
Ideal for applications requiring real-time processing.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a pulse timing diagram in the wave force method of a solid-state image sensor according to an embodiment of the present invention. The solid-state imaging device used here is the same as that shown in FIGS. 2 and 3. In FIG. 1, vertical shift register 24
input pulses φVl, φV2, interlace circuit 25
input pulses Fl, F2 and vertical shift register 2
4 to vertical scanning pulse input lines 23-A, 23-B, 23
-C, . . . are output pulses φA.

Pulses of φB, φC9, . . . are shown. It is assumed that each pulse is output during a horizontal blanking period.

The operation of the method for driving the solid-state image sensor configured as described above will be described below.

What is characteristic here is that the pulses Fl and F2 are at the It level together with the first field and the second field, and the switches 35 and 36 of the interlacing circuit 25 are always closed.

First, during the first horizontal blanking period of the first field, each pin of the vertical shift register 24 is reset to the "1" level, and only the first bins 1 to 341 are set to the "11" level. Pulse φ in the next horizontal blanking period
When one v2 is input, the data of bit 341 (“H
” level) moves to bit 342, and bit 342 goes to “H” level).
” level, and the vertical scanning pulse input lines 23-A and 23-13 are both set to “11” via the switches 35 and 36.
state (pulses φA, φB), the signal charge of the diode 2 passes through the MOS switch 22 and is transferred to the vertical signal line 26 to the column FO 1 connected to the vertical scanning pulse input lines 23-A and 23-8, and the vertical signal On the line, the signal charges of the vertical two photodiodes are mixed, and the transfer gate 28, the horizontal C
The signal passes through the CD 27 and is output to the solid-state image pickup section.

=10= Subsequently, one pulse φVl is input to the vertical shift register 24, and one pulse φ■2 is manually input during the next horizontal blanking period, so that the bit 344 of the vertical shift register is set to "open". The signal charges of the photodiodes corresponding to the vertical scanning pulse input lines 23-C and 23-D are mixed and output.Then, in the same manner,]
For each horizontal blanking, pulses φVl and φv2 are input, and the signal charges of the photodiodes in the odd and even rows are mixed and sequentially output.

Also in the second field, pulses Fl and F2 are “H”
Since the switches 35 and 36 of the interlacing circuit 25 are both in the closed state, by inputting the same pulses φVl and φv2 as in the first field, the signal charges of the photodiodes in the odd and even rows of the same combination are They are mixed and output sequentially.

As described above, according to this embodiment, by keeping the pulse input terminal of the interlacing circuit open for the entire field period, the signal charges of the photodiodes in the odd and even rows are mixed and output, and Since signal charges mixed with the same combination of FO 1 diodes are obtained for each field, the number of data is halved and the configuration is effective for applications requiring real-time processing.

(Effects of the Invention) As described in ``2'' below, the present invention provides a pulse input terminal of an interlace circuit of a solid-state image sensor for the entire field period.
state, odd row, even row pixels (photodiode)
By mixing and outputting the signal charges accumulated in the , the number of data can be halved for high-speed image processing, and the complex processing of interlace processing can be eliminated, making it ideal for recent mechatronics-related fields. A solid-state imaging device can be realized, and its practical effects are enormous.

[Brief explanation of drawings]

FIG. 1 is a timing diagram showing a method of driving a solid-state image sensor according to an embodiment of the present invention, FIG. 2 is an example of the circuit configuration of the solid-state image sensor, and FIG. 3 is a diagram showing the vertical scanning section of the solid-state image sensor. An example of the circuit, FIG. 4, is a timing diagram showing a conventional method of driving a solid-state image sensor. 2]...Photodiode, 22...MOS switch, 23-A, 23-n,..., 23-F.
. . . Vertical scanning pulse input line, 24 . . . Vertical shift register, 25 . . . Interlace circuit, 26 . . . Vertical signal line, 27 . Patent applicant: Matsushita Electronics Co., Ltd. Section 1 φF Figure 2 Figure 3

Claims (1)

[Claims] A group of photoelectric conversion elements arranged two-dimensionally, a vertical shift register having a MOS type structure, a vertical signal line, a horizontal CCD, and for transferring signal charges accumulated in the photoelectric conversion elements to the vertical signal line. and a pulse generated from the vertical shift register, and selects an even row or an odd row of the photoelectric conversion element group according to the states of an even row selection pulse input terminal and an odd row selection pulse input terminal. A method for driving a solid-state image sensing device comprising an interlacing circuit, characterized in that an even-numbered row selection pulse input terminal and an odd-numbered row selection pulse input terminal of the interlace circuit are kept in an "H" state for the entire field period. How to drive the image sensor.