JPS6276764A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To obtain the titled device having less deterioration in an image by arranging photosensitive picture element units for storing a signal generated by an incident light on a semiconductor substrate and vertical shift registers disposed therebetween for separately transferring smear charge in a matrix state, and discharging the transferred smear charge by the register. CONSTITUTION:Photosensitive picture element units 2 for storing signal charge generated by incident light on an Si substrate 1 are formed in a matrix state, and vertical shift registers 3 for separately transferring smear charge stored in the units 2 are provided thereamong, and sequentially selected by an address circuit 4. Transfer electrodes 5, 6 having gate 14 and drain 15, a storage unit 7, a transfer electrode 8 are provided in parallel, terminals 16-20 are attached thereto, horizontal shaft registers 11 having output terminals 25 are arranged thereunder, smear charge from the register 3 is discharged from the terminal 16 through the drain 15 and the gate 14.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a solid-state imaging device, and particularly to a line address type C
CD (Charge Coupled Device
) Regarding image sensors.

[Technical background of the invention and its problems]

The conventional line address type COD image sensor
As shown in the figure, a photosensitive pixel section 2 arranged in a matrix on a semiconductor substrate 1, a vertical shift register 3 arranged in a vertical line adjacent to the photosensitive pixel section 2, and a photosensitive pixel section 2 an address circuit 4 for selecting row by row;
a storage section 9 disposed at the lower end of the vertical shift register 3;
It consists of horizontal shift registers 11 arranged in a horizontal line adjacent to this storage section 9. Further, transfer electrodes 8. are provided between the vertical shift register 3 and the storage section 9 and between the storage section 9 and the horizontal shift register 11, respectively.
10 are provided. and horizontal shift register 11
is connected to the output terminal 25.

Next, the operation will be explained. First, during the horizontal blanking period, the photosensitive pixel sections 2 are sequentially selected row by row by the address circuit 4, and the signal charges accumulated in the photosensitive pixel sections 2 are transferred to the vertical shift register 3.

Then, by applying a clock pulse to the vertical shift register 3, the signal charge is transferred to the storage section 9 until the next horizontal blanking period.

During the next horizontal blanking period, the signal charges in the storage section 9 are transferred to the horizontal shift register 11. At this time, the next row of the photosensitive pixel section 2 is selected by the address circuit 4, and transfer of the signal charge of the photosensitive pixel section 2 to the vertical shift register 3 is started.

After the horizontal blanking period, a clock pulse is applied to the horizontal shift register 11, so that the signal charge in the horizontal shift register 11 is transferred to the output terminal 25.

These series of operations are repeated, and the signal charges of the photosensitive pixel portion 2 are read out from the output terminal 25 as an image signal in a predetermined order.

However, in the above solid-state imaging device, when excessive light is incident, a blooming phenomenon or a smear phenomenon occurs. The blooming phenomenon that occurs when excessive signal charges generated in the photosensitive pixel section 2 overflow can be suppressed by, for example, providing an overflow drain (not shown) close to the photosensitive pixel section 2 and allowing the excess signal charge to flow therein. can do. However, the smear phenomenon caused by charges generated in the semiconductor substrate 1 directly flowing into the vertical shift register 3 cannot be sufficiently suppressed. This smear phenomenon significantly deteriorates the image quality for subjects with excessive light.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a solid-state imaging device that does not cause deterioration in image quality due to the smear phenomenon.

[Summary of the invention]

In order to achieve the above object, a solid-state imaging device according to the present invention includes:
a semiconductor substrate; a photosensitive pixel section arranged in a matrix on the semiconductor substrate and accumulating signal charges generated by incident light; and a photosensitive pixel section arranged in a vertical line adjacent to the photosensitive pixel section, a vertical shift register that separately transfers the signal charge accumulated in the photosensitive pixel portion and the injected smear charge by a transfer electrode; a smear charge discharge means for discharging the smear charge transferred by the vertical shift register; and the vertical shift register. , an accumulation section that accumulates the transferred signal charge, a horizontal shift register 1 to register that transfers the signal charge accumulated in this accumulation section, and an output that outputs a signal based on the signal charge transferred by this horizontal shift register. It is characterized by having a section.

Thereby, the signal charge from which the mixed smear charge has been removed is read out as an image signal.

[Embodiments of the invention]

FIG. 1 shows a plan view of a solid-state imaging device according to an embodiment of the present invention. For example, on the semiconductor substrate 1, which is an n-type silicon substrate,
The photosensitive pixel portions 2 that accumulate signal charges generated by incident light are arranged in a matrix of, for example, 500×400. A vertical shift register 3 that transfers the signal charges accumulated in the photosensitive pixel section 2 by a transfer electrode is
They are arranged in a vertical line adjacent to the photosensitive pixel section 2.

Further, an address circuit 4 is provided which sequentially selects, row by row, the photosensitive pixel portions 2 whose signal charges are transferred to the vertical shift register 3. At the lower end of the vertical shift register 3, an accumulation section 7 that accumulates the signal charges transferred to the vertical shift 1 by the register 3 via the transfer electrodes 5 and 6 is disposed, and a horizontal shift register 11
are arranged adjacent to each other in a horizontal line. Further, a drain 15 is placed in a region covered by the transfer electrode 5 via a control gate 14 . These control gates 14
is connected to the terminal 16, the drain 15 is connected to the terminal 17, and the transfer electrode 5 is connected to the terminal 16.
is connected to the terminal 18, the transfer electrode 6 is connected to the terminal 19, the storage section 7 is connected to the terminal 20, and the transfer electrode 8 is connected to the terminal 21. The horizontal shift registers 11 that transfer the signal charges in the storage section 7 using transfer electrodes are connected to output terminals 25, respectively.

Further, a sectional view taken along the line AA and sectional view taken along the line BB in FIG. 1 are shown in FIGS. 2 and 3, respectively. The photosensitive pixel portion 2 has a photodiode structure consisting of an n+ impurity region 30 formed on the surface of a p-well region 29 with a shallow junction on the surface of the n-type semiconductor substrate 1.

The vertical shift register 3 adjacent to the photosensitive pixel section 2 is
A buried channel consisting of an n+ impurity region 32 formed on the surface of the n-type semiconductor substrate 1 with a deep junction p-well region [31] and an insulating layer 33 made of, for example, a silicon oxide film formed above the buried channel. The transfer electrode 34 is also grooved. A light shield layer 35 made of aluminum, for example, is formed above the transfer electrode 34 via an insulating layer 33 to prevent light from entering. Further, above the photodiode structure of the photosensitive pixel section 2, the light shield layer 35 is opened to allow light to enter.

Further, on the surface of the p well region 1fi31 on the surface of the n-type semiconductor substrate 1 below the transfer electrode 5, an n+
An impurity region 36 is formed. An n+ impurity region 37 with a deep junction as the drain 15 is formed adjacent to this n+ impurity region 36. The boundary between these two n+ impurity regions 36 and 37 is covered by the control gate 14.

Further, the upper portions of the transfer group 1-5 and the control gate 14 are covered with a light shield layer 35 with an insulating layer 33 interposed therebetween.

Next, the operation will be explained using FIG. 4. FIG. 4 shows the transfer electrode 34 in the vertical shift register 3 and the transfer electrode 5.
6, a potential well formed by applying a predetermined pulse to the storage electrode 38 and the transfer electrode 8 in the storage section 7, and the state of the charges accumulated in these potential wells. be. First, during the horizontal blanking period,
The address circuit 4 sequentially selects the photosensitive pixel portions 2 row by row, and transfer electrodes 34 adjacent to the selected photosensitive pixel portions 2
A selection pulse with a positive high voltage is applied to the photosensitive pixel portion 2, and the signal charges accumulated in the photosensitive pixel portion 2 are transferred to the adjacent vertical shift registers 1 to 3. Then, the transfer electrode 34 and the transfer electrodes 5 and 6 of the vertical shift register 3 are applied with, for example, a high level voltage, which is the ground voltage (2) with the p-well region 31 as a reference. , a four-phase clock pulse whose low level voltage is a negative voltage VL is applied, and as shown in FIG. 5(b), signal charges Qs1 . Q
S? Qs3 is transferred.

At this time, the four-phase clock pulse is either the ground voltage V or a negative voltage V, so that the n+ impurity region 3o of the photosensitive pixel portion 2 and the n+ impurity region 3o of the vertical shift register 3 are
The p-well region 31 acts as a potential barrier between the + impurity region 32 and the signal charge of the photosensitive pixel portion 2 does not flow into the vertical shift register 3.

In addition, when excessive light is incident and excessive signal charges are generated in the photosensitive pixel section 2, a vertical overflow drain is formed in which the junction of the p-well region 29 where the n+ impurity region 30 of the photosensitive pixel section 2 is formed is shallow. Because of the structure,
A positive high voltage is applied to the n-type semiconductor substrate 1, punch-through occurs in the p-well region 29 having a shallow junction, and excess signal charges are discharged to the n-type semiconductor substrate 1. In this way, the blooming phenomenon is suppressed.

However, some of the charges generated in the deep p-well region 31 of the junction may flow into the vertical shift register 3, or the n+ impurity region 32 as a buried channel of the vertical shift register 3 may be scattered due to the scattering of incident light. It happens that a charge is generated. Although these smear charges are small, they are almost uniformly applied to the wells at each potential. Strictly speaking, the smear charge increases as the vertical shift register 3 approaches the storage section 7.9;
Here, in order to simplify the explanation, the barrier of smear charges accumulated in each potential well is assumed to be a constant value Q0.

Therefore, as shown in FIG. 4(b), the signal charges Q,
1. Q, 2. Q, 3 each include a smear charge Q, and signal charges Q81. In potential wells other than the potential well where Q, 2°Qs3 is transferred,
A smear charge Qr1 is transferred to each of them.

Before the signal charge Q31''s2.Qs3 is transferred to the potential well below the transfer electrode 5, a positive high voltage is applied to the control gate 14 shown in FIG.
Smear charge Q transferred to the potential well below. are sequentially discharged to the drain 15 to which a heavy high voltage is applied.

For this reason, as shown in FIG. 4(b), J: sea urchin, transfer electrode 5
The potential well below the storage electrode 38 becomes empty of charge.

Signal charge Q81. Q52. When QS3 is transferred to the potential well below the transfer electrode 5, a negative voltage V is applied to the control groups 1 to 14, and the signal charges Q, 1. QS2. Q[ , 3 is prevented from being discharged to the drain 15. The storage electrode 38 and the transfer electrode 8 are supplied with, for example, a high voltage VH1 whose high level voltage is positive, and a low level voltage which is applied to the transfer electrode 34. ．．
Since a four-phase clock pulse with the same negative voltage ■[ as the low level voltage of 5.6 is applied, the signal charge Q81. QS2. Q,3 is sequentially transferred to the potential well below the storage electrode 38 and the transfer electrode 5.

However, since the state in which the positive high voltage ■I+ and the negative voltage ■ continue to be applied to the storage electrode 38 and the transfer electrode 8, respectively, the signal charge Q31°Qs? Qs3 is sequentially transferred to the potential well below the storage electrode 38, and as shown in FIG.
), it is accumulated as a signal charge QSt. However, Qst=Qs1+Qs2+Qs3
(1).

Immediately after this, a negative voltage V and a positive high voltage II are applied to the transfer electrode 6 and the control gate 14, respectively, and this state is maintained. Therefore, the smear charge Q is subsequently transferred to the potential well below the transfer electrode 5. are sequentially discharged to the drain 15.

During the next horizontal blanking period, the address circuit 4 again selects each row of the photosensitive pixel section 2 corresponding to the next scanning line, and the transfer of signal charges from the photosensitive pixel section 2 to the vertical shift register 3 starts. be done. At the same time, a positive high voltage ■I+ is applied to the transfer electrode 8, and the signal charge Qst accumulated in the potential well below the storage electrode 38 is transferred to the horizontal shift register 1.

Before this horizontal blanking period ends, a clock pulse is applied to the horizontal shift register 1, and the signal charges QSt are transferred respectively. Then, the image output signal ■sig corresponding to the signal charge Qst is taken out from the output terminal 25 until the next horizontal blanking period.

In a conventional solid-state imaging device, when a four-phase clock pulse is applied to the vertical shift register 3 adjacent to the photosensitive pixel section 2 consisting of 500 x 400 pixels, the vertical shift register 3 receives one horizontal blanking period. 500/4 or 125 potential wells are formed and transferred. And all of these potential wells have smear charges Q
is accumulated, so that the signal charge Q8t of 1(l!!l contains a smear charge of 125Qo.On the other hand, according to this embodiment, the smear charge of 125Qo is included in one signal charge Qst. The smear charge is 3Q because the signal charge Qst is distributed and transferred to three potential wells.

So, the remaining smear electrode 1122Q is drain 15
is discharged. Therefore, according to this embodiment, compared to the conventional solid holding device, Besmir? This means that the h load has decreased to 3/125. In general, the number of potential wells transferred in one horizontal blanking period is 11, whereas if the number of potential wells transferring signal charges is N8, the smear charge included in the final signal charge Q8 is It decreases to N8/N.

In the above embodiment, the signal charges in the vertical shift register 3 are transferred using three potential wells using a four-phase clock, but as shown in FIG. 5, for example, one potential well may be used using an eight-phase clock. You may also do so.

Further, the vertical shift register and the horizontal shift register are not limited to the transfer electrode structure, the number of driving clocks, the type of signal carrier, etc., and can be selected from various types as long as they are charge transfer type shift registers.

Furthermore, in the above embodiment, the row selection by the address circuit 4 is 1.
However, the selection by the address circuit 4 is made for two rows, and the signals and smear charges for those two rows are transferred independently to the vertical shift register, so that the storage electrode can store the signal charges for two rows. It is also possible to have a configuration. In this case as well, the smear charge is controlled to be discharged to the drain. Such a configuration is extremely effective when used as a color solid-state image sensor in which color filters are provided on photosensitive pixels, as it has the advantage of reducing false signals.

Further, in the above embodiment, the selection of each row of the photosensitive pixel portions 2 by the address circuit 4 was performed during the horizontal blanking period, but it does not necessarily have to be during the horizontal blanking period.

(Effects of the Invention) As described above, according to the present invention, deterioration in image quality due to the smear phenomenon can be reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view (not showing) of a solid-state imaging device according to an embodiment of the present invention, FIG.
4 is a diagram for explaining the operation of the solid-state imaging device, and FIG. 5 is a diagram for explaining the operation of the solid-state imaging device according to another embodiment of the present invention. FIG. 6 is a plan view showing a conventional solid-state imaging device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Photosensitive pixel part, 3... Vertical shift register, 4... Address circuit, 5.6.8
゜34...Transfer electrode, 7...Storage section, 11...Horizontal shift register, 14...Control gate, 15...
Drain, 16.17..., 21...terminal, 25.
...output terminal, 29.31...p well region, 30.
32.36°37...n+ impurity region, 33...insulating layer, 35...light shield layer, 38...storage electrode, QSl, Qs2. Q33. Q85. Q8...Signal charge, Qo...Smear charge. Applicant's agent Yuo Sato 1 Figure

Claims (1)

[Claims] 1. A semiconductor substrate, a photosensitive pixel section arranged in a matrix on the semiconductor substrate and accumulating signal charges generated by incident light, and a vertical line adjacent to the photosensitive pixel section. a vertical shift register that is arranged in a shape and that separately transfers the signal charge accumulated in the photosensitive pixel portion and the injected smear charge by a transfer electrode; and a smear charge discharge means that discharges the smear charge transferred by the vertical shift register. an accumulation section that accumulates signal charges transferred by the vertical shift register; a horizontal shift register that transfers the signal charges accumulated in this accumulation section; A solid-state imaging device comprising: an output section that outputs a signal. 2. A solid-state imaging device according to claim 1, further comprising an excess charge discharge means for discharging excess charge generated in the photosensitive pixel portion due to excessive incident light. 3. The device according to claim 1 or 2, wherein the smear charge discharge means includes a discharge section containing the same carrier as the smear charge, and a discharge section for discharging charges from the transfer electrode of the vertical shift register. A solid-state imaging device characterized by having a control gate for controlling discharge to the solid-state imaging device.