JPS6276714A - Silicon wafer - Google Patents
Silicon waferInfo
- Publication number
- JPS6276714A JPS6276714A JP21720485A JP21720485A JPS6276714A JP S6276714 A JPS6276714 A JP S6276714A JP 21720485 A JP21720485 A JP 21720485A JP 21720485 A JP21720485 A JP 21720485A JP S6276714 A JPS6276714 A JP S6276714A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- density
- region
- back surface
- defects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は、シリコンウェハに係り、詳しくはウェハ表
面の汚染を極めて低下させることができるシリコンウェ
ハに関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to silicon wafers, and more particularly to silicon wafers that can significantly reduce contamination on the wafer surface.
「従来の技術」
ンリコン半導体製造工程における問題点の一つに、不純
物汚染による歩どまりの低下がある。この場合、多くの
半導体素子での電気的活性領域は、ウェハ表面から1μ
m程度以下であるから、ウェハ表面の汚染物質をウェハ
内部もしくはウェハ裏面にまで拡散させ、そこで、留め
て置くようにすれば、ウェハ表面の電気的活性領域は救
済される。``Prior Art'' One of the problems in the silicon semiconductor manufacturing process is a decrease in yield due to impurity contamination. In this case, the electrically active region in many semiconductor devices is approximately 1 μm from the wafer surface.
If the contaminants on the wafer surface are diffused into the inside of the wafer or to the back surface of the wafer and retained there, the electrically active region on the wafer surface can be rescued.
そこで、ウェハ表面の活性領域の救済のために、シリコ
ンウェハ内部またはシリコンウェハ裏面に欠陥を導入し
、これによって、ウェハ表面の活性領域(表面1um程
度の層)を浄化するゲッタリング技術が種々開発されて
いる。Therefore, in order to rescue the active region on the wafer surface, various gettering techniques have been developed in which defects are introduced inside the silicon wafer or on the backside of the silicon wafer, thereby purifying the active region on the wafer surface (a layer approximately 1 um thick on the surface). has been done.
「発明が解決しようとする問題点」
しかしながら、従来のゲッタリング技術は、ウェハ内部
に欠陥を導入する技術と、ウェハ裏面に欠陥を導入する
技術とがそれぞれ別個に存在しており、2種のゲッタリ
ング技術がありながらも両ゲッタリング技術の相乗的な
効果等に関する考察は全くなされていないのが実状であ
った。"Problems to be Solved by the Invention" However, in the conventional gettering technology, there are two separate technologies: one for introducing defects inside the wafer and the other for introducing defects on the backside of the wafer. Although there are gettering technologies, the reality is that no consideration has been given to the synergistic effects of the two gettering technologies.
この発明は、上述した事実に鑑みてなされたもので、両
ゲッタリング技術の効果を相乗的に生かし、これによっ
て、シリコンウェハ表面活性層の不純物汚染を著しく低
下させることができるシリコンウェハを提供することを
目的としている。This invention has been made in view of the above-mentioned facts, and provides a silicon wafer that can synergistically utilize the effects of both gettering techniques and thereby significantly reduce impurity contamination of the silicon wafer surface active layer. The purpose is to
「問題点を解決するための手段」
この発明は、上述した問題点を解決するために、ウェハ
表面層1μmの領域では酸素析出物の密度がI08個/
am’より少なく、また、ウェハ表面下1μmより深い
領域では酸素析出物の密度が108個/cff13以上
となるようにし、かつ、ウェハ裏面に108個/cI1
12以上の密度で、大きさが0.5μm以上の転位集合
体を導入するようにしている。"Means for Solving the Problems" In order to solve the above-mentioned problems, the present invention aims to solve the above-mentioned problems by reducing the density of oxygen precipitates to 1 μm in the wafer surface layer.
am', and the density of oxygen precipitates is 108/cff13 or more in a region deeper than 1 μm below the wafer surface, and 108/cff13 or more on the back surface of the wafer.
Dislocation aggregates with a density of 12 or more and a size of 0.5 μm or more are introduced.
「作用」
ウェハ表面下1μmより深いところにある内部欠陥と、
ウェハ裏面の転位集合体による不純物吸収効果が加え合
わされ、これにより、極めて高い不純物吸収効果が得ら
れる。"Operation" Internal defects located deeper than 1 μm below the wafer surface,
This is combined with the impurity absorption effect due to the dislocation aggregates on the back surface of the wafer, resulting in an extremely high impurity absorption effect.
「実施例」 以下、この発明の実施例について説明する。"Example" Examples of the present invention will be described below.
まず、ウェハ裏面にどのような不純物吸収活性点を導入
すれば、内部の不純物吸収活性点に適合して双方の不純
物吸収効果を生かすことができるかを、種々の条件の組
み合わせにより実験した。First, we conducted experiments using various combinations of conditions to determine what kind of impurity-absorbing active sites should be introduced on the backside of the wafer to match the internal impurity-absorbing active sites and take advantage of the impurity-absorbing effects of both.
そして、この実験の結果、ウェハ裏面には、転位集合体
を導入するのが最も安定した活性点となることが判った
。As a result of this experiment, it was found that introducing dislocation aggregates into the back surface of the wafer provides the most stable active points.
したがって、組み合せ熱処理によってウェハ内部に酸化
物起因の欠陥を導入し、その後に、室温で微粒子粉末を
ウェハ裏面に吹き付けることによりマイクロクラックを
生じさせ、さらに、650℃以上に加熱してウェハ裏面
に高密度の転位集合体を導入したウェハを作成し、この
ウェハについて種々の条件を変えながら、不純物ゲッタ
リングの効果について以下に述べる実験を行った。Therefore, defects caused by oxides are introduced inside the wafer through a combination heat treatment, and then micro-cracks are generated by spraying fine particle powder onto the backside of the wafer at room temperature, and then microcracks are generated on the backside of the wafer by heating to over 650°C. A wafer with a high density of dislocation aggregates introduced was prepared, and the following experiments were conducted to examine the effect of impurity gettering while changing various conditions on this wafer.
(1)始めに、裏面に転位集合体がある場合とない場合
とのゲッタリング効果の違いを調べた。(1) First, we investigated the difference in gettering effect between when there is a dislocation aggregate on the back surface and when there is no dislocation aggregate.
まず、シリコンウェハ内部に酸化物起因の欠陥を導入す
る処理を行うために、1100℃で2゜5時間の熱処理
の後に、900℃で2時間加熱し、さらに、1050℃
で10時間加熱した。そして、上記熱処理を終了したシ
リコンウェハの欠陥導入情況を調べるために、シリコン
ウェハの一部をへき開し、このへき開部の断面に対し選
択エツチングを行い、エツチング後の断面情況を光学顕
微鏡で調べた。この結果、表面から21μmの深さまで
は欠陥は観察されなかったが、21μmより深い位置に
おいては2.4X 10”個/am’の欠陥が観察でき
た。また一方において、上記シリコンウェハに対し透過
電子顕微鏡による観察を行ったところ、ウェハ表面から
1μmの深さの位置までは欠陥が全く観察されなかった
。この場合、透過電子顕微鏡によって観察し得る欠陥の
密度は、108個/ca+’程度が限界であるから、上
記シリコンウェハの表面から1μmまでの位置における
欠陥は、io@1llW/am’以下の密度であること
が判る。First, in order to introduce defects caused by oxides into the silicon wafer, it was heat treated at 1100°C for 2.5 hours, then heated at 900°C for 2 hours, and then heated at 1050°C.
The mixture was heated for 10 hours. Then, in order to investigate the state of defect introduction in the silicon wafer that had undergone the above heat treatment, a part of the silicon wafer was cleaved, selective etching was performed on the cross section of this cleavage, and the state of the cross section after etching was examined using an optical microscope. . As a result, no defects were observed up to a depth of 21 μm from the surface, but 2.4×10” defects/am’ were observed at positions deeper than 21 μm. When observed using an electron microscope, no defects were observed at a depth of 1 μm from the wafer surface.In this case, the density of defects that could be observed using a transmission electron microscope was approximately 108 defects/ca+'. Since this is the limit, it can be seen that the density of defects at a position up to 1 μm from the surface of the silicon wafer is less than io@1llW/am'.
次に、ウェハ裏面に打痕を与えるために、微粒子シリカ
を高速度で打ち付け、これにより、マイクロクラックを
生じさせた。そして、このウェハを950℃に加熱する
ことにより、マイクロクラックから高密度の転位集合体
を発生させた。この場合に発生した転位集合体は、大き
さが0.5μm以上上述のようにして作成されたウェハ
と裏面に転位集合体の無いウェハのゲッタリング効果の
測定結果を以下に説明する。Next, fine silica particles were struck at high speed to create dents on the back surface of the wafer, thereby creating microcracks. Then, by heating this wafer to 950° C., high-density dislocation aggregates were generated from the microcracks. The size of the dislocation aggregates generated in this case is 0.5 μm or more.The measurement results of the gettering effect of the wafer prepared as described above and the wafer having no dislocation aggregates on the back surface will be described below.
この場合の測定としては、ゲッタリング効果を敏感に反
映する酸化膜耐圧と少数キャリアのライフタイムの測定
を採用した。In this case, measurements were taken to measure the oxide film breakdown voltage and minority carrier lifetime, which sensitively reflect the gettering effect.
まず、測定を行うために、ウェハ表面を酸化させてAI
(アルミニウム)電極付けを行い、MOSキャパシタを
作成した。そして、前記電極を介して電圧を印加した際
におけるリーク電流の値が、1G−5Aに達した時点の
印加電圧値を酸化膜耐圧とし、また、印加電圧を逆転し
た際の容量上昇の速さく過渡特性)からライフタイムの
測定を行った。First, in order to perform measurements, the wafer surface is oxidized and AI
(Aluminum) electrodes were attached to create a MOS capacitor. Then, the applied voltage value at the time when the leakage current value reaches 1G-5A when voltage is applied through the electrode is defined as the oxide film breakdown voltage, and the rate of capacitance increase when the applied voltage is reversed is determined. The lifetime was measured from the transient characteristics).
この測定結果は、第1表に示すようになった。The measurement results are shown in Table 1.
そして、第1表から判るように、裏面に転位集合体があ
るウェハは、裏面に転位集合体を導入していないウェハ
に比べて酸化膜耐圧が高く、また、ライフタイムも長な
り、ゲッタリング効果が良いことが確認された。As can be seen from Table 1, wafers with dislocation aggregates on the back side have a higher oxide film breakdown voltage and longer lifetime than wafers without dislocation aggregates on the back side, and gettering It was confirmed that the effect was good.
ままで、裏面の転位集合体の導入の程度を変化させた場
合のゲッタリング効果の違いを説明する。The difference in gettering effect when the degree of introduction of dislocation aggregates on the back surface is changed will be explained.
まず、内部欠陥を作るための熱処理を、1100℃で2
.5時間加熱し、その後に550℃から950°Cまで
毎分1°Cずつ昇温し、さらに、950℃で10分間保
持した後に降温した。この結果、ウェハ表面層1μmの
領域では透過電子顕微鏡で観察しても欠陥は観察されな
かったが、表面下1μmより深い領域では約106個/
cm3の酸化物が観察された。First, heat treatment to create internal defects was performed at 1100℃ for 2 hours.
.. After heating for 5 hours, the temperature was raised from 550°C to 950°C at a rate of 1°C per minute, and after being held at 950°C for 10 minutes, the temperature was lowered. As a result, no defects were observed in the 1 μm region of the wafer surface layer when observed using a transmission electron microscope, but about 106 defects/defects were observed in the region deeper than 1 μm below the surface.
cm3 of oxide was observed.
次に、ウェハ裏面の転位集合体密度が異なるサンプルを
作成するために、微粒子シリカの打ち付は時間を変えた
ウェハを2種作成した。そして、これらのウェハを90
0°Cに加熱して裏面に転位集合体を発生させたところ
、一方のウェハには105個/am”の密度で、また、
他方のウェハには107個/cm2の密度で転位集合体
が発生していた。この場合、転位集合体の大きさは、ど
ちらも0.5μm以上であった。そして、これらのウェ
ハに対し酸化膜耐圧を測定した結果、第2表に示すよう
になり、この表から判るように転位集合体の密度が10
7個/am’の方はゲッタリング効果が著しく酸化膜耐
圧か高くなっているが、密度が105個/cm2の方は
耐圧が低くそのゲッタリング効果が低いことが観察され
た。この場合、さらに実験を重ねた結果、ウェハ裏面の
転位集合体の密度がlO’(Ii!I/c+n’以上と
なったときに、ゲッタリング効果が昔しくなることが認
められた。Next, in order to create samples with different dislocation aggregate densities on the backside of the wafer, two types of wafers were created in which the fine-particle silica was applied for different times. Then, these wafers were
When heated to 0°C to generate dislocation aggregates on the backside, one wafer had a density of 105/am'';
In the other wafer, dislocation aggregates were generated at a density of 107 pieces/cm2. In this case, the size of the dislocation aggregates was 0.5 μm or more in both cases. The results of measuring the oxide film breakdown voltage of these wafers are shown in Table 2, and as can be seen from this table, the density of dislocation aggregates is 10
It was observed that when the density was 7 pieces/am', the gettering effect was remarkable and the oxide film breakdown voltage was high, but when the density was 10 5 pieces/cm 2 , the breakdown voltage was low and the gettering effect was low. In this case, as a result of further experiments, it was found that the gettering effect becomes obsolete when the density of dislocation aggregates on the back surface of the wafer becomes equal to or higher than lO'(Ii!I/c+n').
ここで、上記(1)、(2)の実験結果をまとめると、
ウェハ内部に欠陥を導入した場合であってら、裏面には
転位集合体を導入した方がゲッタリング効果が良く、ま
た、この際に裏面に導入する転位集合体は大きさが0.
5μm以上で、密度が106個/Cm2以上であること
が良好なゲッタリング効果を得るための必要条件となる
。Here, to summarize the experimental results of (1) and (2) above,
Even if defects are introduced inside the wafer, the gettering effect is better if dislocation aggregates are introduced to the back surface, and the size of the dislocation aggregates introduced to the back surface is 0.
The necessary conditions for obtaining a good gettering effect are that the diameter is 5 μm or more and the density is 10 6 pieces/Cm 2 or more.
(3)次に、内部欠陥の分布情況とゲッタリング効果の
関係について説明する。(3) Next, the relationship between the distribution of internal defects and the gettering effect will be explained.
まず、ウェハ表面下から1μmの領域に透過電子顕微鏡
で観察し得る酸化物が10I0個/am’程度以上存在
するウェハで、裏面の転位集合体が7×105fJJ/
cm2の密度のものと、10”f[!II/cm2以上
の密度のものとの2種のサンプルを作成するとともに、
ウェハ表下20μmの領域には欠陥がなく、それ以下の
領域には上記サンプルと同様の密度で酸化物が存在し、
かつ、裏面の転位集合体の密度が106個/cm”以上
のサンプルを作成した。そして、これらについて酸化膜
耐圧を測定した結果、第3表に示すようになった。この
表から判るように、内部欠陥が表面近傍(表面下1μm
)にまで分布しているものは、表面近傍に欠陥のないも
のに比べて酸化膜耐圧が低く、ゲッタリング効果が劣っ
ている。また、実験を重ねた結果、表面下1μmより欠
陥があっても表面下1μmのところに欠陥がなければゲ
ッタリング効果は良好であり、さらに、表面下20μm
までの領域に欠陥がなく、それより深い領域にのみ欠陥
があるウェハについては、より良いゲッタリング効果が
あることが確認された。First, for a wafer in which there are approximately 10I0/am' or more of oxides that can be observed with a transmission electron microscope in a region of 1 μm from the bottom of the wafer surface, the number of dislocation aggregates on the back surface is 7×105fJJ/
Two types of samples were created, one with a density of cm2 and one with a density of 10"f[!II/cm2 or more, and
There are no defects in the area 20 μm below the wafer surface, and oxides exist in the area below that at a density similar to that of the sample above.
In addition, samples were prepared in which the density of dislocation aggregates on the back surface was 106 pieces/cm" or higher.The oxide film breakdown voltage of these samples was measured, and the results are shown in Table 3.As can be seen from this table, , internal defects are near the surface (1 μm below the surface)
), the oxide film breakdown voltage is lower than that with no defects near the surface, and the gettering effect is inferior. In addition, as a result of repeated experiments, even if there is a defect 1 μm below the surface, the gettering effect is good as long as there is no defect 1 μm below the surface.
It was confirmed that wafers with no defects in the region up to the point where the gettering effect is better for wafers with defects only in the deeper region.
また、ウェハ内部には、106個/cm3以上の密度の
酸素析出物があれば、内部欠陥によるゲッタリング効果
は充分であることが測定された。Furthermore, it has been determined that if there are oxygen precipitates with a density of 106 particles/cm3 or more inside the wafer, the gettering effect due to internal defects is sufficient.
以上の測定結果をまとめると、ウェハの表面下1μmの
領域では酸素析出物が個/cm3より少ない(透過電子
顕微鏡で観察し得ない)密度となり、表面下1μmより
深い領域では酸素析出物が108個/cm3以上の密度
となり、さらに、ウェハ裏面には大きさが0.5μm以
上の転位集合体が106個7cm2以上の密度で導入さ
れていることが、良好なゲッタリング効果を得る条件と
なる。To summarize the above measurement results, the density of oxygen precipitates is less than 1 μm/cm3 (unobservable with a transmission electron microscope) in the region 1 μm below the surface of the wafer, and the density of oxygen precipitates is less than 108 cm3 in the region deeper than 1 μm below the surface. The conditions for obtaining a good gettering effect are that the density is 106 pieces/cm3 or more, and that 106 dislocation aggregates with a size of 0.5 μm or more are introduced on the back surface of the wafer at a density of 7 cm2 or more. .
「発明の効果」
以上説明したように、この発明によれば、ウェハ表面層
1μmの領域では酸素析出物の密度が106個/cm3
より少なく、また、ウェハ表面下lJ、Lmより深い領
域では酸素析出物の密度が106個/cm3以上となる
ようにし、かつ、ウェハ裏面に106個/Cm2以上の
密度で、大きさが0.5μm以上の転位集合体を導入し
たので、ウェハ内部およびウェハ裏面の両ゲックリング
効果を相乗的に生かし、これによって、シリコンウェハ
表面活性層の不純物汚染を著しく低下させることができ
る利点が得られる。"Effects of the Invention" As explained above, according to the present invention, the density of oxygen precipitates is 106 particles/cm3 in a 1 μm area of the wafer surface layer.
In addition, the density of oxygen precipitates should be 106/cm3 or more in the region deeper than lJ, Lm below the wafer surface, and the density of oxygen precipitates should be 106/cm2 or more on the back surface of the wafer, and the size should be 0. Since dislocation aggregates of 5 μm or more are introduced, the Geckling effects both inside the wafer and on the back surface of the wafer are synergistically utilized, thereby providing the advantage of significantly reducing impurity contamination of the silicon wafer surface active layer.
Claims (1)
^6個/cm^3より少なく、また、ウェハ表面下1μ
mより深い領域では酸素析出物の密度が10^6個/c
m^3以上となるようにし、かつ、ウェハ裏面に10^
6個/cm^2以上の密度で、大きさが0.5μm以上
の転位集合体を導入したことを特徴とするシリコンウェ
ハ。In the 1 μm area of the wafer surface layer, the density of oxygen precipitates is 10
Less than ^6 pieces/cm^3, and 1μ below the wafer surface
In the region deeper than m, the density of oxygen precipitates is 10^6/c
m^3 or more, and 10^ on the back side of the wafer.
A silicon wafer characterized in that dislocation aggregates having a density of 6 pieces/cm^2 or more and a size of 0.5 μm or more are introduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21720485A JPS6276714A (en) | 1985-09-30 | 1985-09-30 | Silicon wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21720485A JPS6276714A (en) | 1985-09-30 | 1985-09-30 | Silicon wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6276714A true JPS6276714A (en) | 1987-04-08 |
Family
ID=16700496
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21720485A Pending JPS6276714A (en) | 1985-09-30 | 1985-09-30 | Silicon wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6276714A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5389551A (en) * | 1991-02-21 | 1995-02-14 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor substrate |
US5506154A (en) * | 1990-09-14 | 1996-04-09 | Komatsu Electronic Metals Co., Ltd. | Process for preheat treatment of semiconductor wafers |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51107066A (en) * | 1975-03-17 | 1976-09-22 | New Nippon Electric Co | Handotaisochino seizohoho |
JPS5627940A (en) * | 1979-08-14 | 1981-03-18 | Fujitsu Ltd | Manufacture of semiconductor elements |
JPS586140A (en) * | 1981-07-03 | 1983-01-13 | Nec Corp | Manufacture of silicon wafer |
JPS6047426A (en) * | 1983-08-26 | 1985-03-14 | Komatsu Denshi Kinzoku Kk | Bsd-imparted semiconductor substrate |
-
1985
- 1985-09-30 JP JP21720485A patent/JPS6276714A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51107066A (en) * | 1975-03-17 | 1976-09-22 | New Nippon Electric Co | Handotaisochino seizohoho |
JPS5627940A (en) * | 1979-08-14 | 1981-03-18 | Fujitsu Ltd | Manufacture of semiconductor elements |
JPS586140A (en) * | 1981-07-03 | 1983-01-13 | Nec Corp | Manufacture of silicon wafer |
JPS6047426A (en) * | 1983-08-26 | 1985-03-14 | Komatsu Denshi Kinzoku Kk | Bsd-imparted semiconductor substrate |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5506154A (en) * | 1990-09-14 | 1996-04-09 | Komatsu Electronic Metals Co., Ltd. | Process for preheat treatment of semiconductor wafers |
US5389551A (en) * | 1991-02-21 | 1995-02-14 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor substrate |
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