JPS6276320A - Logic circuit - Google Patents

Abstract

PURPOSE:To suppress a through-current by providing an N type transistor (TR) whose gate and drain are connected between P type the 1st TR and N type the 2nd TR. CONSTITUTION:When the gate input signals of TRs QP1, QN1 changes from an H level to an L level, the potential of a gate S2 is a potential lower by the threshold value of the TR QN1 than the potential of the gate S1. When the signal S changes from an L level to an H level, the potential change of the gate S2 is faster than that of the gate S1, and since the timing when the TR QN2 is turned on by the gate S2 is faster than the timing when the TR QP2 is turned on by the gate S1, the time of simultaneous-on is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit, and particularly to a logic circuit in which through-current is suppressed.

[Conventional technology]

A conventional logic circuit has a transistor of one conductivity type (in this example, P
type enhancement transistor) QPl QP
□ and transistors of opposite conductivity type (in this example, N-type enhancement transistors) QN1QN2 are connected in series, and inverters are further connected in series.

[Problem that the invention seeks to solve]

Considering the above-mentioned conventional logic theory DC delta masterpiece,
Regardless of whether the input signal S is at the l )4 W level or the l L level, one of the transistors Q and QN1 and one of the transistors Qr'2 and QN2 are always in the off state, and the power supply VDD Since there is no DC path between the terminal and the ground terminal GND, no power supply current flows.

Considering AC-like operation, the input signal S is 1) 1"
From level to I L level or "Ll level to 1H
When the voltage changes to the level, the output S3 of the transistors Q, QN, becomes an intermediate level that is neither the IHI level nor the IILl level, so the transistors QP□ and QN2 are simultaneously turned on, and the voltage between the power supply "DD" and the ground terminal GND is The through current flows in a pulsed manner.

As shown in FIG. 5, there is a pulsed through current ■ between the power supply vDD and the ground terminal GND. The flow of N causes noise in the power supply vDD, ``!J, and ground terminal GND, causing malfunction of the circuit.Also, there is a drawback that power consumption increases.

An object of the present invention is to provide an embedded circuit that suppresses through current, thereby reducing noise and reducing electricity costs.

[f the problem! 6. Means for deciding] of the present invention;
A circuit is also connected in series between the loose rhinoceros and the ground terminal; a first transistor of the conductivity type, a second transistor of the opposite conductivity type, and a storm protection circuit. A logic circuit including a third transistor of one conductivity type and a fourth transistor of the opposite conductivity type connected in series between a terminal and a ground terminal and in parallel to the first and second transistors,
The source and drain of a fifth transistor whose gate and drain are connected are connected between the first transistor and the second transistor, and the source and drain of the fifth transistor are connected to the third and drain transistors, respectively. This is connected to the gate of transistor No. 4.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The circuit of this embodiment differs from the conventional circuit shown in FIG. 4 in that it is an N-type transistor whose gate and drain are connected between a P-type first transistor QP , the gate S7 of the fifth transistor QN3 is connected to the gate of the P-type third transistor QP□, and the source of the second transistor QN□ is connected to the N-type fourth transistor QN2. It is connected to gate S.

The gate input signal S of transistors QP□ and QN□ is “
When changing from the Hal level to the IL level, the potential of the gate S is higher than that of the first transistor Q with respect to the potential of the gate SI.
The threshold voltage of N-type ■ t11 is a low potential, so A
From a C point of view, the change in potential of the gate S lags behind that of the gate Sl. Therefore, the timing at which the fourth transistor QN2 is turned on by the gate S is delayed by the timing at which the third transistor Qp2 is turned off by the gate S, and as a result, the timing at which the fourth transistor QN2 is turned on by the gate S is delayed by . The time t when the state is simultaneously turned on. N
I2 becomes shorter.

Input 4R"5S changes from "■, level to "1-16 level" (In AC terms, the potential change of gate S2 is faster than gates S and V, Since the timing when transistors Q1 and Q2 are turned off is earlier than the timing when transistors Q1 and Q2 are turned on due to gate SI, t.N is similarly shortened. Therefore, the through current IoN flowing during ton
becomes extremely small.

The AC timing deviation of the signals divided into gates S and S2 is the difference between gates S and 8. Since the rising time tr and the falling time tf of the signal are approximately equal to each other, the operating speed of the logic circuit does not decrease at all.

In terms of DC, one of the transistors QP□ and QN2 has a gate of 1-8. ．． Since it is always in the off state in either S,
DC operation is the same as a conventional logic circuit. .

In the above embodiment, an N-type transistor is used as the fifth transistor QN3, but even if a P-type transistor is used, the
It goes without saying that the present invention can be applied in the same way (8.

FIG. 2 (1) is a circuit diagram of a second embodiment of the present invention.

This second embodiment has a structure in which the transistors QP2QN2 are not directly connected, but have their gates and drains connected via an N-type transistor QN4'ff. As a result, as mentioned above, the signal 01 whose timing is shifted
0. is obtained as the output, so by connecting this circuit, you can create a through current. , it is possible to obtain a large-scale logic circuit that suppresses .

〔Effect of the invention〕

As described above, according to the present invention, the through current I can be reduced without reducing the operating speed. A logic circuit that is effective in suppressing N can be obtained.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing the first and second embodiments of the present invention, respectively, FIG. 3 is a waveform diagram for explaining the operation of the first embodiment of the present invention, and FIG. 4 5 is a circuit diagram showing an example of a conventional logic circuit, and FIG. 5 is a waveform diagram for explaining the operation of the circuit shown in FIG. 4. GND...Ground terminal, IoN...Through current, 01゜0,...Output signal, QNII Q
N2P QN3# QN4 ゛°゛°゛Nu enhancement transistor, QP! QP□・・・・・・Pm
Enhancement fist transistor, s, s'...
・Input signal, S1+ s, l s, -...-gate, ton...conduction time of both transistors, vDD・
·····power supply. Figure 4 Time T Time bottom

Claims (1)

[Claims] A first transistor of one conductivity type and a second transistor of the opposite conductivity type are connected in series between the power supply terminal and the ground terminal, and the first transistor is connected in series between the power supply terminal and the ground terminal.
and a logic circuit including a third transistor of one conductivity type and a fourth transistor of the opposite conductivity type connected in parallel to the second transistor, the source and drain of the fifth transistor whose gate and drain are connected. is connected between the first transistor and the second transistor, and the source and drain of the fifth transistor are connected to the gates of the third and fourth transistors, respectively. .