JPS6275997A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To effectively transfer the information between an FF and a memory part by constituting a RAM by a flip-flop when constituting a memory device by a memory unit consisting of a static type RAM and a non-volatile memory part and controlling an impressing voltage to a transistor of a constituting element. CONSTITUTION:In an operation as a static RAM, a store signal impressed to a control gate of the fist and the second switching transistors T7 and T8 and a recall signal impressed to a control gate of the third transistor T9 are set respectively at low levels and a non-volatile memory part is separated from an FF circuit. The transfer of the data stored in a memory part to the FF circuit is carried out by raising a power source potential to a prescribed potential again after a store terminal is kept at a low potential, a high potential is impressed to a recall terminal and the power source potential VDD is lowered once at the low potential under this state. The transmission of the information from a capacitor C to the transistor T9 is carried out by using complementary type transistors T10 and T11 and an operation condition of the FF circuit is set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device having the functions of both a static RAM and a nonvolatile memory.

[Technical background of the invention and its problems]

Memory LSIs, which are storage devices using semiconductors, are making rapid progress. In particular, static memory is widely used in various devices because information can be easily rewritten and accessed at high speed. However, it has the disadvantage that the stored information is lost when the power is turned off.

On the other hand, EPRO is a non-volatile semiconductor memory device whose stored information is not lost even when the power is turned off.
M, EEPRO'M, etc. have been developed. However, this type of nonvolatile memory has drawbacks such as requiring a longer time to write (rewrite) information than to read information, and furthermore, there is a limit to the number of times information can be rewritten.

Therefore, a non-volatile RAM (NORAM) has been developed that compensates for these shortcomings and takes advantage of their strengths.

This device can be used, for example, as shown in FIG.
A flip-flop, which is a basic cell of AM, is made up of four transistors tl, t2. t3. The output terminal is connected to the bit line D via switching transistors t5 and t6, respectively.

A floating type transistor t8 that provides non-volatility is connected to one output terminal of the flip-flop through a switching transistor t7, and a switching l-run raster t9 for clearing the stored information is connected to this transistor t8. configured.

However, in a storage device configured in this manner, the storage operation as a static RAM is normally performed in the flip-flop section. When transferring the stored information to the nonvolatile memory section, first the transistor t7
．． Each gate potential (CLR, PRO) at t8 is lowered to the ground potential, and a high voltage is applied to the CLR terminal of transistor t9. In this state, after clearing each nonvolatile transistor t8 of all cells, this is performed by applying a VDD potential to the CLR terminal and a high potential to the PRO terminal.

As a result, when node b of flip 70 is at a low level, node d, which has been kept at a high potential, is connected to transistor t7. Discharge occurs through t8, and electron injection occurs into the floating gate of non-volatile transistor t8.

Further, when the node b of the flip-flop is at a high level, the transistor t7 is off, so the node d is kept at a high potential, and the nonvolatile transistor t8 is at a high potential.
- No injection of electrons into the timing gate occurs.

The information stored in the flip-flop in this way is transferred to the nonvolatile transistor t8 by controlling the injection of electrons into the 70-ting gate of the nonvolatile transistor t8.
8 (non-volatile memory section).

On the other hand, the information stored in this non-volatile memory section is
This is performed by lowering the power supply potential of the flip-flop 70 from VDD to the ground potential, and then returning it to the power supply potential VDD, with the CLK terminal, PRO terminal, and CLR terminal each held at a high level. Transistor t1. of the flip-flop section. t2 is designed to have unbalance, and when the nonvolatile transistor t8 is in an off state due to electrons being injected into its 70-ring gate, it returns to the state determined by its original unbalance. . On the other hand, when the nonvolatile transistor t8 is in the on state, the original load imbalance is reversed and the reverse storage state is restored.

In this way, the information stored in the non-volatile transistor t8 is transferred to the flip-flop section 70, and the flip-flop section returns to the state before the power was turned off.

However, in a storage device configured in this way, in order to transfer the information, the above-mentioned VDI-), CLK, P
It is necessary to control each of the four terminal potentials of RO and CLR from the outside.

However, in a semiconductor memory device constructed by arranging a large number of memory cells having the above-described structure in a matrix, the wiring structure for controlling each of the potentials described above becomes complicated. This has been a major hindrance in achieving high-density integration.

Also, in order to keep the node d at a high potential, the transistor t7
．． It is necessary to separate node d by t9 and keep it floating. However, there are problems such as junction leakage and bunch through in the semiconductor substrate, and there are problems in always correctly transferring information.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its purpose is to provide a system suitable for high-density integration and capable of stably and reliable information transfer between the flip-flop section and the nonvolatile memory section. An object of the present invention is to provide a semiconductor memory device.

[Summary of the invention]

The present invention provides a static memory device formed on a semiconductor substrate by cross-connecting the input and output terminals of two sets of transistor inverter circuits consisting of a drive transistor constituted by an MIS type transistor and a load transistor. A floating gate formed on the semiconductor substrate includes a non-volatile memory section formed of a flip-flop circuit formed on the semiconductor substrate and forming a pair with the static storage device to form one memory cell. between two electrodes capacitively coupled to each other and connected to each output terminal of the flip-flop circuit via first and second switching transistors, and the floating gate as a gate, and between the power supply of the flip-flop circuit. It is characterized by comprising a pair of complementary transistors connected in series, and a third switching transistor connected between a common connection point of the pair of complementary transistors and one output end of the flip-flop circuit. It is something to do.

〔Effect of the invention〕

Thus, according to the present invention, the connection between the flip-flop section and the nonvolatile memory section can be achieved by simply controlling the voltages applied to the control terminals of the first and second transistors and the control terminal of the third transistor, and controlling the power supply voltage. It becomes possible to reliably transfer information between the two, and problems such as the aforementioned joint leakage are no longer caused.

Therefore, in addition to ensuring reliable operation, great practical effects such as facilitating high-density integration can be achieved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an electrical circuit configuration diagram of an embodiment device, showing the configuration of one memory cell formed on a semiconductor substrate.

Transistor T3, which has transistors TI and T2 as loads, respectively. A pair of inverter circuits constituted by T4 have their input and output terminals cross-connected to constitute a flip-flop circuit.

And the two output terminals are each connected to a transistor T5.
．． It is connected to the bit line D via T6 and constitutes one unit cell in the static RAM. This configuration is completely the same as the basic configuration of the conventional type -0- shown in FIG.

On the other hand, the nonvolatile memory section paired with the flip-flop circuit is configured as follows.

A capacitor C formed in a semiconductor substrate has a floating gate structure, and its electrodes are connected to the first and second gates.
are connected to each output terminal of the flip-flop circuit through switching transistors T7 and T8. Further, the gate of the capacitor C is connected to a pair of complementary transistors T10. connected in series between the power supplies of the flip-flop circuit. Connected to each gate of Tit. And this pair of complementary transistors T
A switching transistor T9 is connected between the common connection point of the 10° T11 and one output terminal of the flip-flop circuit, here the output terminal of the transistor T4.

These constitute a nonvolatile memory section using the capacitor C as a nonvolatile memory element.

Specifically, the capacitor C with the floating gate has a second
As shown in Figure (a), for example, A
n-type high concentration impurity lI formed by doping with s ions
A floating gate is made of polycrystalline silicon 4 formed through a thin silicon oxide film 3 of about 100 layers on top of 2, and a control layer made of polycrystalline silicon is formed through a silicon oxide film formed by oxidizing this polycrystalline silicon. It is configured by forming a gate 5.

At this time, the transistors TIO and T11 are connected to each other as shown in FIG.
b) formed on the same p-type silicon substrate 1.
P-type transistors and p-type transistors having a common floating gate 8 are formed on the type well 6 and the surface of the silicon substrate 1 through a gate oxide film 7 forming a part of silicon oxide l113.

Note that this floating gate 8 is formed as an extension of the polycrystalline silicon 4. It goes without saying that other transistors are similarly formed on the same p-type silicon substrate 1.

Incidentally, the capacitor C is formed by, for example, polycrystalline silicon 9 formed on a field oxide film (silicon oxide film) 3 on a p-type silicon substrate 1, and on the top thereof, as shown in FIG. 2(C). 10. Floating gate made of crystalline silicon. Further, another electrode 11 is formed on top of the electrode 11.
It is also possible to configure by

According to the present device configured in this manner, its operation as a static RAM is performed by the first and second switching transistors T7. This is done by setting the 5TORE signal applied to the control gate of T8 and the RECALL signal applied to the control gate of the third switching transistor T9 to a low level, thereby disconnecting the non-volatile memory section from the 7 lip-flop circuit.

When the information stored in the flip-flop section is to be transferred to the nonvolatile memory section, first, the power supply voltage VDD is raised to a high potential, a high potential is applied to the 5TORE terminal, and the transistor T7. Make each T8 conductive. At this time, the RECALL terminal of the transistor T9 is kept at a low potential. As a result, the floating gate type capacitor C is connected to the transistor T7, depending on the information storage state of the flip-flop circuit. A high or low potential is applied through T8.

When the potential on the electrode side connected to the transistor T7 is high, injection of electrons into the floating gate occurs due to a tunnel current, and electron emission occurs on the electrode side connected to the transistor T8.

Further, when the potential on the transistor TI side is low, no injection of electrons into the floating gate occurs. In this way, data of the flip-flop circuit is transferred depending on whether electrons are injected into the floating gate of the capacitor C, and the information is stored and held in the floating gate of the capacitor C.

On the other hand, the data stored in the nonvolatile memory section is transferred to the seven flip-flop circuits as follows.

This data transfer is performed by the transistor T7. While keeping the 5TORE terminal for T8 at a low potential, a high potential is applied to the RE CA L L terminal of the transistor T9, and in this state, the power supply potential VDD is temporarily lowered to a low potential, and then,
This is done by raising the potential to a predetermined level again.

In this way, from capacitor C to transistor T9
As mentioned above, the means for transmitting information to the complementary transistor T10. Since the transistor T11 is configured by the transistor T11, when electrons are injected into the floating gate of the capacitor C, only the p-channel transistor T10 becomes conductive.

As a result, a high potential is applied to the gate of the inverter circuit constituted by the transistors TI and T3 via the transistors T10 and T9, and the operating state of the flip-flop circuit is uniquely set.

Further, when no electrons are injected into the floating gate of the capacitor C, only the transistor T11 becomes conductive, and the gate potential of the inverter circuit constituted by the transistors TI and T3 changes from the transistor T9. It is pulled to a low potential through T11. As a result, the flip-flop circuit is set to the opposite state from the previous state.

The information stored in the nonvolatile memory section in this way is
The data is transferred to the flip-flop circuit, and the flip-flop circuit section returns to its original state.

In this way, according to this device, data transfer between the flip-flop circuit section and the nonvolatile memory section can be reliably controlled only by controlling the power supply potential VDD and controlling the voltage application to the 5TORE 1 child and the RECALL terminal. I can do it. Therefore, compared to the conventional device shown in FIG. 3, the number of control signal lines can be reduced by one, which greatly contributes to high-density integration. Further, the application of control signals during the information transfer is easily controlled, and the configuration of the peripheral circuits can be simplified.

Furthermore, according to the above-described configuration, each node of the circuit does not become in a floating state during its operation, so problems that occur with conventional devices do not occur, and stable operation can be ensured. . Furthermore, since the cell structure can be made symmetrical in terms of the element structure, it is possible to achieve great practical effects such as widening the margin against variations caused by process variations.

It should be noted that the present invention is not limited to the embodiments described above, and the structure of the capacitor C having a floating gate may be determined according to its specifications.

In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of each memory cell in an embodiment of the present invention, FIG. 2 is a diagram showing the element structure of the embodiment device, and FIG. 3 is a diagram showing the configuration of each memory cell of a conventional device. It is. C...Capacitor with floating gate, TI, T2゜T
3. T4...transistor (flip-flop circuit), T7. T8. T9...Switching transistor, TIO, T11...Complementary transistor. Applicant's agent Patent attorney Takehiko Suzue Vo. Figure 1 Figure 2

Claims (4)

[Claims] (1) A semiconductor memory device in which a memory unit composed of a static memory device and a nonvolatile memory section is formed on a semiconductor substrate, where the static memory device is composed of MIS type transistors. The non-volatile memory section is composed of a flip-flop circuit formed by cross-connecting input and output terminals of two sets of transistor inverter circuits consisting of a drive transistor and a load transistor, and the non-volatile memory section is a floating transistor formed on the semiconductor substrate. between two electrodes capacitively coupled to the gate and connected to each output terminal of the flip-flop circuit via first and second switching transistors, and the floating gate as the gate, and the power supply of the flip-flop circuit. and a third switching transistor connected between a common connection point of the complementary transistor pair and one output end of the flip-flop circuit. semiconductor storage device. (2) The first and second switching transistors are
The semiconductor memory device according to claim 1, which is driven on and off at the same time. (3) The floating gate is made of polycrystalline silicon, and the two electrodes capacitively coupled to the floating gate are a high concentration impurity region of opposite conductivity type formed in the semiconductor substrate and a polycrystalline silicon layer stacked on the floating gate. The semiconductor memory device according to claim 1, characterized in that it is made of crystalline silicon. (4) The semiconductor memory device according to claim 1, wherein the floating gate and the two electrodes capacitively coupled to the floating gate are each made of polycrystalline silicon.