JPS6274349A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an ultrasonic diagnostic apparatus that displays ultrasonic images based on radial scan ζ.

[Technical background of the invention and its problems] [1.] The image display method in conventional ultrasonic diagnostic equipment that performs radial scanning uses an X-Y monitor and displays analog X, Y coordinates and Images were displayed by setting brightness signals and sweeping them. Such image display methods have problems such as the rasters being displayed at a distance from each other, the displayed image being difficult to see if the sweep time is slow, and the display image being difficult to freeze (still).

On the other hand, an ultrasound diagnostic device that displays ultrasound images by sector scanning uses DSC (Digital 5can).
A method is adopted in which scan data converted into a digital signal by a converter circuit is written into a storage means (frame memory) in the same vector as the ultrasonic raster, and this is read out in the scanning direction of a TV monitor to display an image.

By the way, if you think about the reason why a DSC circuit is not used when displaying images of radial scan data,
In the case of sector scan data, when reading empty pixels between rasters, interpolation processing is performed in the horizontal direction of the TV monitor to fill in the empty pixels, while in the case of radial scan data, as shown in Figure 10, the TV monitor This is because in a raster near the horizontal direction, there are many empty pixels in the horizontal direction, and it is difficult to perform interpolation processing on these pixels.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and when radial scan data is interpolated and written to each pixel of a storage means, a small amount of vector data information is appropriately converted to enable zoom display and moving display. The object of the present invention is to provide an ultrasonic diagnostic apparatus that enables writing.

[Summary of the invention]

The outline of the present invention for achieving the above object is to store radial scan data obtained by radially scanning an ultrasonic probe in a storage means, and display a radial scan image based on this radial scan data on a display means. The ultrasonic diagnostic apparatus includes an interpolation processing section that performs predetermined interpolation processing on the radial scan data and sends the interpolation result data to a storage means, and a plurality of pixel areas on the storage means in which the interpolation result data is to be stored. A conversion process that sets data corresponding to the entire area based on vector data indicating the raster direction in one of the divided areas, an addition process of a predetermined bias value to these vector data, and area discrimination based on the result of the addition process. The write address signal corresponding to each divided area or the fortune-telling address signal determined by the area determination process is sent to the storage means in synchronization with the transmission timing of the interpolation result data from the interpolation processing unit to the storage means. and write address designation means for sending data to storage means.

[Embodiments of the invention]

Examples of the present invention will be described in detail below. The embodiment device shown in FIG. 1 includes an ultrasonic probe 1, such as a mechanical sector scan probe, capable of radial scanning of a subject, and a controller 30 (details will be described later) that controls each part of the device. A transmitting/receiving circuit 2 which excites the ultrasonic probe 1 at a predetermined timing based on a control signal and receives radial scan data obtained by the ultrasonic probe 1; An interpolation processing section 4 that performs interpolation processing based on a control signal from the controller 30;
write address designating means 5 which specifies a write address for writing the interpolation processing result of the radial scan data by the interpolation processing unit 4 into each pixel of the frame memory 6 which is a storage means; A readout circuit 7 reads radial scan data and interpolation processing data (hereinafter referred to as "interpolation processing result data") and sends it to a TV monitor 8 which is a display means, and a human power signal is sent to the controller 30 via the controller 30. and input means 9, such as a trackball, which changes the state of the displayed image on the TV monitor 8 by controlling the readout circuit 7.

The write address designating means 5 includes a controller 30.
The radial scan data to be stored on the frame memory 6 forms a circular area P (third
For example, a vector data generating section 31 generates vector data XA+yA corresponding to A block when a block (see figure) is divided into four blocks, A block to D block, and a vector data generator 31 generates vector data A basic address generating section 32 that generates the address of block A shown in FIG. 4(a) and a controller 30 rotate the address of block A generated by the basic address generating section 32 as shown in FIG. 4(a). B.Ci
D Coordinate conversion unit 33 that generates addresses for each block
and is controlled by the controller 30, as shown in FIG. 4(b).
, As shown in (c), a predetermined bias value (α for the X direction, β for the y direction) is added to the address of each block to obtain the address to be written to the frame memory 6. The bias addition unit 34 determines whether each address after bias addition corresponds to an address on the frame memory 6, and if it is determined that it is not an address on the frame memory, prohibits reading of that address. The address determination unit 35 has an address discriminating unit 35.

Now, considering the addresses of the A-D blocks, as shown in FIG. 4(a), the vector data Xi and yi of the B block are the vector data XAI of the A block)
'A rotated 90 degrees clockwise, XR=y
It can be expressed as A, Va = XA.

Furthermore, the vector data Xc, 3'c of the C block is obtained by rotating the vector data XA, yA in the clockwise direction, and can be expressed as XC-XAI Yc='IA.

Similarly, vector data X of D block. ,y.

is the vector data XAI>'A rotated by 270 degrees clockwise, and XD=MA+'! o =
It can be expressed as XA.

Each of these vector data x, ) XAI xB
y>'Il.

xc l >'C+ xD + 3'o is each block A.

It will only have values within B, C, and D.

Next, the bias value addition process of the bias addition section 33 will be considered. When the frame memory 6 is plotted on the x and y coordinates as shown in FIG. Bias value α for the output, for example in the X direction.

and a bias value β for the X direction.

That is, this bias value α1. The setting of β1 is such that the address corresponding to the write address signals X and Y specified through the determination by the address determination unit 35 is
It means that everything above exists.

On the other hand, the bias value α1. Bias value α2. which is different from β. β2 is set, and the result of addition by the bias adder 34 is displayed in the frame memory 6 as shown in the shaded area in FIG. 4(c).
If the part corresponds to the actual address above and the other part, the address discrimination unit 35 sends the write address signal only to the part corresponding to the shaded part to the frame memory 6.
The data is sent to , and the portion within that range is written-protected.

As a result, in this case, only the interpolation processing result data from the interpolation processing unit 4 corresponding to part of the B block, part of the C block, and the central part of the A block and D block in the area P are written to the write address. Write address signal X from specifying means 5.

Y is written to the corresponding pixel on the frame memory 6.

Next, details of the interpolation processing section 4 and the controller 30 will be explained with reference to FIG. 5.

This interpolation processing unit 4 is an A/D converter that converts radial scan data, which is a reflected ultrasound echo signal, into a digital signal.
A converter (ADC) 12, a high-speed buffer memory group 13 comprising a plurality of high-speed sofa memories 13A to 13N each storing digital data of a scanned beam line by line via a switch SW1, and each high-speed buffer. A filter computing unit group 15 includes a plurality of filter computing units 15A to 15N that multiply the data read out from the memory via the switch SW2 by a coefficient for filter computing, and adds the outputs of each filter computing unit 15A to 15N. , and an adder 6 that sends the addition result to the frame memory 6 as interpolation processing result data.

The interpolation processing of the radial scan data by the interpolation processing section 4 is performed based on a first basic address signal (described in detail later) consisting of three types from the controller 30.

That is, the controller 30 counts the clock generator 17, which generates the basic clock for each circuit based on the input signal from the input means 9, and the clock signal CK of this clock generator 17 by +1, and outputs the X address selection signal. X address (n) which inputs the Y address counter 18 and the clock signal GK to cumulatively add a predetermined X direction unit address signal ΔXn.
A +l counter 22 that uses the first clock signal CKI of the two clock signals from the cumulative adder 19 and the clock generator 17 as a clear signal, counts the second clock signal CK2 by +1, and generates an output of +δ.
and an adder 21 that adds the output +δ of the +1 counter 22 and the output ΔX from the X-address cumulative adder 19 and outputs an X-direction selection signal. The selection signal is sent to the write address designation means 5 as a second basic address signal.

Here, the principle of interpolation processing of radial scan data by the interpolation processing section 4 will be explained.

Conventionally, as shown in Fig. 6, sample points (large black circles in the figure) are determined for the beam BM passing through the pixel P at approximately pixel intervals, and the data is inserted into the writing point (white circles in the figure) at the center of the pixel. However, in the present invention, additional sample points (small black circles in the figure) are provided, which are smaller sample points, and the filter is filtered based on the data of the sample point where the starting point of the beam is at the same distance as the center position of the pixel P. The calculation is performed, and the center (white circle) of the pixel is filled in with the result. The filter calculation in this case is performed by the following equation (1).

f (x) −Σ h (X −kx) −DATA
(kx) ・” (I) As is clear from equation (1) above, what determines the filter operation is the shape of the filter function h (x) and the convolution range N. In this case, the filter function h Since it changes infinitely depending on the design method, it can be arbitrarily determined without being specified, and the range N of convolution can also be changed infinitely depending on the scale of the scan and hardware configuration, so it can be arbitrarily determined. It can be decided.

The above explanation was about writing data into pixels through which beam BM passes, but please refer to FIG. 7 for writing (embedding) into pixels through which beam BM does not pass.

I will explain. In the figure, for example, pixels Pz, Px, P4
is the range through which the beam does not pass. In this case, arcs p2, . eJ.

14 and the adjacent beams BMn and B that intersect each line
Sample point SZ+ Sz' located at the intersection of Mn-+
S3. A filter operation is performed based on the data obtained by combining each of Sz', S41 and S4', and the result is written at the center position Oz, 03, and Oa of each pixel. Similarly, the pixel PI through which the beam passes
Similarly, sample points S+, S on the same arc
It is also possible to write to the center position OI based on the data of +'.

Here, the principle of selection of sample points on which the filter calculation is based will be explained with reference to FIG.

The distance between adjacent beams BMn and BMn is L, the writing target pixel is P3, its center position is 0°, and the distance to the sample point S0 located at the intersection of beam BMn and the horizontal line passing through 03 is X, and the sample point S located at the intersection of the lines drawn on the beam 8Mn from the center position 03
, and the deflection angle of the beam is θ, then the sample point S on the beam 8Mn.

[distance rl] to another sample point S3] is determined by the following equation (2).

rB=)(a ・sin θ −
(21) Note that the sample point S0 is a coordinate determined by cumulative addition in the X direction, and r shown in the figure is a radius determined by cumulative addition in the radial direction.

The position of the sample point S3 can be found by adding the above r to r8 obtained by the above equation (2).

Similarly, sample point 83 of adjacent beam BMn-+
', performs a filter operation based on the data at both ends, and writes the result to the center 03 of the pixel P3. In this case, the filter coefficient can be determined by manually inputting the above X and L to determine the positional relationship between the writing point and the adjacent beam, and by providing this and the filter characteristics. As a result, data and coefficients can be output, so a convolution operation can be performed based on both, and the output can be written to the target pixel.

Furthermore, in the present invention, in order to prevent empty pixels from occurring, processing is performed to fill all pixels.

This will be explained with reference to FIG. Here, n main beams BMn (!=n1st main beam BMn-.

The case where everything between is filled will be explained.

First, two systems of hector generation units are prepared, and addresses are generated by cumulatively adding +1 in the Y direction and ΔXn and ΔXn−+ in the X direction. Y address Y, X address selection, Xn.

After computing, Xn-Xn-+ is computed to calculate the number of character pixels. After writing to (Y, Xn), write to Y, Xn +1) by increasing Xn by +1. After performing this operation Xn-xn-+ times, a new address is generated as Y=Y+1 Xn=Xn +ΔXn
As shown in the figure, all pixels 1 to 36 in the range surrounded by the beam can be filled.

Now, the cumulative adder for the X address has a two-system configuration, in addition to the cumulative adder for the n-th beam mentioned above,
There is a cumulative adder 20 for the n-1th beam on this side, which performs cumulative addition of the clock signal CK and the unit selection signal ΔXn-+ of the n-]th beam.

This is provided to realize the previous calculation shown in FIG. 8, as described below.

That is, by providing a subtracter 23 for subtracting the outputs of the two X-address cumulative adders 19 and 20, two adjacent beams BMn and BMn as shown in FIG. 8G are obtained.

Find the distance of the line passing through the center 03 of the target pixel P3 that intersects with P3, and input this output as one of the first basic address signals as a parameter of the filter calculator 15, which will be described later, and also input it to the next stage comparator. It is output to 24. The comparator 24 uses the distance and the output +δ of the +1 counter 22.
are compared, and a clear signal is output to the clock generator 17 based on the output when both have lost. As a result, the X addresses are selected one after another with the distance as the limit, but when cleared, they return to the original position and address selection is performed in relation to the next Y address selection signal. Further, the output +δ from the +1 counter 22 is led to the adder 25 together with the output of the cumulative adder 19 for the X address (n), and from this adder 25, the sample point of the beam BMn shown in FIG. The distance Xm from S0 to the center o3 of the target pixel P3 is output as one of the first basic address signals. This output X8 is input to the XY-Rθ converter 26 together with the beam deflection angle θ, and this converter 26 converts the reference sample point S0 in FIG.
The distance rl(sinθ・xs
) is calculated.

Addresses of the high-speed buffers 13A to 13N are selected by signals as described below. First, there is a high-speed buffer address selection accumulator 27 which outputs the radius signal r shown in FIG. 8 by cumulatively adding the clock signal CKl from the clock generator 17 and the sampling interval signal Δr; and an adder 28 for adding the output signal r from the XY-Rθ converter 26 and the output signal rfl from the XY-Rθ converter 26, and using the addition result as one of the first basic address signals and sending it out. Sample point S3 is selected based on the output of . still,
The sampling interval Δr is set to a fineness several tenths of that of the conventional method.

On the other hand, a filter computing unit 15 (for example, 15N) receives the output signal of the subtracter 23 and outputs the output signal XI of the adder 25.
l. Consisting of a coefficient determining circuit 15a that makes the filter characteristic 3-man-powered, and a multiplier (convolution calculation unit) 15b that multiplies the filter coefficient determined by this circuit by the data obtained via the switch SW2, A filter operation is performed on the selected sample points.

Next, the operation of the device having the above configuration will be explained, focusing on the operation of the write address designating means 5.

The operation of the interpolation processing section 4 was already described in the explanation of the principle, so only the general operation will be explained below.

The controller 30 sends a second basic address signal consisting of an X address selection signal and a Y address selection signal to the vector data generation section 31 of the write address designation means 5. At this time, the X address cumulative adder 1 having two systems
9. The difference between the outputs of 20 and 20 is calculated by subtraction H23, and 1 is sequentially added to the X address until all empty pixels within the distance are filled.

Then, each time the X address is determined, an XY-Rθ converter 26
The value rB is calculated by adding this result and the radius r to the adder 28.
By using the addition result as a high-speed buffer address selection signal, the sample data on the same radius as the write point of the target pixel is added to several surrounding pixels (at least two
The filter calculation is performed by reading from the high-speed puffer memory of the book. The filter coefficient can be determined by inputting the values X, . . . L to determine the positional relationship between the target writing point and the adjacent beam, and by providing the values and filter characteristics. A convolution operation is performed based on the filter coefficients and data, and this is sent to the frame memory 6 as interpolation processing result data. Then X
After adding 1 to the address sequentially to obtain calculation result data to fill in the empty pixels in the horizontal direction sandwiched between the two ultrasonic beams, the operation is repeated for the distance, and then the calculation results to fill in the empty pixels in the lower row in the vertical direction. The data are obtained and sent to the frame memory 6 in sequence.

In this way, all the data of the storage target pixel area on the frame memory 6 is obtained.

On the other hand, in the write address designation means 5, the vector data generation section 31 generates vector data XA, yA of the A block, the basic address generation section 32 generates the address of the A block, and the coordinate conversion section 33 generates the A block data XA, yA.
Conversion processing of the address of the block to other blocks B, C, and D blocks, and a predetermined bias value α by the bias addition unit 33.

Addition processing of β and area determination processing of the addition processing result by the address determination section 34 are performed.

Now, when the interpolation processing result data to be stored in each pixel of A block is sent from the interpolation processing unit 4 to the frame memory 6, the write address designation means 5 is controlled by the controller 30, and the write address designation means 5 is controlled by the controller 30 to No conversion processing is performed, and the bias adder 33 adds the bias value α1 to this address. β, is added, and this addition result is sent to the address discrimination unit 34 as the address of the shaded area A block shown in FIG. Sent to 6.

As a result, the interpolation processing result data from the interpolation processing unit 4 to the A block is sequentially written to each pixel of the A block on the frame memory 6.

When the interpolation processing result data is sent from the interpolation processing unit 4 to the B block after the writing process to the A block is completed, the coordinate conversion unit 32 is controlled by the controller 30 and converts the address of the A block to the address of the A block. Performs address conversion processing to B block. Then, for this address, bias value α6. The f&B block write address signal is sent to the frame memory 6 as an f&B block write address signal which has been subjected to addition processing of β and area determination processing. As a result, the interpolation processing result data for the B block is sequentially written into each pixel of the B block on the frame memory 6.

Thereafter, in the same manner as the interpolation process result data for C and D blocks are sent to the frame memory 6, a write address signal based on the conversion process corresponding to the C2D block is sent from the write address designating means 5 to the frame memory 6. Through the above operations, interpolation processing result data is written in real time to each storage target pixel in the entire area of blocks A to D.

The interpolation processing result data of the radial scan data stored in the frame memory 6 in this manner is read out in the horizontal direction by a readout circuit 7 controlled by the controller 30 and sent to the TV monitor 8. As a result, a high-quality interpolated radial scan image is displayed on the screen of the TV monitor 8.

Next, a case will be described in which partial display or zoom display of a radial scan image is performed.

In this case, the bias adder 34 adds the bias values α2°β2 to each address of the A-D block to obtain the address of the circular area shown in FIG. 4(c), and the address discriminator 35 The vector data belonging to the shaded area in the figure is determined, and in synchronization with the sending timing of the interpolation processing result data, a basic address signal based on the data of the part belonging to this area and a write prohibition command for the part not belonging to this area are generated. is sent to the frame memory 6.

As a result, of the interpolation processing result data, only those belonging to part of the -B block and C block and the central part of the A block and D block are written to the frame memory 6, and other parts are not written. .

By arbitrarily setting the bias value in the bias adder 34 in this way, interpolation processing result data can be partially written.

In addition, when performing partial enlargement display based on the interpolation processing result data, the bias value of the bias addition section 34 is further changed, and the address discrimination section 35 discriminates the area corresponding to the part to be enlarged, and performs interpolation. A write address signal for changing the write address on the frame memory 6 of processing result data is sent to the frame memory 6. The same applies to the case of partially reduced display.

Incidentally, the above-mentioned bias value change is performed by sending a bias value change signal from the input means 9 to the bias addition section 34 via the controller 30.

The data for partial or zoom display written in the frame memory 6 in the above procedure is read out by the readout circuit 7 and displayed on the screen of the TV monitor 8 as a partial image or a zoom image.

The present invention is not limited to the embodiments described above (it goes without saying that various modifications can be made within the scope of the invention).

For example, in the above-mentioned embodiment, a case was explained in which the vector data for storing interpolation processing result data in the frame memory is generated only in block A, which is obtained by dividing a circular area into four, but the invention is not limited to this. Vector data may be generated for one block.

〔Effect of the invention〕

According to the present invention described in detail above, the write address designation means generates hector data and its address for one block divided into a plurality of circular areas formed by the radial scan data, and coordinates the address for the address. Since the write address signal to the storage means is obtained by performing conversion processing, bias addition processing, and area discrimination processing, it is possible to perform partial display or zoom display of a radial scan image by simply retaining a small amount of vector information. It is possible to provide an ultrasonic diagnostic apparatus that can perform a writing operation.

In addition, since the radial scan data is interpolated to the storage target pixel in the storage device and then written to the storage device, it is possible to obtain high-quality images without producing empty pixels. equipment can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of write address designation means in the same device, and FIG. 3 is an explanation showing the area formed by radial scan data on the frame memory. 4(a) is the area X shown in FIG. 3. An explanatory diagram showing the coordinates of vector data in the y-coordinate system,
FIGS. 4(b) and 4(c) are explanatory diagrams showing the state in which bias has been added to the area shown in FIG. 4(a), and FIG.
The figure is a circuit diagram showing the configuration of the interpolation processing unit, basic address generation unit, and write address designation means in the device of this embodiment, and FIGS. 6 to 9 each illustrate the principle of interpolation processing by the interpolation processing unit of the device of this embodiment. FIG. 10 is an explanatory diagram showing the storage state of conventional radial scan data in a frame memory. 1... Ultrasonic probe, 2... Transmission/reception circuit, 3...
- Control circuit, 4... Interpolation processing section, 5... Write address designation means, 6... Frame memory, 7... Readout circuit, 8.
...TV monitor, 31...Vector data generation section, 3
2... Vector data conversion section, 33... Bias addition section, 34... Address determination section.

Claims (2)

[Claims] (1) In an ultrasonic diagnostic apparatus that stores radial scan data obtained by radially scanning an ultrasound probe in a storage means and displays a radial scan image based on this radial scan data on a display means, the radial scan data an interpolation processing section that performs predetermined interpolation processing on the data and sends the interpolation result data to storage means; A conversion process for setting data corresponding to the entire area based on vector data indicating the direction, an addition process of a predetermined bias value to these vector data, and an area discrimination process of the result of the addition process are performed from the interpolation processing unit to the storage means. write address designation means for sending to the storage means a write address signal corresponding to each divided area or a write address signal determined by area determination processing in synchronization with the sending timing of interpolation result data to the storage means; An ultrasonic diagnostic device characterized by: (2) The interpolation processing unit performs sampling thinner than one pixel in the storage means for the radial scan data, and the same distance as the storage target pixel in a plurality of ultrasound beams near the storage target pixel in the storage means. A process of performing a filter operation based on the data of the sample points in and storing the result of this operation in the storage means based on the write address signal from the write address designating means is repeated until all pixels located within the ultrasonic beam are stored. The ultrasonic diagnostic apparatus according to claim 1, which is configured to store interpolation result data.