JPS6273814A - Delay circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably a forming region of a transfer mold by using master slice so as to select a gate length of the transfer mold so as to very an ON-resistance optionally. CONSTITUTION:In selecting the width of a gate electrode 41 by the master slice so as to form the channel length as, e.g., L1, the on-resistance of an NMOS 35 is R1. Thus, the input signal is delayed for a prescribed time by a time constant R1.C1 comprising a capacitance C1 of a parasitic capacitor 39 and the on-resistance R1 and the result is given to an inverter 38. Thus, plural channel lengths L1-4L1 are prepared in advance and the channel lengths L1-4L1 and the gate electrode 41 are selected by the master slice, then the on-resistances R1-4R1 of the NMOS 35 are set optionally and a desired delay time is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a delay circuit that extends signal transfer time by eight times.

(Prior art) Conventionally, as a technology in this field,
There was one described in Publication No. 33E1. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional delay circuit.

This delay circuit is a circuit made by master slice type neck wiring, with an input terminal 1, an output terminal 2. Power supply VD
D terminal 3. and a ground terminal 4. The input terminal l has a plurality of transfer gates, for example, an N-channel M
OS transistors (hereinafter referred to as NHO2) 5-7 are connected in series via connection points (hereinafter referred to as contacts) 8-10. The gate electrodes of each of the NMOSs 85 to 7, to which control inputs are received, are connected to the power supply VDfl terminal 3 via a metal wiring 11, and the final stage NMOS 7 is further connected to the gate electrode of the inverter 12 via a contact 10. The inverter 12 is connected to a power supply VDD terminal 3 and a ground terminal 4, and further has an output side connected to an output terminal 2.

FIG. 3 is a pattern diagram of the circuit shown in FIG. 2. Each NMO 55 to 7 is an NMO formed on a P-type substrate.
fi diffusion layer 20, gate electrode 2 made of polycrystalline silicon
1. and metal wiring 22 connecting each contact 8 to 10
It is made up of etc.

In the above configuration, the power supply voltage VIll! applied to each gate electrode 21 of each N in FIG. D turns it on. Therefore, the signal input to the input terminal 1 is transferred to the inverter 12 through each of the NMOs 55 to 7, inverted by the inverter 12, and output from the output terminal 2.

Here, if the resistance value of each NMO 55 to 7 in the on state (hereinafter referred to as on-state resistance value) is R, then the series resistance value thereof is 3R. Further, since there is a parasitic capacitance C inside the circuit, a predetermined delay time occurs in the signal passing between the input and output terminals 1.2 due to the time constant 3RXC determined by the parasitic capacitance C and the series resistance value 3R.

Therefore, the delay time can be changed by arbitrarily setting the contacts 8 to 10, which are the connection points of the NMOs 85 to 7, to mAf. That is, in FIG. 3, depending on the combination of the presence or absence of contacts 8 to 10 and the metal wiring 22,
The selection of NMOSs 5 to 7 formed by the gate electrode 21 is performed by master slicing. As a result, the on-resistance R,
Either 2R or 3R is selected, and a predetermined delay time is obtained by a time constant determined by its on-resistance value and parasitic capacitance C.

In this type of delay circuit, in order to obtain a predetermined delay time,
On-resistance values of NMOS 5 to 7 are used.

Therefore, a large resistance value can be obtained using a small-sided square, and the circuit can be made smaller compared to one that utilizes the low resistance value of a gate electrode made of polycrystalline silicon or an N-type diffusion layer.

(Problem to be Solved by the Invention) However, in the delay circuit with the above configuration, a plurality of NM
Since OS 5 to 7 are patterned and a combination of contacts 8 to IO and metal wiring 22 is selected by master slicing to obtain a predetermined on-resistance value, a pattern area for each NMO 95 to 7 is required. Not only that, but
There was a problem in that the area occupied by contacts 8 to 10 became harsh.

The present invention provides a delay circuit which solves the problems of the prior art in that a pattern area for a plurality of 1a MOS transistors is required and the contact area becomes large.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes a transfer gate that is turned on by a control input and transfers an input signal to provide it to an inverter. In a delay circuit that extends the transfer time of a serious crime signal by a predetermined time based on a resistance value in an on state, the transfer gate has a channel length varied by a master slice to set a resistance value in an on state to a predetermined value. It is structured as follows.

(Function) According to the present invention, since one or more delay circuits are configured, one transfer gate is prepared, and the channel length of the transfer gate is appropriately selected by the master slice to set a predetermined on-resistance value. do. This allows the delay time to be determined. Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a pattern diagram of a delay circuit showing an embodiment of the present invention.
FIG. 4 is its circuit diagram.

As shown in FIG. 4, this delay circuit includes input terminals 31,
Output terminal 32, power supply VDD terminal 33, and ground terminal 34
have. One transfer gate, for example N11O935, is connected to the input terminal 31.

The gate electrode of the NMOS 35 to which the control input is applied is connected to the power supply VDD terminal 33 by a metal wiring 36.
Furthermore, the output side is connected to the inverter 3 via the metal wiring 37.
It is connected to the gate electrode of No.8. The inverter 38 is connected to the Ichihara VDD terminal 33 and the ground terminal T-34.

Further, the output side is connected to an output terminal 32. Also,
A parasitic capacitance or gate capacitance (hereinafter simply referred to as parasitic capacitance) 39 is formed between the metal wiring 37 and the ground.

Here, the NMOS 35 has a structure in which the channel length can be varied by the master slice.
The phase q of the MOS transistor: the contactor Gm is expressed by the following equation.

Here, VD=constant However, YD; Drain', Pi style.

■D; Drain voltage.

VG, gate voltage.

VT: threshold voltage.

k; Is it a career change?

εOx: Attraction of gate oxide film rate.

TOX: Thickness of gate oxide film difference.

W, MOS transistor Channel width.

L; MOS transistor Channel length.

The above (:) expression,! ;If you change it, it becomes as follows.

As is clear from equation (2), the phase-1II conductance Cm is proportional to the channel width W and inversely proportional to the channel length. When the channel length increases by N times, the phase W conductance Gya becomes l/N, so by making the channel length variable, the on-resistance R of the MOS transistor can be set to any value.

Therefore, since the NMOS 35 shown in FIG. 4 has a channel length of +i (variable structure), its on-resistance value R can be varied.

The structure of this NMOS 35 is shown in the pattern diagram of FIG. In Fig. 1, NMOS35 is P type),
(By adjusting the N-type diffusion layer 40 formed on the plate 1- and the gate electrode 41'S- made of polycrystalline silicon, and changing the width of the gate electrode 41, a channel length of I'ti length can be obtained. Channel length 4L multiple times L1, for example 4 times
It has a structure that can be varied up to 1.・The inverter 38 has two gate electrodes 42 and 43, one of which is connected to the NMOS 35 via the metal wiring 37.
It is connected to the N type diffusion layer 40 of.

The operating element of the delay circuit configured as described above will be explained.

First, the circuit operation in FIG. 4 is similar to the conventional one.
Since the power supply voltage vDD is applied to the gate electrode of the NMOS 35, the NMOS 35 is turned on. Therefore.

The signal input to the input terminal 31 is passed through the NMOS 35, transferred to the inverter 3, inverted by the inverter 38, and output from the output terminal f-38.

Here, in FIG. 1, if the width of the gate electrode 41 is selected by master slicing so that the channel length is Ll, for example, the on-resistance value of the NMOS 35 becomes R1. Therefore, the time constant R1・C determined by the capacitance value C1 of r39 and the on-resistance value R1 in FIG.
1, the input signal is delayed for a predetermined period of time, which is then provided to the inverter 38.

In this way, the tree-(on the downstream side, a plurality of channel lengths Ll
, 2L1, 3L1, and 4Ll are prepared in Y sizes, and the channel lengths L1 to 4Ll and the gate electrode 41 are selected by master slicing according to the spirit.
The on-resistance values R1 to 4R1 of 5 can be set arbitrarily.

The desired delay time is thereby obtained. Moreover, since this is possible with only one NN0535, NMOS35
pattern area and contact area can be reduced. In this embodiment, the number can be reduced to 172 pieces compared to the conventional one.

In addition, in the above embodiment, the channel length can be changed within the range of L1 to 4L1, but this range can be further extended to 5L1.
If it is made wider than this, NMOS will function as a resistance.
The formation area of 35 can be significantly reduced compared to the conventional one.

In addition, on the actual flow side described in 1-1, the transfer gate is NMO
Although it is configured with S35, it may be configured with a P-channel MO9) transistor (hereinafter referred to as PMOS) or a complementary MOS transistor (hereinafter referred to as CMOS) AV'. When configured with CMOS, the NM that configures it
The structure may be such that the channel length of either or both of the OS and PMOS can be changed. Furthermore, it goes without saying that circuit parks other than the transfer gate can be modified in various ways.

(Effects of the Invention) As explained in detail above, according to the present invention, the gate length of the transfer mold is selected by master slicing, and the structure is such that the on-resistance value can be arbitrarily varied, so that the formation area of the transfer mold can be greatly expanded. can be reduced to

[Brief explanation of drawings]

FIG. 1 is a pattern diagram of a delay circuit showing an embodiment of the present invention;
FIG. 2 is a circuit diagram of a conventional delay circuit, FIG. 3 is a pattern diagram of FIG. 2, and FIG. 4 is a circuit diagram of FIG. 1. 31...Input terminal, 32...Output terminal, 33...Power supply VDD terminal, 34...
Ground terminal, 35...8MO8, 37...
・Fully bent wiring, 38... Inverter, 39...
...parasitic capacitance. 40...P-type diffusion layer, 41...gate electrode. Pattern diagram of the delay circuit invented by Heather Figure 1￥2 Figure

Claims (1)

[Scope of Claims] A transfer gate that is turned on by a control input and transfers an input signal and supplies it to an inverter is provided, and the transfer time of the signal is extended by a predetermined time based on the resistance value of the transfer gate when the transfer gate is in the on state. 2. A delay circuit characterized in that the transfer gate has a configuration in which the channel length of the transfer gate is varied by a master slice and a resistance value in an on state is set to a predetermined value.