JPS6273651A - Semiconductor integrated circuit module - Google Patents
Semiconductor integrated circuit moduleInfo
- Publication number
- JPS6273651A JPS6273651A JP21233985A JP21233985A JPS6273651A JP S6273651 A JPS6273651 A JP S6273651A JP 21233985 A JP21233985 A JP 21233985A JP 21233985 A JP21233985 A JP 21233985A JP S6273651 A JPS6273651 A JP S6273651A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- electrode
- package
- semiconductor wafer
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体集積回路モジュールに係り、特にモジュ
ールの配線基板として半導体ウェハを用いたマルチチッ
プ・モジュール、または回路が形成された半導体ウェハ
を実装するモノリシックＷＳ丁モジュールの構造に関す
る。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit module, and particularly to a multi-chip module using a semiconductor wafer as a wiring board of the module, or a semiconductor wafer on which a circuit is formed. Concerning the structure of a monolithic WS module.
半導体ウェハをモジュールの配線基板として用いたマル
チチップ・モジュールは、文＃（１）プロシーディンゲ
ス オブ ザ １９８３ カスタ１１インテケレイテ
イツド サーキット コンフエレンス（Ｐｒｏｃｅｅｄ
ｉｎｇｓ ｏｆ Ｔｈｅ １９８３ ＣｕｓｔｏｍＩｎ
ｔｅｇｒａｔａｄ Ｃ１ｒｃｕｉｔｓ Ｃｏｎｆｅｒｅ
ｎｃｅ）ｐｐ、 １４２．−１４６、文献（２）日立１
９８４年５月号ｐＰ、 ８−９、あるいは特開昭５９−
２３５３１号に開示されている。しかし、これらの従来
技術では、モジュールの信号ピンはワイアボンドにより
モジュール基板の周囲からとり出しているため、数１０
個のＬＳＩチツプを搭載したモジュールを実現しようと
すると、モジュール基板の中央部におかれたＬＳＩチッ
プの出力にはボンディング・パッドまでの長い配線によ
る抵抗がはいる。従って、このＬＳＩ出力をそのままモ
ジュールの出力とすることはできず、モジュール基板周
辺のボンディング・パッド近くにモジュールの出力バッ
ファ用チップを置く必要があり、モジュール基板上の長
い配線と合わせて出力回路の遅延時間が問題になってい
た。さらに２１０００ピン以上の多数の信号ピンを必要
とするモジュールにおいては、モジュールを搭載するパ
ッケージとして、文献（２）に示されているリードフレ
ームのような、パッケージの周辺からビンをとり出す構
造を用いることはできず、パッケージの全面にピンを立
てるビン・グリッド・アレー構造を採らざるを得ない、
すると、ピン・グリッド・アレーの中央部の信号ビンへ
は、モジュール基板の周囲からボンディング・ワイアに
よりパッケージ上の電極に接続した後、パッケージ上に
再び長い配線を行う必要があった。このため、パッケー
ジ上の配線による静電容置が大きくなり、さらにパッケ
ージ上を長い信号配線が平行して走るので、隣接した配
線からのクロストーク・ノイズが問題になっていた。A multi-chip module using a semiconductor wafer as the module's wiring board is based on the document #(1) Proceedings of the 1983 Customer 11 Integrated Circuit Conference.
ings of The 1983 CustomIn
tegratad C1rcuits Conference
nce)pp, 142. -146, Literature (2) Hitachi 1
May 1984 issue pP, 8-9, or JP-A-1987-
No. 23531. However, in these conventional technologies, the signal pins of the module are taken out from the periphery of the module board by wire bonding, so the number of
When attempting to realize a module equipped with several LSI chips, the output of the LSI chip placed in the center of the module board will have resistance due to the long wiring to the bonding pad. Therefore, this LSI output cannot be directly used as the module's output, and it is necessary to place the module's output buffer chip near the bonding pad around the module board. Latency was an issue. Furthermore, for modules that require a large number of signal pins (21,000 pins or more), a structure in which the vias are taken out from the periphery of the package is used as a package for mounting the module, such as the lead frame shown in document (2). It is not possible to do so, and a bin grid array structure with pins placed all over the package must be used.
Then, to connect the signal bin in the center of the pin grid array to the electrode on the package using bonding wires from around the module board, it was necessary to run a long wiring again on the package. For this reason, the electrostatic capacity caused by the wiring on the package becomes large, and since long signal wiring runs in parallel on the package, crosstalk noise from adjacent wiring becomes a problem.
本発明の目的は、モジュール基板として半導体ウェハを
用いながら、多数の信号ビンをとり出すことができ、し
かも遅延時間の増大やクロストーク・ノイズを生ずるこ
との少ないモジュールを提供することにある。An object of the present invention is to provide a module that can extract a large number of signal bins while using a semiconductor wafer as a module substrate, and that does not increase delay time or cause crosstalk noise.
本発明は、モジュール基板であるウェハに表面と裏面を
電気的に接続するフィードスルーを設け。The present invention provides a wafer, which is a module substrate, with a feedthrough that electrically connects the front and back sides.
これによりＬＳＩチップを搭載するウェハ表面から裏面
にモジュールの信号を伝搬させ、さらにウェハ裏面に設
けた信号電極とパッケージ基板上に設けた信号電極を非
等方電導性ゴムなどの手段により接続しようとするもの
である。As a result, module signals are propagated from the front side of the wafer on which the LSI chips are mounted to the back side, and the signal electrodes provided on the back side of the wafer are connected to the signal electrodes provided on the package substrate using means such as anisotropically conductive rubber. It is something to do.
以下、本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例のモジュールの断面図である
。図において、１はフリップチップ型のＬＳＩチップ、
２はモジュール基板であり、 ＬＳＩチップ１はフェー
スダウン・ボンディングによりモジュール基板２に接続
する。、３がそのハンダ・バンプである。４はパッケー
ジのセラミック基板であり、５はパッケージのビンであ
る。６はモジュール基板の裏面に設けられた電極パッド
とピン５を接続するコネクタであり、モジュールの入出
力信号はＬＳＩチップ１からモジュール基板２゜コネク
タ６を経てピン５に導かれる。７は空冷用のフィンと一
体化したパッケージのキャップであるが、フィンとキャ
ップを別々に製造した後、接着したものであってもよい
。ＬＳＩチップ１の裏面には熱伝導性グリース８を塗布
し、キャップ７と熱的に接着する。ＬＳＩチップ１が０
ＭＯ８の場合にはこの程度の冷却系で問題ないが、バイ
ポーラＬＳＩのよう大電力のＬＳＩチップを搭載する場
合には、例えば米国特許４１９３４４５号に開示されて
いるようなピストン構造の冷却系を採る。９はパッケー
ジ内部に不活性ガスを充填した後、気密状態を保つため
のバッキングであり、１０はパッケージ基板４にキャッ
プ７を固定するためのボルトである。第２図は本発明の
ポイントであるモジュール基板上の配線とパッケージの
ビンを接続する部分を示すモジュール断面の拡大図であ
る。図において、１１はモジュール基板であるウェハの
両面間を電気的に接続するフィードスルーであり。FIG. 1 is a sectional view of a module according to an embodiment of the present invention. In the figure, 1 is a flip-chip type LSI chip;
2 is a module board, and the LSI chip 1 is connected to the module board 2 by face-down bonding. , 3 are the solder bumps. 4 is a ceramic substrate of the package, and 5 is a bottle of the package. A connector 6 connects an electrode pad provided on the back surface of the module board to the pin 5, and input/output signals of the module are guided from the LSI chip 1 to the pin 5 via the module board 2° connector 6. 7 is a package cap integrated with air cooling fins, but the fins and cap may be manufactured separately and then bonded together. Thermal conductive grease 8 is applied to the back surface of the LSI chip 1 and it is thermally bonded to the cap 7. LSI chip 1 is 0
In the case of MO8, there is no problem with this level of cooling system, but when mounting a high power LSI chip such as a bipolar LSI, a piston structure cooling system as disclosed in US Pat. No. 4,193,445, for example, is required. . Reference numeral 9 is a backing for maintaining an airtight state after filling the inside of the package with inert gas, and reference numeral 10 is a bolt for fixing the cap 7 to the package substrate 4. FIG. 2 is an enlarged cross-sectional view of the module showing a portion where the wiring on the module board and the bottle of the package are connected, which is the key point of the present invention. In the figure, numeral 11 is a feedthrough that electrically connects both surfaces of a wafer, which is a module substrate.
文献（３）アイ・イー・イー・イー トランザクション
ズ コンピュータ ポル（＞３３．第１号。Literature (3) IE Transactions Computer Pol (>33. No. 1.
１月、 １９８４ （ＩＥＥＩＥ Ｔｒａｎｓ、Ｃｏｍ
ｐｕｔｅｒ、Ｖｏ Ｑ 、 Ｃ−３：３ ｒ ＆ Ｉ
ＩＪａｎ、 １９８４） ｐｐ−６９８１に示されてい
るサーモマイグレーションの手段により形成する。フィ
ードスルー１１はＮ型ウェハ基板に対してＰ型となり、
ウェハに最も高いｔ位を与えるこによりフィードスルー
同士は電気的に絶縁できる。このようにフィードスルー
を形成したウェハ上には、半導体の配線プロセスと同様
にして、ＬＳＩチップとフィードスルー間、ＬＳＩチッ
プ同士を接続する配線１２、ＬＳＩチップ１をフェ−ス
ダウン・ボンディングするための電極】−３゜ＬＳＩの
テストするために信号を人力したり［ｓｔｙしたりする
ためのｆｆ１ｔ４１４を形成する。一方、ウェハの裏面
は、フィードスルーの開口部以外には絶縁膜をつけ、そ
の上でフィードスルーに電極１５をつける。この電極１
５とパッケージのピン５は、ウェハのソリやウェハとパ
ンケージのセラミック基板の熱膨張差を吸収するために
コネクタ６を介して接続する。本実施例ではコネクタ６
は絶縁体であるゴムに多数の細い金属線１６を埋めこん
だものであり、電極１５とピン５の台座を１本以上の金
属線１６に接触させて接続する。接続をより確実にする
ために、電極１５と金属線１６、ピンの台座と金属線１
６の間をハンダ接続するようにしてもよい。January, 1984 (IEEE Trans, Com
puter, Vo Q, C-3:3 r & I
IJan, 1984) pp-6981. The feedthrough 11 becomes P type for the N type wafer substrate,
By providing the highest t-position to the wafer, the feedthroughs can be electrically isolated from each other. On the wafer with feedthroughs formed in this way, wires 12 for connecting LSI chips and feedthroughs, wirings 12 for connecting LSI chips to each other, and wires for face-down bonding the LSI chips 1 are placed on the wafer in the same manner as in the semiconductor wiring process. [Electrode]-3° Forms ff1t414 for manually inputting signals and [sty] for testing LSI. On the other hand, on the back side of the wafer, an insulating film is applied to areas other than the openings of the feedthroughs, and an electrode 15 is applied to the feedthroughs thereon. This electrode 1
5 and the pins 5 of the package are connected via a connector 6 in order to absorb the warping of the wafer and the difference in thermal expansion between the wafer and the ceramic substrate of the pancage. In this embodiment, the connector 6
A large number of thin metal wires 16 are embedded in rubber, which is an insulator, and the electrode 15 and the base of the pin 5 are connected by contacting with one or more of the metal wires 16. To make the connection more secure, the electrode 15 and the metal wire 16, the pin base and the metal wire 1
6 may be connected by soldering.
第３図は本発明の他の実施例のマルチチップ・モジュー
ルの断面の拡大図である０本実施例においてはモジュー
ル基板２であるウェハを貫通するフィードスルーは異方
性エツチングにより錐状の穴２１をあけ、内面に絶縁［
１１２３をつけ、低融点金属２５を充填して形成する。FIG. 3 is an enlarged cross-sectional view of a multi-chip module according to another embodiment of the present invention. In this embodiment, the feedthrough penetrating the wafer, which is the module substrate 2, is formed into a conical hole by anisotropic etching. Open 21 and insulate the inside [
1123 and filled with low melting point metal 25.
これをコネクタのメスとするためにモジュール基板２と
同じ材質のウェハ２２を用い、錐状の穴２１と同じ位置
に柱状のスルーホール２４を異方性エツチングにより形
成してモジュール基板２と接着し、カップ状リセプタク
ルとする。一方、パッケージのセラミック基板４にはマ
イクロピン２６を立て、カップ状リセプタクルに充填し
た低融点金属ボールの中に挿入した後、低融点金属を溶
融させて接続する。In order to make this a female connector, a wafer 22 made of the same material as the module board 2 is used, a columnar through hole 24 is formed at the same position as the conical hole 21 by anisotropic etching, and the wafer 22 is bonded to the module board 2. , a cup-shaped receptacle. On the other hand, micro pins 26 are erected on the ceramic substrate 4 of the package, inserted into low melting point metal balls filled in a cup-shaped receptacle, and then connected by melting the low melting point metal.
ウェハのそりはカップ状リセプタクルの柱状の部分で吸
収し、ウェハとパッケージのセラミック基板の熱膨張差
はマイクロビンの弾性により吸収する。マイクロビン２
６とパッケージのピン５はスルーホール２７により接続
する。本実施例ではセラミック基板４の表面にピン５を
立てたが、第２図の実施例のようにセラミック基板を貫
通するピンを用い、マイクロビン２６とピン５の接続を
セラミック基板４上の配線により行ってもよい。Warpage of the wafer is absorbed by the columnar portion of the cup-shaped receptacle, and the difference in thermal expansion between the wafer and the ceramic substrate of the package is absorbed by the elasticity of the microbin. Microbin 2
6 and the pin 5 of the package are connected through a through hole 27. In this embodiment, the pins 5 are set up on the surface of the ceramic substrate 4, but as in the embodiment shown in FIG. It may also be done by
以上の説明はマルチチップ・モジュールの場合について
行ったが、第１図から第３図の２が回路の形成された半
導体ウェハ（Ｗ Ｓ Ｉ 、 ＷａｆｅｒＳｃａｌｅ
Ｉｎｔｅｇｒａｔｉｏｎ）である場合にも本発明に含ま
れる。The above explanation has been made for the case of a multi-chip module, but 2 in FIGS. 1 to 3 refers to a semiconductor wafer (WSI, Wafer Scale
Integration) is also included in the present invention.
本発明によれば、モジュール基板として安価な半導体ウ
ェハを用いることができ、しかもウェハを貫通するフィ
ードスルーを形成して、短い配線距離でパッケージのピ
ンに接続することにより。According to the present invention, an inexpensive semiconductor wafer can be used as a module substrate, and moreover, feedthroughs passing through the wafer are formed and connected to pins of a package through a short wiring distance.
モジュールの入出力での遅延時間の増大を防止し、クロ
ストーク・ノイズの発生を少なくできる。This prevents the delay time from increasing at the input and output of the module and reduces the occurrence of crosstalk noise.
第１図は本発明の実施例のマルチチップ・モジュールの
断面図、第２図、第３図はモジュールノに板とパッケー
ジのピンを接続する部分の拡大図である。
１・・・ＬＳＩチップ、２・・・モジュール基板（半導
体ウェハ）、３・・・ハンダ・バンプ、４・・・パッケ
ージ基板、５・・・ピン、６・・・コネクタ、１１・・
・フィードスルー、１２・・・ＬＳＩチップとフィード
スルー間やＬＳＩチップ同士を接続する配線、１５・・
・電極。FIG. 1 is a sectional view of a multi-chip module according to an embodiment of the present invention, and FIGS. 2 and 3 are enlarged views of a portion where pins of a board and a package are connected to the module. DESCRIPTION OF SYMBOLS 1... LSI chip, 2... Module board (semiconductor wafer), 3... Solder bump, 4... Package board, 5... Pin, 6... Connector, 11...
・Feedthrough, 12... Wiring that connects LSI chips and feedthroughs or between LSI chips, 15...
·electrode.
Claims (1)
マルチチップ・モジュール、または回路が形成された半
導体ウェハを実装するモノリシックＷＳＩモジュールに
おいて、上記半導体ウェハ上の配線を半導体ウェハの裏
面の電極まで導くフィードスルーを設け、該半導体ウェ
ハの電極とパッケージのピンを接続するコネクタを有す
る半導体集積回路モジュール。 ２、上記コネクタとして非等方電導性ゴムを用いる特許
請求の範囲第１項記載の半導体集積回路モジュール。 ３、上記半導体ウェハの裏面から錐状の穴をあけて半導
体ウェハ上の配線と接続し、錐状穴と同じ位置に柱状穴
を持つウェハとはり合わせることにより、この穴に低融
点金属を充填してコネクタのメスとして用い、パッケー
ジに立てたマイクロピンと接続するようにした特許請求
の範囲第１項記載の半導体集積回路モジュール。[Claims] 1. In a multi-chip module in which one or more LSI chips are mounted on a semiconductor wafer, or in a monolithic WSI module in which a semiconductor wafer on which a circuit is formed is mounted, wiring on the semiconductor wafer is connected to the semiconductor wafer. A semiconductor integrated circuit module having a feedthrough leading to an electrode on the back surface of the semiconductor wafer and a connector for connecting the electrode of the semiconductor wafer and the pin of the package. 2. The semiconductor integrated circuit module according to claim 1, in which the connector is made of anisotropically conductive rubber. 3. Drill a conical hole from the back side of the semiconductor wafer, connect it to the wiring on the semiconductor wafer, and fill this hole with a low melting point metal by gluing it together with a wafer that has a columnar hole at the same position as the conical hole. 2. The semiconductor integrated circuit module according to claim 1, wherein the semiconductor integrated circuit module is used as a female connector and is connected to a micro pin erected on a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21233985A JPH0744243B2 (en) | 1985-09-27 | 1985-09-27 | Semiconductor integrated circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21233985A JPH0744243B2 (en) | 1985-09-27 | 1985-09-27 | Semiconductor integrated circuit module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6273651A true JPS6273651A (en) | 1987-04-04 |
| JPH0744243B2 JPH0744243B2 (en) | 1995-05-15 |
Family
ID=16620900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21233985A Expired - Fee Related JPH0744243B2 (en) | 1985-09-27 | 1985-09-27 | Semiconductor integrated circuit module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744243B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5424573A (en) * | 1992-03-04 | 1995-06-13 | Hitachi, Ltd. | Semiconductor package having optical interconnection access |
| US5485039A (en) * | 1991-12-27 | 1996-01-16 | Hitachi, Ltd. | Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface |
| US6784540B2 (en) * | 2001-10-10 | 2004-08-31 | International Rectifier Corp. | Semiconductor device package with improved cooling |
| JP2014192148A (en) * | 2013-03-28 | 2014-10-06 | Ebara Corp | Vacuum feed-through and vacuum device |
| CN106972095A (en) * | 2017-05-26 | 2017-07-21 | 厦门市东太耀光电子有限公司 | A kind of LED wafer structure |
-
1985
- 1985-09-27 JP JP21233985A patent/JPH0744243B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5485039A (en) * | 1991-12-27 | 1996-01-16 | Hitachi, Ltd. | Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface |
| US5424573A (en) * | 1992-03-04 | 1995-06-13 | Hitachi, Ltd. | Semiconductor package having optical interconnection access |
| US6784540B2 (en) * | 2001-10-10 | 2004-08-31 | International Rectifier Corp. | Semiconductor device package with improved cooling |
| USRE41559E1 (en) * | 2001-10-10 | 2010-08-24 | International Rectifier Corporation | Semiconductor device package with improved cooling |
| JP2014192148A (en) * | 2013-03-28 | 2014-10-06 | Ebara Corp | Vacuum feed-through and vacuum device |
| CN106972095A (en) * | 2017-05-26 | 2017-07-21 | 厦门市东太耀光电子有限公司 | A kind of LED wafer structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744243B2 (en) | 1995-05-15 |
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