JPS6271319A - Voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To obtain a voltage controlled oscillator with good linearity to a current even at a high frequency by oscillating an emitter multi-type oscillator at a half of a desired oscillation frequency and multiplying (coupling) its output signal and a signal retarding the said output signal by 90 deg.. CONSTITUTION:The addition by an adder 2 is that the level at waveforms of points A, B of transistors (TRs) 101 and 102 is compared and the result is outputted as waveform of point C. The collector waveform of the TR 102 in this case, that is the emitter waveform of a TR 111 is reversed in comparison with the emitter waveform of the TR 110, that is, the collector waveform of the TR 101. There is a phase difference of 90 deg. between the two signals and the output signal of the said adder 2. In multiplying the output signal of the emitter multi-type oscillator 1 with the output signal of the adder 2 by a multiplier 3, a signal having a frequency being twice the oscillated frequency of the emitter multi oscillator 1 is obtained at the output terminal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multi-emitter voltage controlled oscillator suitable for high frequency oscillation.

(Background of the Invention) A conventional multi-emitter voltage controlled oscillator is described as a basic circuit in FIG. 1 of the conventional example of Japanese Patent Application Laid-Open No. 77565/1982. Also, as an applied circuit, it is described in Japanese Patent Application Laid-Open No. 49-859.
It is also described in Publication No. 46. The oscillation frequency f of the voltage controlled oscillator described in these can be expressed as f=i/(4·C−V). Here, C is the oscillation capacitance, ■ is the output amplitude, and i is the current flowing through the oscillation capacitance C. Here, in order to obtain a very high oscillation frequency, it is necessary to reduce the oscillation capacitance C (
(2) and i are constant values). However, when the oscillation capacitance C is made small, the influence of the parasitic capacitance of each element increases, and the linearity of the oscillation frequency f with respect to the current i deteriorates.

[Purpose of the invention]

An object of the present invention is to provide a voltage controlled oscillator that has good linearity with respect to current i even at high frequencies.

[Summary of the invention]

To do this, a multi-emitter oscillator is oscillated at 1/2 of the desired oscillation frequency, and its output signal is multiplied (doubled) by a signal that is further phase-shifted by 90 degrees. The desired oscillation frequency was obtained by

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, 1 is a multi-emitter oscillator, 2 is an adder, and 3 is a multiplier. The emitters of transistors 101 and 102 forming the astable multi-pipe lake have a capacitance of 10
5, and their respective emitters are connected to the collectors of transistors 103 and 104. The bases of transistors 103 and 104 are commonly connected to voltage source 11.
5 and the common emitter is connected to a variable current source 113. The collector of the transistor 101 is a load resistor 10
6 to the power supply Vcc and to the base of transistor 1100. transistor 110
The collector is connected to the power supply ■ec, and the emitter is connected to the constant current source 112 and to the base of the transistor 102. Similarly, the collector of transistor 102 is connected to power supply VCC via load resistor 107 and to the base of transistor 111. The collector of transistor 111 is connected to power supply VCC,
The emitter is connected to constant current source 114 and to the base of transistor 101. And diodes 108 and 109 whose anode side is connected to the power supply VCC
are connected to the bases of transistors 102 and 101, respectively. The emitters of the transistors 101 and 102 are respectively connected to the adder 2, and the output of the multiplier 2 is connected to the multiplier 3.
is connected to the input child of Further, the transistor 110,
The emitters of 111 are each connected to the other input side of multiplier 3.

The configuration has been described above, and now the operation will be explained. Since the operation of the multi-emitter oscillator is well known, it will be briefly described here.

FIG. 2 shows signal waveforms at various parts in the circuit of FIG. 1.

The voltage waveforms at the emitters of transistors 101 and 102 (points A and B, respectively) in FIG. 1 are as shown in FIG. 2 (a) and (b). When these two signals are added by the adder 2, the waveform shown in (c) in the figure is obtained.

However, the addition operation in the adder 2 is not a simple analog addition, but a level comparison between the A point waveform and the B point waveform is performed, and during the period when the level of the A point waveform exceeds that of the B point waveform, the level is high. During the period when the value is below , arithmetic operations such as outputting a low level as a point C waveform are performed.

The emitter waveform of transistor 110 at this time, that is, transistor 10! The collector waveform is the waveform shown in (d) in the figure. Further, the emitter waveform of the transistor 111, that is, the collector waveform of the transistor 102 (transistors 110, 11, and 1 each operate as an emitter follower) has a waveform in reverse phase to the above waveform (d). There is a phase difference of 90'' between these two signals and the output signal of the adder 2. Therefore, the output signal of the multi-emitter oscillator 1 and the output signal of the adder 2 are multiplied by the multiplier 3. When you do this, the output terminal 4 will have a waveform (
As shown in e), a signal having a frequency twice the oscillation frequency of the emitter multi-oscillator 1 can be obtained.

Next, a specific example of a circuit for operating the adder 2 and the multiplier 3 is shown in FIG. In FIG. 3, differential pair transistor 5.
The bases of the transistors 6 are connected to the emitters of the transistors 102 and 101, respectively, and the common emitter is connected to the constant current source 13. The collector of transistor 5 is connected to the common emitter of differential pair transistors 7.8. Similarly, the collector of transistor 6 is connected to differential pair transistors 9 and 1.
0 common emitter. Also, the base of transistor 7.10 is connected to the emitter of transistor 111.
The collector of transistor 102 is connected via the base, and the base of transistor 8.9 is connected to the collector of transistor 101 via the emitter-base of transistor 110.

The collector of transistor 7.9 is connected to load resistor 11.
is connected to the power supply Vcc via the transistor 8.1
The collector of 0 is connected to the power supply vcc via a load resistor 12. The collector connection points of these transistors are respectively output terminals 14 and 15. Next, the operation will be explained. Here, since the circuit of the multi-emitter oscillator l is the same as that shown in FIG. 1, the explanation of its operation will be omitted. At the bases of the differential pair transistors 6.5, there are transistors 1 and 1, respectively.
01.102 emitter waveform (Fig. 2 (a), (b)
) waveform・) is input. Therefore, the current of the difference between (a) and (b) in FIG. 2, that is, the current shown in (c) in the figure, flows through the collector of the transistor 6. At this time, the voltage shown in (d) in FIG. 2 is input to the base of the transistor 9 constituting the upper stage differential switch. Therefore, transistor 6.
While the base of 9 is at a "high level", current flows as shown. Conversely, in the case of “low level”, transistor 7
．． Since the current flows through the path 5, the output waveform of the output terminal 15 becomes the waveform shown in (e) in FIG. At the other output terminal 14, an output waveform having a phase opposite to that shown in (e) in the figure appears.

〔Effect of the invention〕

As described above, according to the present invention, the oscillation frequency of the multi-emitter oscillator may be set to 1/2 of the desired oscillation frequency. Therefore, the oscillation capacitance that becomes a problem when oscillating at a high dark wave number is reduced, and the nonlinearity of the oscillation frequency due to parasitic capacitance can be improved. Furthermore, various performances required of the transistor can also be relaxed.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a basic embodiment of the present invention, Fig. 2 is a waveform diagram showing signal waveforms of each part in Fig. 1, and Fig. 3 is a circuit diagram showing a specific embodiment of the invention. , is. Explanation of symbols 1...Multi-emitter oscillator, 2...Adder, 3
... Multiplier Agent Patent Attorney Akio Namiki GT Diagram Emi Y Fourte Type G11 Ticket No. 211! + (1! N output o = H type

Claims (1)

[Claims] 1) A multi-emitter oscillator including an astable multivibrator configured by coupling the emitters of a first transistor and a second transistor via a capacitor, an adder, and a multiplier. The emitter of the first transistor is connected to one input terminal of the adder, and the emitter of the second transistor is connected to the other input terminal of the adder, and the addition result in the adder is multiplied by the multiplication result. The outputs appearing at the collectors of the first and second transistors constituting the astable multivibrator are input to one input terminal of the multivibrator, and are input to the other input terminal of the multiplier to perform multiplication. A voltage controlled oscillator characterized in that the resulting output from the multiplier is used as an oscillation output. 2) In the voltage controlled oscillator according to claim 1, the adder interconnects the emitters of the third and fourth transistors forming the first differential pair and connects them to a constant current source. The base side of each of the third and fourth transistors is used as an input terminal and is connected to the emitter of each of the first and second transistors constituting the astable multivibrator, and the multiplier is , consisting of fifth and sixth transistors forming a second differential pair, and seventh and eighth transistors forming a third differential pair, and each of the fifth transistor and the sixth transistor A first emitter connection point where the emitters are interconnected and a second emitter connection point where the emitters of the seventh transistor and the eighth transistor are interconnected are used as one input side, and the second emitter connection point is used as one input side. 3. A first base connection point connected to the collector of each of the fourth transistors and interconnecting the bases of the fifth transistor and the eighth transistor, and each of the sixth transistor and the seventh transistor. a second base connection point interconnecting the bases, and the first and second bases constituting the astable multivibrator with
A voltage controlled oscillator characterized in that the voltage controlled oscillator is connected to take in a signal appearing on the collector side of each transistor.