JPS6269B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test circuit, in particular a test circuit for elevator installations.

Previously, in particular, German Patent Application Publication No. 1537379
The safety circuit device disclosed in the publication includes a logic block consisting of two circuits. One of the two circuits has a NAND circuit, and the other circuit includes a NOR element as a logic element.
Two test objects are connected to the inputs of each of the elements, and these test objects are adapted to generate signals of opposite values or anti-equivalent values during normal operating conditions. Further, a plurality of monitor elements are connected in series to the outputs of the two logic elements. A test signal source is connected to the first monitor element among the plurality of monitor elements, and the last monitor element has a logic element that monitors the output signal supplied from the previous monitor element and compares the signal with the test signal. It is connected.

However, the safety circuit device has the following drawbacks. That is, according to this safety circuit device, if a defect occurs in two logic elements at the same time and generates a signal with a value opposite to the value that should occur, or if the input signal from one of the devices under test If a defect occurs in one of the logic elements activated by the input signal at the same time,
Two signals provided by two logic elements may produce values that are opposite to those of the signals that would normally occur. When two defects occur one after another in time, they can be detected by test signals provided by a test signal source and one after the other in time.
However, if defects occur simultaneously, they cannot be detected by the monitor element.

On the other hand, German Patent Application No. 1055782 discloses a safety device for electrically driven elevators. This safety device consists of a test circuit and a control circuit connected in parallel, and one of the two contacts of a plurality of photoelectric relays placed near the door is connected in series to the test circuit and control circuit, respectively. ing. Furthermore, in the test circuit, a test relay is connected in series to each contact, a cutoff relay is connected in parallel to the series circuit of the test relay and photoelectric relay contacts, and in the control circuit, a running relay is arranged in series to each contact.

In this safety circuit, during the test process, the photoelectric relay is first placed in a non-conducting state in order to operate the test circuit. This causes all of the contacts of the test circuit to be conductive and all of the contacts of the control circuit to be non-conductive. Next, when all the contacts of the test circuit become conductive, the test relay is activated, and when the cutoff relay becomes non-conductive, the photoelectric relay becomes conductive again.
The contacts of the photoelectric relay in the control circuit become conductive, and the command relay connected in parallel to the control circuit and the test circuit maintains its self-holding state, completing the inspection of each contact of the photoelectric relay. However, in this inspection of the safety circuit, even if one of the contacts of the photoelectric relay on the control circuit side is welded and does not open, it cannot be detected. As a result, a defective contact photoelectric relay is present, which has the disadvantage that when the light between the light source and the photocell is interrupted, the drive motor is not switched off, which can lead to dangerous operating conditions.

It is an object of the present invention to provide a test circuit which detects and prevents the action of two defects which occur simultaneously at the point of operation of a test process and which can lead to a dangerous operating condition.

The above objective is achieved by the invention, when the outputs of the two logic elements of the two diodes of the monitored circuit have signals of equal value, the logic of the input side of the monitoring circuit is coupled to a control line which shuts down the installation. The elements and the logic elements to be monitored are connected to a test circuit that continuously sends a test signal simulating an error to the two logic elements to be monitored when the entire equipment or portion of the equipment begins operation. This is accomplished by supplying and a timing element with a delay element being connected to a control line or conductor that shuts down the equipment.

Specific examples of the present invention will be described in detail below with reference to the accompanying drawings.

In FIG. 1, the switch circuit of the test circuit is indicated by SK1. The elevator door is composed of an elevator cabin door and a shaft door arranged at the entrance/exit of each floor of the elevator passage. The switch circuit includes contacts G11 and G12 that cooperate with the elevator cabin door to detect whether the elevator cabin door is opened or closed, and information transmitters G11 and G12 that indicate whether the door is closed or opened. are doing. Information transmitter G
11 is connected to one input of a digital logic element V11 of an AND element having two inputs via an information channel IK11 connected to a relay for an elevator drive motor; Transmitter G12 is an information channel IK connected to the elevator drive motor relay.
12 to the input of a digital logic element V12 of the OR element, which has two inputs. A monitor circuit US1 is connected to the outputs of the AND element and OR elements V11 and V12, and this circuit consists of one NOR element V13 and one AND element V14, and each element is connected to two AND elements. It has two inputs connected to the outputs of element V11 and OR element V12. NOR element V13
The outputs of AND element V14 are connected to control line StL and test circuit PS1 through one diode D11 and D12, respectively, which constitute an OR circuit. Test circuit PS1 has three inputs on one side,
The other is an AND element V15 having two inputs.
and V16, a memory device SP11 having two inputs and two outputs, a memory device SP12 having two inputs and one output, and a NAND element V17 having two inputs. In that case, AND
The input of the element V15 is connected to the output of the NOR element V13, the control line StL, and the test line PrL, and the input of the AND element V16 is connected to the output of the AND element V14 and the control line StL. There is. The outputs of the AND elements V15 and V16 are connected to the inputs e1 and e2 of the storage device SP11, and the output a1 of this device is then connected to the inputs e1 and e2 of the storage device SP11.
12 input e1 and OR element V via conductor LSi2
12 inputs. Storage device SP1
Outputs a2 and a1 of SP1 and SP12 are connected to both inputs of NAND element V17.

In Figure 2, positions SK1, US1, PS1, V
11, V12, V13, V14, V15, V1
6, SP11, SP12, V17, D11, D1
2, IK11, IK12, LSi1, LSi2, LSi3,
LQ1, LQ2, PrL and StL indicate the same members as in FIG. SK2, SK3 and SK4 designate switch circuits of the test circuit which together with switch circuit SK1 form a series circuit.
At this time, switch circuits SK1, SK2, SK3 and
SK4 monitor connection US1, US2, US3 and US
4. Furthermore, the test connections PS1, PS2 and PS3 of the switch circuits SK1, SK2 and SK3 are respectively identical. SK2 has an information transmitter (not shown) that cooperates with the shaft doors on each floor and has contacts and the like to detect the opening and closing of each shaft door. This information transmitter is provided corresponding to each shaft door. SK3 serves as an optional monitor for the test circuit of the elevator equipment, although not described in detail. In switch circuit SK4, switch circuit SK1
As a result, the information from to SK3 is collected into one piece of information. In the switch circuit, the respective outputs of NAND elements V17, V27, V37 of the front switch circuit are connected to digital logic elements V21, V3 of the rear switch circuit via conductors LSi3, LSi5, LSi7.
1, are connected in series to be connected to the input of V41. Switch circuit SK2, SK3, SK4
Input a1 of storage device SP21, SP31, SP41
is connected to the memory device SP1 of the front switch circuits SK1, SK2, SK3 via conductors LQ2, LQ3, LQ4.
2, connected to input e2 of SP22 and SP32.

The storage device SP0 is placed outside the switch circuit and has two inputs and one output.
A conductor connected to the elevator stop floor instruction button via the equipment control device at input e1
LSi0 and input e2 are respectively connected to output a1 of storage device SP11 (FIG. 1) via conductor LQ1. On the other hand, the output a1 of the storage device SP0 is the conductor wire where the NOT element VO is arranged.
After passing through LSi1, digital logic element V11 (first
(Figure) is connected to the second input.

Input e1 of storage device SP42 of test circuit PS4
is connected to the conductor LSi0 through the conductor LSi0', and the output a1 of the device is an OR with two inputs.
It is connected to one input of element V47. OR
The output of element V47 is connected to an inhibition line SpL which is connected to a relay for the elevator motor via a test line PrL and a control device of the equipment. The input e2 of the storage device SP42 is connected to the output a1 of the storage device SP41 and the second input of the OR element V47. A timing element ZG, which is arranged outside the switch circuit and is equipped with closing delay means, is connected on the input side to the control line StL and on the output side to the control device of the device.

Information channels IK11/12, IK21/22 and IK3 of switch circuits SK1, SK2 and SK3
1/32 is connected to the input of a digital logic element of the switch circuit SK4, the output of which is connected on the one hand to the input of the monitor connection US4 and on the other hand to the information channel connected to the relay for the elevator drive motor. It is connected to the equipment control means via IK41/42.

The above safety circuit operates as follows.

When the elevator cabin is stopped and the elevator cabin door is closed, the information transmitter G11 sends a signal 1 to the AND element V11, and the information transmitter G12 sends a signal 0 to the OR element V12. The signal 0 supplied by the control device connected to the elevator cabin is connected to the conductor LSi0 (second
) and reaches the input e1 of the storage device SP0,
The output a1 of the device therefore likewise has a signal 0. NOT element placed inside conductor LSi1
Since VO negates this signal, a signal 1 appears at the input of the corresponding AND element V11, so that the output of that element also has a signal 1. From this, the outputs of the NOR element V13 and the AND element V15 have a signal 0, and as a result, the memory device SP11 is not set, and the signal 0 reaches the corresponding input of the OR element V12 via the conductor LSi2, and this element The output of, therefore
The output of AND element V14 also has a signal 0. The control line StL is thus “unbroken”
leads to a signal 0 defined as . During this time, information channel IK11/12 is connected to element V11/12.
have signals of different values at the output. When the wire is disconnected, the control line StL will send signal 1 to stop the equipment.
guide. However, if this signal is short-lived, such as a short-term coincidence of signals from information transmitters,
Timing element ZG prevents equipment from stopping.

Switch circuits SK2, SK3, SK4 operate similarly to switch circuit SK1. At this time, digital logic elements V21/22, V31/32, V
The number of inputs is 41/42 in each case.
corresponds to the number of pieces of information to be processed, and the element V1
Signals 1 and 0 in the conductor LSi1/2 of the switch circuit SK1, which acts to lead to 1/12, pass through the conductors LSi3/4, LSi5/6, and LSi7/8 to the elements V21/22, V31/32, and V41. /42 to the corresponding input.

Input e1 of storage devices SP41 and SP42 is signal 0
Since the output a1 and the output of the device are
The output of NOR element V47 likewise has a signal 0. Test line PrL and inhibition line
SpL therefore leads to a test signal 0 and a signal 0 defined as "start of operation".

When all switch circuits are working properly, the channel
Signals with different values appear on IK41/42. Channels 41/42 are connected to the control system of the installation, ie to the relay for the elevator drive motor, so that when different values appear, the test process is terminated and the motor can be started.

At the start of operation, the stop floor is instructed by the stop floor instruction button, and after the shaft door has closed and just before the elevator cabin door closes,
A signal 1 is applied to the conductor LSi0 by the control means of the installation to test the safety circuit. This signal sets memory devices SP42 and SP0. After this, a signal 1 appears at the output of OR element V47. This signal inhibits activation of the elevator motor relay via the inhibition line SpL during the test process and is supplied via the test line PrL to the switch circuits SK1 to SK4. Output a of storage device PS0
Similarly, a signal 1 appears at 1, and this signal is connected to the conductor LSi
1 and the NOT element V0, and reaches the corresponding input of the AND element V11 as a signal 0. As a result,
The outputs of AND element V11 and NOR element V13 have signals 0 and 1, and all three inputs of AND element V15 have signal 1. At that time, diode D
12, both inputs of AND element V16 are also signal 1
prevent the occurrence of Thus storage device SP
11 is set, so that the signal 1, on the one hand, via the conductor LQ1 resets the storage device SP0, and on the other hand, via the conductor LSi2, reaches the corresponding input of the OR element V12. As a result, the output of the element and
Furthermore, since the output of the AND element V11 already has the signal 1 due to the reset of the memory device SP0, the output of the AND element V14 also has the signal 1. There is also a signal 1 at both inputs of AND element V16. As a result, the memory device SP11 is reset and a signal 1 appears at its output a2.
Diode D11 then prevents the device from being set again. Storage device SP12
Since the output a1 of also has the signal 1,
The signal 1 at the output of NAND element V17 changes to signal 0. This signal 0 is further conducted via the conductor LSi3 to the switch circuit SK2, in which the same process as in the switch circuit SK1 is then repeated. That is, if the shaft doors on each floor are closed at the time of inspection, a signal 1 is sent to each input of the AND element V21 of SK2 from each information transmitter that cooperates with each shaft door and detects the opening and closing of the shaft door. A signal 0 is sent to each input of the OR element V22 of SK2 from each of the information transmitters that detect the opening/closing of the shaft door. If all shaft doors are closed and normal, SK1
The signal 1 at the output of the NAND element V27 changes to the signal 0 through the same process that occurred in the circuit of SK1 by the signal 0 sent by the LSi3 from the NAND element V17. This signal 0 passes through the conductor and further
Guided by SK3.

The same process as SK1 and SK2 is repeated in SK3 as well.

After setting the storage device SP41 in the switch circuit SK4, the storage device SP42 is reset, and the storage device SP of the switch circuit SK3 is reset via the conductor LQ4.
32 is also reset. At the same time, OR element V47
The signals 1 and 0 at both inputs change to 0 and 1, so lines PrL and SpL still have a signal 1. Only after the reset of the storage device SP41, the output of the OR element V47 has a signal 0, which ends the test process and starts the operation.

In the event of a fault, the safety circuit device operates as follows.

It is assumed that both digital logic elements V11 and V12 of the switch circuit SK1 become defective at the start of operation, either one behind the other or at the same time. Element V1 connected to information transmitters G11 and G12
1, the inputs of V12 have signals 0 and 1.
Via the conductor LSi1, the test signal 0 reaches the second input of the AND element V11, so that this AND element 11
The output of will also have a signal 0. However, assume that the output has a signal 1 due to a defect. Since the second input of OR element V12 has the signal 0, its output is "1". Now assume that due to a defect the output still has a "0". Since the output of the NOR element V13 therefore has a signal 0, the memory device SP11 cannot be set and the signal 1 is passed through the conductor LSi2 to the OR element V
It doesn't reach 12. Since the output of the AND element V14 and the output a2 of the storage device SP11 each have a signal 0, no change in the signal state is recognized at the output of the NAND element V17, and therefore, the test signal is sent to the switch circuit SK2 via the conductor SLi3. is not communicated. For this reason, switch circuit SK4 is connected via conductor LSi7.
As a result, the test signal does not reach the storage device.
SP41 and SP42 are not reset and the line SpL
subsequently provides a signal 1 which controls the activation of the relay for the elevator motor.

Furthermore, diode D12 of switch circuit SK1
Assume that a defect occurs in the flow path and the flow does not flow in either the pass-through direction or the inhibition direction. During the test process, if the inputs of elements V13 and V14 have a signal 1, a signal 0 appears at the output of NOR element V13 and a signal 1 appears at the output of AND element V14. There are therefore signals 0 and 1 at both inputs of the AND element V16, so that the output of the element has a signal 0. For this reason, storage device SP11
cannot be reset, and no signal change occurs at the output of NAND element V17. The test signal is therefore not conducted further, so that the line SpL also carries a signal 1 which suppresses the activation of the relay for the elevator motor.

As another example, the digital logic element V2 that the monitor connection US2 of the switch circuit SK2 has
3. Assume that both V24s are defective at the start of operation, either one behind the other or at the same time. The inputs of elements V21, V22, which are connected to the information transmitter of the safety gate (not shown), have signals 1 and 0 when the safety gate is closed. After testing the switch circuit SK1, which is free from defects and is connected to the elevator cabin door, the conductor LSi3
The test signal 0 reaches the corresponding input of the AND element V21, so that the output of the AND element V21 has the signal 0. Since no test pulse has yet reached the corresponding input of OR element V22 via conductor LSi4, its output also has a signal 0. In this way, the output of NOR element V23 is "1", and the output of AND element V2
The output of 4 has a "0". It is assumed here that, due to a defect, a signal with a value opposite to the value that should appear at the output appears. Therefore, the storage devices SP21 and SP22 connected via the AND element 25 cannot be set, and the input of the NAND element V27 connected to the output a23 of the storage device SP22 still has the signal 0. No further test signal is introduced since no change in the signal is therefore observed at its input. Therefore, the storage device of switch circuit SK4
SP41, SP42 cannot be reset, so that line SpL carries a signal 1 which inhibits activation of the relay for the motor. As another example, in an elevator safety device, one of the contacts of a photoelectric relay
The A and B contacts of each photoelectric relay have two sets of contacts that operate even if the relay cannot open due to welding.
By connecting information transmitters G11 and G12 to the contacts and generating signals of different values, it is possible to test whether the operation of each photoelectric relay is always normal by operating the circuit.

The invention is not limited to the illustrated embodiment, but also includes other possible implementation variants. Therefore,
For both digital input logic elements V11 and V12, the AND element and the OR element are replaced with the NOR element and
The NOR element and the AND element may be replaced by an OR element and a NAND element for both logic elements V13 and V14 of the monitor circuit US1. Furthermore, the entire circuit may be constructed using NOR technology or MOS theory with self-closing MOS FETs.

As a result of having the above configuration, the present invention inspects the switch circuit after receiving an instruction to start operation,
Even if two failures of information communication devices, etc. in the safety equipment and their attached parts occur at the same time, it is possible to detect these two defects and prevent their effects.

[Brief explanation of the drawing]

FIG. 1 is a power distribution diagram of a switch circuit of an elevator equipment test circuit, and FIG. 2 is a power distribution diagram of a test circuit having a plurality of switch circuits. SK...Switch circuit, G...Information transmitter, IK
...Information channel, V...Logic element, SP...Storage device.

Claims (1)

[Claims] 1. A first AND element V11 having an input connected to an information transmitter G11 and another information transmitter G1
an OR element V12 having an input connected to
A NOR element V13 having an input connected to the output of the first AND element V11 and another input connected to the output of the OR element V12, and an input and an OR element connected to the output of the first AND element V11. V
a second having inputs connected to twelve outputs, respectively;
AND element V14, OR circuits D11 and D12 each having an input connected to the output of the NOR element V13 and another input connected to the output of the second AND element V14, and an output of the NOR element V13. a third AND having connected inputs and inputs connected to the outputs of OR circuits D11 and D12, respectively;
element V15, an input connected to the output of the second AND element V14, and the OR circuit D11, D.
a fourth AND element V16 and a third AND element V15, each having another input connected to the output of 12;
input and a fourth AND element V connected to the output of
16 outputs, respectively, and when the signals supplied to the two inputs of the third AND element V15 satisfy the AND condition, the signal generated from the third AND element V15. is reset by a signal generated from the fourth AND element V16 when the signal set by the signal generated by the fourth AND element V16 and supplied to the two inputs of the fourth AND element V16 satisfies the AND condition; Two outputs a1 and a send out signals indicating these set and reset states.
2, the first storage element SP11 has
A second storage element SP12 has an input e1 connected to the output a1 on the set side of the storage element SP11, and is set by a signal indicating the set state of the first storage element SP11; It has an input connected to the reset side output a2 of the memory element SP11 and another input connected to the set side output a1 of the second memory element SP12.
The first memory element consists of a NAND element V17.
The output a1 on the set side of SP11 is the OR element V12.
is connected to one other input of the first
A test circuit characterized in that the test circuit is configured such that a test start signal is supplied to another input of the AND element V11. 2 a first having an input connected to an information transmitter;
AND elements V11, V21, V31 and an OR element V1 having an input connected to another information transmitter
2, V22, V32 and the first AND element V1
1, the inputs connected to the outputs of V21, V31 and
NOR elements V13, V having other inputs connected to the outputs of OR elements V12, V22, V32, respectively
23, V33 and the first AND element V11, V2
1, a second AND element V14, V2 having an input connected to the output of V31 and another input connected to the output of the OR element V12, V22, V32, respectively;
4, V34, and the NOR elements V13, V23,
input connected to the output of V33 and the second AND
OR circuits D11 and D12 with other inputs connected to the outputs of elements V14, V24 and V34, respectively;
and input and OR circuits D11 and D12 connected to the outputs of the NOR elements V13, V23, and V33.
a third each having another input connected to the output of
AND elements V15, V25, V35, and the second
A fourth circuit having inputs connected to the outputs of the AND elements V14, V24, and V34 and other inputs connected to the outputs of the OR circuits D11 and D12, respectively.
AND elements V16, V26, V36 and the third
Inputs connected to the outputs of AND elements V15, V25, V35 and fourth AND elements V16, V2
6, V36, respectively, and the third AND elements V15, V25, V
The signals supplied to the two inputs of 35 are AND
When the condition is satisfied, the third AND element V15,
It is set by the signals generated from V25 and V35, and the fourth AND element V16, V26, V3
When the signals supplied to the two inputs of V6 satisfy the AND condition, the fourth AND element V16, V
26, a first storage element having two outputs which are reset by signals generated from V36 and which send out signals indicating these set and reset states;
SP11, SP21, SP31 and the set side output a of this first storage element SP11, SP21, SP31
1 and a second storage element SP12, SP22, SP32 which is set by a signal indicating the set state of the first storage element SP11, SP21, SP31; The input connected to the reset side output a2 of elements SP11, SP21, SP31 and the second storage element SP1
2, a NAND element V17 having other inputs connected to the set side output a1 of SP22 and SP32, respectively;
V27 and V37, and the first memory element
Output a1 on the set side of SP11, SP21, SP31
is connected to the other input of OR elements V12, V22, V32, and the first AND element V1
A plurality of test circuits SK1, SK2, and SK3 configured such that a test start signal is supplied to one input of V1, V21, and V31, and another test circuit SK.
4, and the other test circuit SK4 includes the first AND elements V11, V21,
Another first AND element V41 having a plurality of inputs respectively connected to the output of V31, and another OR element having inputs respectively connected to the outputs of the OR elements V12, V22, V32 of the plurality of test circuits. V4
2, and another NOR element V43 having an input connected to the output of the other first AND element V41 and an input connected to the output of the other OR element V42, respectively.
, another second AND element V44 having an input connected to the output of the other first AND element V41 and another input connected to the output of the other OR element V42, and another NOR element V43. and an input connected to the output of the other second AND element V44, respectively.
1 and D12, and another third circuit having an input connected to the output of another NOR element V43 and another input connected to the output of the other OR circuit D11, D12, respectively.
AND element V45 and another second AND element V4
input connected to the output of 4 and another OR circuit D1
1, another fourth AND element V46 having other inputs connected to the outputs of D12, and another third AND element V46 having other inputs connected to the outputs of
It has an input connected to the output of AND element V45 and another input connected to the output of another fourth AND element V46, and is supplied to two inputs of another third AND element V45. When the signal satisfies the AND condition, the other third AND element V45
set by a signal generated from another fourth
When the signals supplied to the two inputs of the AND element V46 satisfy the AND condition, the other fourth AND
It is reset by a signal generated from element V46 and is connected to another first storage element SP41 having an output for sending out a signal indicating a set state, and to the output a1 of this other first storage element SP41. input e2, and this other first storage element
Another second storage element SP42 that is reset by a signal indicating the set state of SP41, an input connected to the output of the other first storage element SP41, and the set side of the other second storage element SP42 Output a
a third OR with each other input connected to 1
element V47, and another first memory element SP
The set-side output of 41 is connected to another input of another OR element V42, and the plurality of test circuits are connected to the NAND elements V17, 41 of the preceding test circuit.
The output of V27 is connected to the other inputs of the first AND elements V21 and V31 of the subsequent testing circuit, and the output of V27 is connected to the other inputs of the first AND elements V21 and V31 of the subsequent testing circuit.
The set side outputs of SP21 and SP31 are connected to the second memory element SP1 of the front test circuit in order to reset the second memory elements SP12 and SP22 of the front test circuit.
2. It is connected to the reset side input of SP22, and the output of the NAND element V37 of the final stage test circuit in the plural test circuits connected in series is the output of the first AND element V41 of the other test circuit SK4. The set side output of the other first storage element SP41 of the other test circuit SK4 is connected to the other input.
Second storage element SP32 of the final stage inspection circuit
An inspection device characterized in that it is connected to an input on the reset side of the test device. 3. The input e1 on the set side of the other second memory element SP42 of the other inspection circuit SK4 is connected to the other second memory element SP42 when the equipment starts operating.
The output of the third OR element V47, which is connected to the conductor LSi0 inducing a signal to set the test circuit, and which outputs a signal to inhibit operation during the test process, is connected to the conductor LSi0 which is inducing a signal to set the The output of the third OR element V47 is connected to the other inputs of the third AND elements V15, V25, V35 and the other input of the third AND element V45 of the other test circuit SK4. , other first and second storage elements
3. The inspection device according to claim 2, wherein when SP41 and SP42 are reset, the transmission of the signal for suppressing the equipment is stopped.