DE2842370A1 - Signal processor monitoring system - uses two processing stages operating with cycle monitoring stages - Google Patents

Abstract

A monitoring system is used for a processor. It is based upon two synchronised branch cycles, and it is fully interlocked to detect any erroneous state. The two processing units receive separate inputs from clock generator stages. The main unit responds with an output to cause a bistable device to switch. A second bistable device receives the output and switches dependent upon the secondary stage. The status of the branch operations is determined by coincidence detectors.

Description

Circuit arrangement for monitoring the workflow

a signal processing unit.

The invention relates to a circuit arrangement for monitoring the flawless processing sequence to be effected on the basis of a supplied input signal in at least. -one of two possible branches, at least one of which is one Contains processing unit, with the last processing step a corresponding End signal is generated and the input signals simultaneously or in any temporal offset to each other occur and the single input signal is the criterion for the processing order of the other input signal in the second processing branch contains, and for the monitoring one of the signals of both branches in their switching state variable tilting stage is used.

The ones contained in the two or only in one processing branch Unit can, for example, be a unit for staggering a cycle that has been supplied be. This yon clock can be used for one processing branch / an operating clock generator and the functions for the other processing branch in the event of a fault the replacement clock taking over the operating clock will be delivered. That one The signal supplied to the branch can only be used as a reference signal without further processing can be used.

In connection with the generation of clock signals, it is known the clock pulses emitted by two separate clock generators to monitor the functionality to compare the two clocks with each other.

With such a monitoring an error is reported, as well as a Deviation in the frequency or in the phase position of the pulses of one pulse train occurs in relation to the pulses of the other pulse train.

There is also a monitoring device for several pulse sources known, in which the pulses from each 2 pulse source the two control inputs be fed to a bistable multivibrator. Their exit is direct or via further bistable multivibrators, which create the decoupling to other pulse sources, connected to an alarming device. There are impulses with each other compared, which occur coincidentally with trouble-free operation. Is this due to a disturbance is not the case, the duty cycle of those changes bistable multivibrators emitted signals to which these pulses have been fed are such that the presence of an error is reported.

In known monitoring circuits in which a minimum of effort aimed at with regard to the components to be used for the monitoring, the problem arises that certain defective states of individual components result in a permanent approval. In these cases there is no error signaling more possible in the event of a malfunction of the facility to be monitored.

It is the object of the invention to specify a monitoring circuit, with the least effort also a self-monitoring of the used for this Blocks in connection with a corresponding error signaling is possible.

In an arrangement of the type mentioned at the beginning, this is achieved by that both the output which is signaling in the idle state and the output which is not signaling a clock-controlled bistable toggle stage, each with an input of a coincidence element is connected, of which the coincidence element connected to the first-mentioned output via the other input with the end signal of the processing unit of the first Branch and the coincidence element connected to the output that does not carry the signal is applied directly to the input signal fed to the second branch, that the output of each coincidence element is a perceptible error registration causing the error message signal that the set input of the flip-flop through an immediately upon termination of the input signal mentioned or upon termination of the respective end signal of a processing unit additionally present in this branch derived signal is applied that the clock input of the flip-flop with the not signal-carrying in the idle state Output of another clock-controlled bistable flip-flop is connected, the set input of which is supplied to the first branch Input signal and its clock input with the end signal of the processing unit this branch is acted upon.

The processing unit contained in the two or in each case only in one processing branch is therefore according to the invention with regard to their input signals and their output signals supervised. It can therefore be recognized whether a control signal is missing or a for the processing unit predetermined timing not up to his The end is carried out. With a minimum of effort, the arrangement is made so that that the units used directly for monitoring in the form of Flip-flops can also be monitored for a defect at the same time. It is not Malfunction of a structural unit possible, which results in an unprogram positive statement Has. This is done by connecting the two flip-flops in series and by the query of the two outputs of the output multivibrator. All basic disturbances in the input signal and in the output signal of the processing unit and in the monitoring units lead via the two coincidence elements coupled to the output flip-flop a corresponding fault message.

According to a further development of the invention, this provides for the control the output signal derived from the set input of the bistable output multivibrator one triggered with the pulse end of the input signal fed to the second branch monostable multivibrator.

In this way, the timing of the input impulses affects the two branches are not mutually exclusive. So the one with the back flank of one Input pulse of this flip-flop is set, the downstream can also The input pulse supplied to the coincidence element does not lead to a coincidence.

According to a development of the invention, the input signals represents the impulses of a time cycle.

These input signals are for the first branch from an operating clock and for the second branch from a functionally independent replacement clock generator delivered. At least the processing unit of the first branch is one supplied pulse in each case staggering unit, whose with the last Graduated pulse generated represents the end signal. The processing unit of the second branch can be a similar staggering unit, which is then used as a substitute takes over the function of the processing unit in the first branch, or this processing unit can be omitted. Then each pulse is used by the replacement clock for this branch delivered time cycle as a reference signal for monitoring.

In those cases where the staggering unit with the one on the last The impulse arising in the staggered step is initially to be switched ineffective According to a further development of the invention, it is checked whether this deactivation is actually made or whether the grading unit is constantly a Makes graduation. This is achieved in that the one with a coincidence-ed connected output of the bistable output multivibrator with one input of a Another coincidence element is connected, the other input with a graduation step lower atomic number is connected. Will the staggering with the last If the step is not stopped, it will be wired in the above-mentioned way when it is reached Output step, a corresponding error display is issued via the coincidence element.

An exemplary embodiment of the invention is shown in the drawing.

1 shows a block diagram for carrying out the inventive Monitoring FIG. 2 shows a pulse diagram at various circuit points in the undisturbed Case and switching states occurring in certain malfunctions.

It is assumed for the exemplary embodiment according to FIG. 1 that that the input signals to be processed in the two branches Z1 and Z2 come from one Operating clock generator TG delivering time clocks or from a similarly structured one Replacement ETG clock can be supplied. The one contained in the processing branch Z1 Unit ST is intended to stagger each pulse from the operating clock TG given specific timing serve. It takes place in this unit thus controlled by the control device SE contained in it serial processing of a every input pulse. That means that with an intended n-fold Graduation at the corresponding outputs S1 to Sn, this graduation unit ST within a period of time that is smaller than the time interval between two successive input pulses one after the other without temporal overlap output pulses develop.

The unit US shown in the processing branch Z2 could be one with the graduation unit ST of the first Branch Z1 matching Be unity. It would then replace this unit in the event of a fault.

In the embodiment of FIG 1, the unit US is one of the Switchover to a unit that is used by the replacement clock generator ETG be. If a switchover is required, this switchover device the clock delivered by the replacement clock without being staggered to the one with the corresponding Clock output lines connected connection points A1 to An applied. These connection points are in normal operation with the outputs S1 to Sn of the staggering unit ST tied together.

In general, the two processing branches Z1 and Z2 present processing units represent arrangements in which any Functions with a chronologically serial sequence can be implemented.

The mode of operation of the embodiment shown in FIG will first be explained for an undisturbed operating case. The im Section A1 of FIG. 2 with respect to individual circuit points shown pulse curve used. Those shown in the individual sections A1 to A6 of FIG Lines a to h show the pulse states associated with those with the same reference numerals a to h provided circuit points in different yet to be explained Malfunctions occur.

In the case of undisturbed operation, these are those in section A1 of FIG 2 pulse states shown. Each pulse of the operating clock TG according to the Line a of the given time cycle sets the corresponding input with its The leading edge is the bistable multivibrator K2. Simultaneously becomes this Impulse of the already explained grading unit contained in the processing branch Z1 ST supplied. The intended graduation of the input pulse supplied carried out properly, appears when the last staggering step is activated Sn a pulse signaling the termination of the graduation. This one is in line f each shown. With this respective end signal, the clock input T1, the flip-flop K2 is reset. The change in the signal state of output Ac then influences the bistable multivibrator K1 via the clock input T2. This tilting stage became with the termination of a pulse of the replacement clock generator ETG according to the line b set time cycle. It is assumed that this timing cycle is synchronous at the clock rate given by the clock generator TG. However, this is not a mandatory requirement Advance dents - setting. That in terms of their effect on the two branches Immediately related impulses of the two time cycles can differ with regard to differ in their duration and they can also be offset in time from one another be. An impulse for the processing branch Z2 only needs at least the statement contain that processing is to be carried out in processing branch Z1. This impulse can therefore also be present before such processing begins.

In the example shown, a synchronous delivery of the individual pulses of the time clocks according to lines a and b of section A1 of FIG Pulse via the unit US directly to the clock input without further processing fed to the monostable multivibrator K3. This delivers triggered by the trailing edge this pulse is a short-term pulse according to line d, through which the flip-flop K1 via the corresponding input gear is set. So she takes at their outputs A7 and A2 the switching position opposite to its initial state a. At the output Al there is thus an output pulse according to line e, which is generated by the Control via the clock input T2 according to line c with the trailing edge of the output signal the flip-flop K2 is ended. The flip-flop K1 is thus with the end of the last Graduated step of the grading unit ST due to the processed in the flip-flop K2 End pulse reset according to line f. With the resetting of the flip-flop K1 thus documents that the staggering of the pulse carried out in the unit ST of a time cycle has been completely executed. Furthermore, there was the corresponding impulse of the time cycle taken from the replacement clock generator ETG is available. The two exits A1 and A2 of the flip-flop K1 are each connected to an input of a coincidence element Gl and G2 connected.

The outcome of each of these coincidence elements leads exclusively in the event of a fault, an output signal which is fed to the unit S1 or S2 and is displayed there. It can also be done at the same time / these arrangements the subsequent functions to be linked directly to the corresponding fault message be initiated.

With the gate G1, which has one input with the one in the output state The signal-carrying output Al of the flip-flop K1 is connected to the other The input immediately corresponds to the respective input pulse for the processing branch Z1 assigned pulse of the time clock taken from the replacement clock generator ETG is supplied. Since, as already mentioned, the flip-flop Kl is set at the end of this pulse, In the case of undisturbed operation, the directly supplied pulse cannot coincide at the two inputs of the gate G1 for Have consequence.

The gate G2, which via the input with the signal-carrying in the output state Output A2 of flip-flop K1 is connected to the other output End signal signaling the completion of a graduation order according to line f applied. Since a signal occurs at output A2 that corresponds to that at output A1 Line e pending signal is inverse, also occurs for these two inputs no such incidence in the control signals. With a proper process thus appear at the outputs of gates G1 and G2 according to lines g and h no output signals.

If there are faults, output signals appear at gates G1 and G2 which then lead to a corresponding error signal. In the sections A2 to A6 of FIG. 2 show the switching states that occur in the event of certain malfunctions occur at the corresponding switching points. What is common to these individuals Diagram sequences that in each case either at the output of G1 or at the output A signal occurs from G2 due to the disorders still to be treated in detail.

Section A2 deals with the case that instead of the time cycle a continuous signal is erroneously emitted by the operating clock. this leads to then to the switching states shown in section A2 according to the lines a to h correspond to circuit points indicative of a. Because of the permanent potential the flip-flop K1 is not reset, so that according to line e there is always an output potential is present at the output Al. This is the same as that shown in the diagram second Pulse fulfills the coincidence condition for gate G1, so that according to line g an output pulse arises. This then leads to error signaling.

Because of the fixed static made on the basis of the continuous signal The control of the set input of the flip-flop K2 is the clock pulse at its clock input TR ineffective so that the flip-flop K2 remains set.

This means that flip-flop K1 cannot be reset. In the one described In this case, the unit S1 processing the error signal sends a command to switch over delivered on a replacement cycle. This switchover command U is transmitted via the graduation unit ST fed to the switchover unit US. As a result, in the exemplary embodiment of delivered to the replacement clock and which correspond to the failed clock Timing is switched on immediately in phase at the connection points Al to An. The clock output lines connected to these connection points are thus continues to be supplied with a non-staggered clock as an alternative.

In section A3 of the timing diagram according to FIG. 2, the relationships are shown, which result if there is no time cycle from the operating clock generator due to a fault TG is released. This means that the flip-flop K2 is not set and thus no output signal arises at its output according to line c of this diagram section. The flip-flop K1, which starts with the trailing edge of the replacement clock according to line b delivered pulse is set with the output signal of the multivibrator K3 according to line d is therefore not reset. At their exit is therefore in accordance with Row e is a permanent potential. This leads to the gate G1 with the subsequently released Pulse of the substitute clock for the coincidence of the input signals.

The resulting output signal according to line g is in turn the this signal processing device S1 supplied. It will be in the same way as this was explained for the error case relating to section A2, a switchover command generated, whereby the connection points A1 to An to the switching through the substitute clock Line SO / not shown in any further way are switched on.

In section A4 of the diagram according to FIG. 2, lines a to h shows those switching states that are at the correspondingly designated switching points in the event that, as a result of a fault, the replacement clock generator ETG accordingly line b does not provide any pulses for the specified time output.

Because, as can be seen in section A4, at the switching points d and e no signals' arise, is to be compared with the the end of processing in the staggering unit signaling the impulse The coincidence condition for the gate G2 is met, since there is accordingly a permanent potential at the output A2 pending. With the output signal of the gate G2, the mentioned type of error of the device S2 signals. This can then lead to a corresponding display. Since he recognized Error does not affect the basic functions, is the one already described Switching not required.

In the diagram section A5 of FIG 2, those relationships are shown, which then result at the circuit points a to h of FIG an input signal for the grading unit St delivered graduation order not fulfilled will. This means that due to the incomplete processing of the input signal an end signal is not generated in this unit will. The switching point So f remains potential-free according to line f of diagram section A5. Through the The time cycle according to line a, the flip-flop K2 was set.

The flip-flop was created in the same way via the monostable flip-flop K3 K1 is set by the pulse of the substitute clock. Since the last relay step as a result of an error in the processing unit ST is not executed, both remain the tilt stage K1 as well as the tilt stage K2 in the set position. This gets over the output G1 with the next pulse of the existing substitute clock an error signaling made to unit S1. This in turn leads to what has already been described Way to connect the non-staggered clock cycle to be created as an alternative the connection points A1 to An. In section A6 those switching states are shown, which occur at the switching points a to h when due to an error from the replacement clock generator ETG according to line b instead of the individual pulses a continuous cycle is emitted. As a result, the flip-flop K1 is not set, so that there is no signal at its output A1 and thus at one input of the gate G1. Since output A2 assumes the initial state which is the inverse of output A1, this leads to according to line f with the completion of the processing operation in the unit ST End signal for the coincidence of the input information for gate G2. It arises accordingly, according to line h, an output signal that of the one that registers this disturbance Unit S2 is supplied.

With the coincidence gates G3 and G4 shown in FIG two other types of errors can be registered. Gate G3 is over the one Input connected to output A2 of flip-flop K1. The other one corridor leads to an output corresponding to a grading step with a lower ordinal number the grading unit ST. Let this be output S3, for example.

At the end of a processing sequence due to an input pulse As already mentioned, the flip-flops K2 and K1 are in their idle state State reset. It is now assumed that with the output end signal at the same time, for reasons that cannot be explained in more detail, the graduation unit becomes ineffective is switched. This ineffective switching should then only be repeated with a subsequent one Impulse of a clock pulse can be canceled. If this ineffective switching is disturbed, this would be the case with the immediately following and internally generated Pulses triggered the second run of the graduation unit with the third graduation step the resulting output signal sets the coincidence condition for the gate G3 must be met.

This could be done by a unit S3 that registers this type of error the resulting output signal can be communicated. This in turn can then be the switchover on the clock to be connected to the connection points Al to An as an alternative Have consequence.

At the output of the coincidence gate G4 there is always an output pulse, if double impulses occur at the outputs of the staggering unit ST. For example, arise incorrectly overlapping pulses at the outputs S1 and S2, thus, coincident ones occur at the inputs of the gate G4 connected to these outputs Impulses. This then leads to a corresponding output signal, which in the same Way like the output of the coincidence gate G3, for example the unit S3 can be fed.

The flip-flops K1 and K2, which enable a monitoring function are also monitored for a fault at the same time. For example, is the flip-flop If K2 is disturbed in such a way that a reset is not possible, it has the same Effect as if according to section A2 of the diagram according to FIG processing clock is incorrectly replaced by a continuous signal.

If the flip-flop K2 is so disturbed that it is set to the active State is not possible, this intrinsic disturbance of the flip-flop has such an effect, as if the operating clock, according to section 3 of FIG. 2, had failed.

If there is a self-interference of the flip-flop K1 in the form that also If it is no longer possible to set it to the active state, this has a fault the same effect as the error case described in section 4.

In the same way, errors cannot be considered up to now Schaltzu. * Inden the flip-flops to the fault cases shown in FIG of the monitored units.

4 claims 2 figures

Claims (4)

Circuit arrangement for monitoring the proper processing sequence to be effected on the basis of a supplied input signal in at least one of two possible branches containing a processing unit, with the last processing step generating a corresponding end signal and the input signals simultaneously or at any time offset occur to each other and one input signal is the criterion for the processing order of the other input signal in the second processing branch and for the Monitoring one of the signals of both branches changeable in their switching state The flip-flop is used, so that both the signal-carrying (A2) and the non-signaling (Al) output in the idle state a clock-controlled bistable multivibrator (K1) each with an input of one Coincidence element (G1 or G2) is connected, of which the one with the former Output (A2) connected coincidence element (G2) via the other input to the end signal of the processing unit (ST) of the first branch (Z1) and that with the non-signal-carrying Output (A1) connected coincidence element (G1) directly to the second branch (Z2) applied input signal that the output signal (g, h) of each coincidence member a perceptible error registration (ski, S2) causing the error message signal that the set input of the multivibrator (K1) by an immediately upon termination of said input signal or upon termination of the respective end signal of a processing unit additionally present in this branch derived signal (d) is applied that the clock input (T2) of the flip-flop (K1) with the output (Ac), which does not carry a signal in the idle state, of another clocked steered bistable flip-flop (K2) is connected, whose set input with that of the first branch supplied input signal and its clock input (T1) with the end signal of the processing unit (ST) this branch (Z1) is applied. 2. Circuit arrangement according to claim 1, d a d u r c h g e k e n n notices that this is used to control the setting input of the bistable Flip-flop (K1) derived signal the output signal of a with the pulse end of the the second processing branch fed input signal triggered monostable Represents flip-flop (K3). 3. Circuit arrangement according to claim 1 and 2, d a -d u r c h g e k It is noted that the input signals represent the impulses of a time cycle, those for the first branch from an operating clock (TG) and for the second branch (Z2) can be supplied by a functionally independent replacement clock generator (ETG) and that at least the processing unit (ST) of the first branch (Z1) has one supplied pulse is in each case staggered in time, the unit with the last The pulse generated by a staggered step represents the end signal (f). 4. Circuit arrangement according to claim 3, d a d u r c h g e k e n n indicates that the output connected to the one coincidence element (G2) (A2) of the bistable multivibrator (K1) with one input of a further coincidence element (G3) is connected, the other input of which with a further graduation step, preferably lower ordinal number is connected to that by the output of this Eoincidence element a perceptible display and a switch to one to be output in the event of an error Output information is effected.