JPS6267984A - Video picture recording method - Google Patents

Abstract

PURPOSE:To eliminate an influence of random noise in a video signal and improve a picture quality by reading signals of respective picture elements of the video signal N times at different times to store in a memory device, reading the signal values and recording the picture correspondingly to the respective picture elements of the recording picture at 1:1. CONSTITUTION:In the case of a 4X4 picture element. non-interlace system, in the figure (a), a CRT 50 is scanned in the sequence from A, E, I, M, B, F...P. A memory 74 has line buffers 74A and 74B in which a writing and reading are changed over alternately. In the writing, to one negative pulse of a horizontal synchronous signal, four picture cell clocks PC are formed. The picture element data written in addresses 0-7 and 8-15 of the memory 74 respectively correspond to the first column and the second column of a recording picture shown in the figure (b). The reading from the memory 74 is carried out correspondingly to the respective picture elements of a video picture. In this case,an average value of random noise included in A1-A4 corresponding to, for instance, a picture element A is substantially the same as other one (for example the average value of the random noise included in K1-K4). This averaged operation is automatically performed by visually observing, so that the picture quality is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention records one pixel of a video image displayed on a display such as a CRT, and records N pixels of the image (N is an integer of 2 or more).
The present invention relates to a video image recording method for recording a video image on a recording material to obtain a hard copy.

[Conventional technology]

In this type of video image recording method, one pixel of the video image is read once and the video image is recorded on the recording material in correspondence with N pixels of the recorded image. As a result, it is possible to obtain a hard copy of a video image of the same size even if CRTs having different total video image pixel numbers are used.

However, the video signal contains random noise that changes over time, which limits the image quality.

[Problem that the invention seeks to solve]

An object of the present invention is to obtain a video image recording method that can reduce the influence of random noise contained in a video signal and improve the quality of recorded images.

[Means for solving problems]

In the video image recording method according to the present invention, one of the video images is
In a video image recording method in which a video image is recorded on a recording material by associating a pixel with N pixels (N is an integer of 2 or more - L) of a recorded image, the video signal of each pixel of the video image is read out at different times. a video image reading step in which the video signal values of each pixel are read out from the storage device at a certain timing, and each video signal value is corresponded one-to-one to each pixel of the recorded image. a video image recording step of recording an image on the material.

[Effect]

Random noise contained in a video signal changes over time. For this reason, note 1. N of each pixel stored in the a device
The amount of random noise included in each of the video signal values is different. If this stored video signal value is read out and an image is recorded on a recording material in one-to-one correspondence with each pixel of the recorded image, each pixel of the recorded image will be affected by random noise. However, the size of N pixels in the recorded image corresponds to 1 pixel in the video image and is relatively small, so N pixels can be seen as 1 pixel, and the random noise contained in each unit pixel is invisible to the human eye. The random noise contained in each unit pixel, with N pixels as one unit, becomes approximately equal.

Therefore, the quality of the image recorded on the recording material is improved.

〔Example〕

FIG. 1 shows a schematic block diagram of a device to which the present invention is applied, in which a video signal value from a CRT 50 is sampled and held at a predetermined timing by a sample and hold circuit 66, and an analog/digital converter 68 is used to After writing the D-converted video signal to the -H buffer memory 74, it is read out from the buffer memory 74 at a certain timing, and after being subjected to image processing by the image processing circuit 82, the drive circuit 8
The amount of light emitted from each of the light emitting diodes 14R, 114G, and 14B is controlled through the light emitting diode 4, and the image of the CRT 50 is exposed onto the photosensitive material 20. In this embodiment, regardless of whether the display of the CRT 50 is 512 x 512 pixels in a non-interlaced format or 1024 x 1024 pixels in a non-interlaced format, a video image of the same size is displayed on the photosensitive material 2.
The number of pixels of the image exposed on the photosensitive material 20 is 1024x1024. This is achieved by changing the method of capturing video signals into the buffer memory 74, as will be described in detail later, depending on the number of pixels and display method of the CRT 50.

FIG. 2 shows the mechanical configuration of an image recording section in an embodiment using the video image recording method according to the present invention, in which a rotating body 10 is supported by a shaft 12. As shown in FIG.

On the circumferential surface of the rotating body 10, light emitting diodes 14R are arranged 120 degrees apart and emit red light, green light, and blue light, respectively.
, 14G, and 14B are buried.

A photosensitive material mounting member 16 is disposed along the axial direction of the shaft 12 in correspondence with the rotating body 10 . A recess 18 is formed in the photosensitive material mounting member 16 in correspondence with the lower circumferential surface of the rotating body 10 . A photosensitive material 20 is attached to the surface of the four parts 18 using a clip (not shown) or the like. Rotating body 1
0 can move in its axial direction (arrow X direction or X" direction) while rotating. Main scanning is performed by rotating the rotating body 10, and by moving in the X direction or Sub-scanning is now performed. During these scans, video signals are supplied to the light emitting diodes 14R, 14G, and 14B, respectively, so that the photosensitive material 20 is exposed with a video image.

FIG. 3 shows another example of the mechanical configuration of the image recording section, in which a drum 22 is supported at its axial center and is rotatable. The photosensitive material 20 is wound around the circumferential surface of the drum 22 and attached thereto. A guide shaft 26A corresponding to the circumferential surface of the drum 22 and parallel to the axial direction of the shaft 24;
26B is arranged. The guide shafts 26A and 26B support the exposure head 28 so as to be movable in its axial direction.

Light emitting diodes 14R, 14G, and 14B are embedded in the exposure head 28 in correspondence with the circumferential surface of the drum 22. The light emitting diodes 14R, 14G, and 14B are arranged in close proximity to each other in the circumferential direction of the drum 22. Therefore, while rotating the drum 22, the exposure head 28
A video image is exposed onto the photosensitive material 20 by supplying a video signal to each of the light emitting diodes 14R, 14G, and 14[3] at appropriate timings while moving the photosensitive material 20 in the X direction or the X' force direction.

Below, the buffer memory 7 for the case where the display image of the CRT 50 is 512 x 512 pixels / non-interlace method, 1024 x 1024 pixels / non-interlace method
To simplify the explanation, the method of importing image signals into 4 is 4x4 pixel, non-interlaced method,
A detailed explanation will be given with reference to FIGS. 4 to 11 assuming that the 8×8 pixel non-interlace method is used and the recorded image is 8×8 pixels.

In the case of 4 x 4 pixel non-interlaced system, the fourth
In the figure, the CRT 50 is A, E, 1. ,M.

B, F...P are scanned in this order. The time it takes for the CRT to scan two frames corresponds to the time for one revolution of the rotating body 10 or the drum 20.

The buffer memory 74 is a line buffer memory 74 in which writing and reading are alternately switched, as shown in FIG.
A and 74B, and their addresses are 0 to 15. While the CRT 50 scans one screen, the CRT
50 vertical lines of pixel data are stored in the buffer memory 74.
The data is written alternately to either A or 74B.

The write address to the buffer memory 74 is alternately switched between even bits and odd bits of the buffer memory for each vertical synchronizing signal VsYNc included in the video signal VS, and the line buffer memories 74A and 74B are also written alternately. Specifically, the write address value to the buffer memory 74 is set to (0, 2) every vertical synchronization signal VSYNC.
, 4°6) → (1, 3, 5, 7) → (8, 10, 12° 14) → (9, 11, 13, 15).

Pixel data of the CRT 50 is written to the buffer memory 74 in the order of this address.

The pixel signal of which column (vertical line) of the image on the CRT 50 is to be written to the buffer memory 74 is determined as follows. As shown in FIG. 7, four pixel clockers PC are created for one negative pulse of the horizontal synchronizing signal H3YNC.

The pulse of each pixel clock PC corresponds to each pixel in the scanning order of the CRT 50. Therefore, in order to read the pixel signal of the Q-th column of the image of Cr1T50, the horizontal synchronization signal I
Qth pixel clock P from the negative pulse of JSYNC
It is sufficient to read the pixel signal corresponding to the C pulse.

This Q is a column setting counter to be described later, and this value is incremented every four pulses of the vertical synchronization bone vertical synchronization signal VSYNC are input.

In this way, as shown in FIG. 5, when the CRT 50 scans one frame J (one image), the addresses 0, 2
．． 4.6 Pixels A, B, and C in the first column of Fig. 4, respectively
, D corresponding to pixel data A, , B+ , C+ , DI
is written. When scanning the next frame, address 1
．． Similarly, pixel data A2, B2, C2, and B2 of the first column of the CRT 50 are written to 3.5.7. Similarly,
Next, pixel data A3 to address 8, 10.12.14
, B3, C3, B3 are written, then address 9.
Pixel data A4, B4, C4, to 11.13.15
Da is written.

The pixel data written to addresses 0 to 7 of the buffer memory 74 correspond to the first column of the recorded image shown in FIG. 6, and the pixel data written to addresses 8 to 15 correspond to the second column of the recorded image. corresponds to columns.

When writing to the line buffer memory 74A is completed and pixel data is written to the line buffer memory 74B, the pixel data from the line buffer memory 74A is read out. Furthermore, when writing to the line buffer memory 74B is completed and pixel data is written to the line buffer memory 74A, the pixel data from the line buffer memory 74B is read out. By repeating this alternately, it is possible to perform each read and write timing independently.

Next, the image quality of the image exposed onto the photosensitive material 20 in this manner will be explained with reference to FIG. Each pixel A3, 2,
Since BI is data read at different times, the values of random noise included in each are generally different. However, the average value of the random noise contained in A3, A2, A3, A4 corresponding to pixel A of the video image is different from other values, such as Kl, K2, K3,
It is almost the same as the average value of random noise included in K4. Since the pixels are relatively small, this averaging is done automatically by visual inspection. Therefore, compared to the conventional method of exposing the photosensitive material 20 by making the signal value of one pixel of the CRT 50 correspond to four pixels of the photosensitive material 20 at the same time, the image quality is improved. Additionally, video images can be recorded in the same amount of time as conventional methods. Furthermore, the processing is not complicated.

Note that even if the number of pixels of the CRT 50 is 8 x 8 and the interlace method is used, the case is almost the same as the above case, and FIG. 4 corresponds to FIG. 8, and FIG. 5 corresponds to FIG. 9. Correspondingly, FIG. 6 corresponds to FIG. 10, and FIG. 7 corresponds to FIG. 11. The CRT 50 scans odd fields and odd fields alternately. That is, in FIG. 8, a,
i..., c, , ・-1eXm, --1g, o,
-\b1 j.

..., dl 1..., fXn, ..., h, p, ...
Scan in order of... Correspondingly, the buffer memory 74 stores a+, C+%E3+, g+%t
)+, d, , fl, hI, . . . pixel signals are written in this order. The value of Q is incremented every time two pulses of the vertical synchronization signal VSYNC are input. For example, in FIG. 11, the discrimination between interlaced and non-interlaced
C negative pulse every other horizontal synchronizing signal HS YNC
This is done depending on whether the period H is between H/4 and 3H/4.

The other points are the same as in the case of 4×4 non-interlace described above.

Next, a more detailed control circuit diagram using the 112 method will be explained according to FIG. The video signal VS is separated into R (red), G (green), and B (blue) signals and taken out from the CRT 50. One of them, for example, the G signal, is supplied to the synchronization separation circuit 52, and the synchronization signal is separated. The separated vertical synchronization signal VSYNC is supplied to CP tJ 54. In the case of 1024XI024 interlace, horizontal synchronization signal 1 (S Y N C1 vertical synchronization signal V
1st from SYNC. Determines the second field and outputs a signal AS of 0 for the first field and 1 for the second field, and in the case of 512x512 non-interlace, the signal AS is inverted by 0° and 1 for each vertical synchronization signal VSYNC.
is output and input to the address control circuit 78.

On the other hand, the equalization pulse is removed from the horizontal synchronization signal H3YNC containing the equalization pulse through the equalization pulse removal circuit 56, and the equalization pulse is removed from the horizontal synchronization signal H3YNC containing the equalization pulse.
The signal is supplied to the L, L multiplier circuit 58. The pixel clock PC generated by the PLI and multiplier circuit 58 is supplied to a counter 60. counter 6
0 counts pulses from the PLL multiplier circuit 58 and supplies them to the coincidence circuit 62 as a column signal CVI. On the other hand, the minus number circuit 62 is supplied with the signal PS of the column setting counter Q from the CP TJ 54. The numerical circuit 62 compares the values of the column signal CVI and the column installation signal 1) S, and when they match, it supplies a coincidence signal SP in the form of a pulse to the timing circuit 64.

When the timing circuit 64 receives this coincidence signal SP,
Using PLI and the pixel clock PC from the multiplier circuit 58 as a synchronization signal, a sample and hold timing signal SC is supplied to the sample and hold circuit 66, and the A/D converter 68
The conversion timing signal AC is supplied to the The sample-and-hold circuit 66 samples and holds the video signal VS according to this sample-and-hold timing signal SC, and
/D converter 68. The A/D converter 68 receives the conversion timing signal AC, converts the analog signal from the sample hold circuit 66 into a digital signal, and sends the digital signal to the latch circuit 72.

A transfer start address, the number of transfer bytes, and a DMA enable signal are supplied from the CPU 54 to the DMA controller 76 . The timing circuit 64 supplies a write clock signal DR1 to the I) MA controller 76,
Based on this, the DMA controller 76 controls the latch circuit 7.
2, the latch circuit 72
The signal held in the buffer memory 74 is written to the buffer memory 74. This write address is the DMA controller 7
6 is supplied to the buffer memory 74 via an address control circuit 78. The address control circuit 78 shifts the write address from the DMA controller 76 to the upper bit by one bit when data is input, inputs the signal AS to the least significant bit, and alternately switches the value of the least significant bit to 01, thereby controlling the data. controls how data is written to the buffer memory. l) The MA controller 76 receives the successive timing signal D from the image processing circuit 82.
Data in the buffer memory 74 is not read out to the latch circuit 80 based on R2. This read data is held in the latch circuit 80 based on the launch timing signal LT2 from the DMA controller 76. The data held in the processing circuit 80 is supplied to the image processing circuit 82 based on the successive output timing SW2 from the image processing circuit 82. The image processing circuit 82 performs image processing such as color correction and gradation conversion on this, and passes it through the drive circuit 84 to the light emitting diode 14R114.
The exposure signal is supplied to G and 14B.

Note that a rotation synchronization signal that synchronizes the rotation of the rotating body 10 or the drum 22 is input as a clock signal to the image processing circuit 82, and the image processing circuit 82 processes this signal to create the successive timing signal DR2. It has become. This successive timing signal DR2 causes the DMA controller 76 to read the R, , B, and G data from the buffer memory 74 with a delay from each other by a time corresponding to 1×3 rotations of the rotating body 10.

Next, the operation of the control circuit configured as described above will be explained with reference to the control flowchart of the CPU 54 shown in FIGS. 13(A) and 13(B). First, Figure 13 (A)
The main routine shown in is explained below.

In step 100, an interwoven counter I, a column setting counter Q, and an interwoven status Is, which count the number of interruptions caused by a negative pulse of the vertical synchronization signal vSYNC, are cleared.

In addition, as mentioned above, every other negative pulse of the vertical synchronization signal VSYNC is H/4 of one period H of the horizontal synchronization signal H8YNC.
It is determined whether the interlace method or non-interlace method is used depending on whether the data is between .about.3H/4H. First, the case of 512×512 pixels and non-interlace method will be explained.

Next, in step 102, the CPU waits until the end flag F is set in an interrupt processing routine to be described later.

When an interrupt is generated in step 102 by the negative pulse of the vertical synchronizing signal VSYNC, the process shown in FIG. 13(B) is started. In step 200, the interwoven counter I is incremented, and in step 202, if the value of the interwoven counter I is 1 to 2048, the step 20 is incremented according to the value of the interwoven status TS in step 204.
6,210° 212 or 214 processing is performed. Initially, the interlaced status l5=O, step 20
In step 6, the input address by DMA is set as the starting address of the line buffer memory 74A. In the example shown in FIG. 5, it is 0. Also, assume that the number of input bytes by DMA is 512.

Furthermore, as described above, in the example shown in FIG. 5, data is input to addresses 0, 2° and 4.6. Next, DMA is started, the interlaced status Is is incremented in step 208, and the process returns to step 102 to wait for the next interrupt.

Next, when an interrupt occurs, step 200 is performed in the same manner as described above.
-204.210, and similarly to the above, the input address by DMA is set as the starting address of the line buffer memory 74A. Also, assume that the number of input bytes by DMA is 512.

Furthermore, assuming AS=1, in the example shown in FIG.
, 3, 5.7 to input data. Then, DMA is started. In step 208, the interlaced status Is is incremented and the process returns to step 202.

As a result, in the example shown in FIG. 5, one column of pixel data is input to addresses θ to 7.

Next, when an interrupt occurs, steps 200 to 204.21
2, the input address by DMA is set as the starting address of the line buffer memory 74B.

In the example shown in FIG. 5, it is 8. The number of input bytes by DMA is 512 as in the previous case. Also, AS-0,
In the example shown in FIG. 5, pixel data is input to addresses 8.10.12 and 1.4. Next, the output address by the DMA is set as the start address of the line buffer memory 74A. In the example shown in FIG. 5, it is 0. Also, DMA
Assume that the number of output bytes is 1024. Then, DMA is started.

As a result, in the example shown in FIG. 5, the data stored in addresses 0 to 7 is output to the image processing circuit 82 side, and becomes pixel data in the first column shown in FIG. At the same time, C
Pixel data from RT50 is input.

Then, in step 208, the interlaced status Is
is incremented and returns to step 102.

Next, when an interrupt occurs, steps 200 to 204.21
4, the input address by DMA is set as the starting address of the line buffer memory 74B.

In the example shown in FIG. 5, it is 8. Also, assume that the number of input bytes by DMA is 512. Furthermore, AS=1 and in the example shown in FIG. 5, pixel data is input to addresses 9, 11, 13°15. Next, DMA is started and column setting counter Q is incremented. Next, in step 216, the interlaced status IS is cleared and the process returns to step 102.

As a result, in the example shown in FIG. 5, pixel data is stored at addresses 8-15.

Next, when an interrupt occurs, steps 200 to 204.20
Proceeding to step 6, the DMA input address is set to the starting address of the line buffer memory 74A, the number of DMA input bytes is set to 512, and AS=0, as described above. Further, the output address by DMA is set as the start address of the in-buffer memory 74B.

In the example shown in FIG. 5, it is 8. Further, the number of output bytes is set to 1024 by DMA. Then, DMA is started.

As a result, in the example shown in FIG. 5, the pixel data at addresses 8 to 15 are output to the image processing circuit 82 side, and correspond to the pixel data in the second column shown in FIG. At the same time, pixel data is stored at addresses 0, 2, and 4.6.

When the above processing is repeated and the value of the interwoven counter I reaches 2049 in step 202, the process advances to step 218, sets the end flag F, and returns to step 102. This allows step 1 in the main routine.
The process proceeds from 02 to 104, where the end flag F is reset and the process ends.

In this way, one image on the CRT 50 is transferred to the photosensitive material 20.

Next, a case of 1024×1024 pixels/interlace method will be explained. In this case, the process is the same as in the case of the non-interlaced method except that the column setting counter Q is incremented in step 210. Taking FIG. 9 as an example, in step 206 the address O32,
Pixel data is input to addresses 4 and 6, and in step 210, pixel data is input to addresses 1.degree. 3.5.7, and a column setting counter Q is incremented. Further, pixel data is input to addresses 8, 10, 12, and 14 in step 212, and data at addresses O to 7 is output to the image processing circuit 82 to form the first column in FIG. Step 214
Then, pixel data is input to addresses 9, 11°, 13.15, and the column setting counter Q is incremented. Next, in step 206, the pixel data at addresses 8 to 15 are outputted to the image processing circuit 82 side to form the second column in FIG. 10, and the pixel data are inputted at addresses 0, 2, and 4.6.

In this way, the image on the CRT 50 can be transferred to the photosensitive material 20 in the interlaced method as well as in the non-interlaced method.

The only difference in processing due to the difference in mode is whether or not the column setting counter Q is incremented in step 210, which simplifies the processing.

〔Effect of the invention〕

In the video image recording method according to the present invention, the video signal of each pixel of the video image is read N times at different times and recorded in the storage device, and the video signal value of each pixel is read out from the storage device at a certain timing. Since each signal value corresponds one-to-one to each pixel of the recorded image and the image is recorded on the recording + 4 image, the influence of random noise can be averaged out and recorded on the recording material using a simple method. This has an excellent effect of improving the quality of recorded images.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a control circuit to which an embodiment of the video image recording method according to the present invention is applied, FIG. 1
3) is a plan view of FIG. 2(A), FIG. 3(A> is a front view showing another example of the mechanical tank configuration of the video image recording section, and FIG.
B) is a side view of FIG. 3(A), FIG. 4 is a pixel arrangement diagram of a simplified video image (4 x 4 pixels, non-interlace method), and FIG. 5 is a buffer memory 74 corresponding to FIG. 4.
6 is a pixel arrangement diagram of the recorded image corresponding to FIGS. 4 and 5, and FIG. 7 is the main (t-M waveform diagram) of FIG. 1 in the simplified case, and FIGS. Figure 11 is 8
Figures 4 to 7 in the case of ×8 pixels/interlaced method
12 is a detailed control block diagram of FIG. 1, and FIGS. 13(A) and 13(B) are control flowcharts of the CPU 54. 14R114G, 14B... Light emitting diode, 20.
...Photosensitive material, 28...Exposure head, 50...CRT. 54...CPU. 74... Buffer memory, VS... Video signal, VSYNC... Vertical synchronization signal, ('J Figure 2, Figure 5, Figure 6, Figure 8, Figure 9 = 74A 748 Figure 10

Claims (2)

[Claims] (1) One pixel of the video image is recorded as N pixels of the image (N is 2
In the video image recording method of recording a video image on a recording material in correspondence with the above integer), the video image reading step of reading the video signal of each pixel of the video image N times at different times and storing each in a storage device; and a video image recording step of reading out the video signal value of each pixel from the storage device at a certain timing and recording the image on the recording material by making each video signal value correspond one-to-one to each pixel of the recording image. A video image recording method characterized by: (2) The video image recording method according to claim 1, wherein in the video image reading step, the data of each pixel of the video image is read N times by repeatedly reading each line N times.