JPS6267918A - Afc circuit - Google Patents
Afc circuitInfo
- Publication number
- JPS6267918A JPS6267918A JP20682585A JP20682585A JPS6267918A JP S6267918 A JPS6267918 A JP S6267918A JP 20682585 A JP20682585 A JP 20682585A JP 20682585 A JP20682585 A JP 20682585A JP S6267918 A JPS6267918 A JP S6267918A
- Authority
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- Japan
- Prior art keywords
- signal
- frequency
- correction
- delay time
- control voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は衛星放送用受信機等に使用できるAFC(自動
周波数制御)回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an AFC (automatic frequency control) circuit that can be used in satellite broadcasting receivers and the like.
従来の技術
周波数シンセサイザ方式選局回路を有する受信機におい
ては、局部発振器の周波数精度は周波数シンセサイザ回
路の基準発振器の精度と同等であり、基準発振器には通
常水晶発振器が使用されるので、受信信号の周波数精度
が良い場合には中間周波信号の周波数精度は充分高くな
りAFC回路は不要である。(〜かし衛星放送受信シス
テムにおいては、マイクロ波帯の受信信号を屋外のダウ
ンコンバータにおいて第1中間周波信号に周波数変換し
た後、ケーブルにて屋内に導びき、その第1中間周波信
号を屋内の受信機(でおいて2回目の周波数変換をし第
2中間周波信号を得るのが一般的である。第2中間周波
への周波数変換は通常選局のために行なわれ、希望チャ
ンネルの信号のみが選択される。こうした選局システム
構成では屋内の受信機の選局用局部発振器の周波数精度
が周波数シンセサイザ方式等によりいかに高くできても
、屋外のダウンコンバータの局部発振器の周波数精度が
あ丑り良くなければ第2中間周波の周波数精度は良くな
らない。実際に、屋外のダウンコンバータの局部発振器
の発振周波数は数MHzの温度ドリフトを持つのが一般
的である。Conventional technology In a receiver having a frequency synthesizer type tuning circuit, the frequency accuracy of the local oscillator is equivalent to the accuracy of the reference oscillator of the frequency synthesizer circuit, and since a crystal oscillator is usually used as the reference oscillator, the received signal When the frequency accuracy of the intermediate frequency signal is good, the frequency accuracy of the intermediate frequency signal is sufficiently high and an AFC circuit is not necessary. (In the satellite broadcasting receiving system, the microwave band reception signal is frequency-converted into a first intermediate frequency signal in an outdoor down converter, then guided indoors by a cable, and the first intermediate frequency signal is transmitted indoors.) Generally, a second frequency conversion is performed at the receiver (to obtain a second intermediate frequency signal). Frequency conversion to the second intermediate frequency is usually performed for channel selection, and the signal of the desired channel is In such a tuning system configuration, no matter how high the frequency accuracy of the local oscillator for tuning in the indoor receiver can be made using a frequency synthesizer method, the frequency accuracy of the local oscillator in the outdoor down converter is poor. The frequency accuracy of the second intermediate frequency cannot be improved unless the frequency is good.Actually, the oscillation frequency of the local oscillator of an outdoor down converter generally has a temperature drift of several MHz.
一方、第2中間周波の周波数精度に悪くとも数百KHz
以内であるべきであり、受信機の選局回路が周波数シン
セサイリ′方式を有する場合でも第2中間周波の周波数
精度を高く保つためにAFC回路が不可欠である。On the other hand, the frequency accuracy of the second intermediate frequency is at worst several hundred KHz.
Even if the receiver's tuning circuit has a frequency synthesis method, an AFC circuit is essential to keep the frequency accuracy of the second intermediate frequency high.
上記17た様な周波数シンセサイザ方式選局回路にAF
C回路を備えだ従来例としては特開昭56−23674
号公報に示されているものがある。AF to frequency synthesizer type tuning circuit like above 17
A conventional example of a C circuit is disclosed in Japanese Patent Application Laid-Open No. 56-23674.
There are some that are shown in the publication.
第5図は本従来例の構成を示すブロック図である。FIG. 5 is a block diagram showing the configuration of this conventional example.
以下図面を参照しながら従来例に関して説明する。A conventional example will be described below with reference to the drawings.
第6図の1は受信信号入力端子、2は高周波増幅器、3
は周波数混合器、4は電圧制御型の局部発’&?5.6
はPLLシン七ザイザ部、6は中間周波A−7
増幅器、7はFM復調器、8ばFM復調器7の復調信号
出力端子、9は低域通過フィルタ、10は中間周波数ず
れ検出器である。In Fig. 6, 1 is a received signal input terminal, 2 is a high frequency amplifier, and 3 is a high frequency amplifier.
is a frequency mixer, and 4 is a voltage-controlled local oscillator'&? 5.6
is a PLL synthesizer section, 6 is an intermediate frequency A-7 amplifier, 7 is an FM demodulator, 8 is a demodulated signal output terminal of the FM demodulator 7, 9 is a low-pass filter, and 10 is an intermediate frequency shift detector. .
第6図は周波数ずれ検出器10の構成図であり、FM復
調器7の復調出力を低域通過フィルタ(以下LPFとい
う)9で平滑して、復調信号から直流電圧成分を取出し
た後、電圧比較器10a、10bによって一定のしきい
値電圧vr1.vr2と比較している。FM信号の復調
出力をLPF9を介して直流電圧成分を取出すと復調信
号の平均電圧値が得られ、これはFM信号の平均周波数
に対応する。FIG. 6 is a block diagram of the frequency shift detector 10. After smoothing the demodulated output of the FM demodulator 7 with a low-pass filter (hereinafter referred to as LPF) 9 and extracting the DC voltage component from the demodulated signal, the A constant threshold voltage vr1. Comparing with vr2. When a DC voltage component is extracted from the demodulated output of the FM signal through the LPF 9, an average voltage value of the demodulated signal is obtained, which corresponds to the average frequency of the FM signal.
そこで第6図に示すごとく構成し、あらかじめ設定され
たしきい値電圧vrj + vr2 と復調出力の平
均電圧値とを比較することにより、中間周波信号の中心
周波数よりのずれが所定の範囲内であるか、またずれが
所定の範囲外であれば中心周波数と比べて高いか低いか
のいずれであるかを検出できる。Therefore, by configuring the system as shown in Fig. 6 and comparing the preset threshold voltage vrj + vr2 with the average voltage value of the demodulated output, it is possible to determine if the deviation from the center frequency of the intermediate frequency signal is within a predetermined range. If the deviation is outside a predetermined range, it can be detected whether the deviation is higher or lower than the center frequency.
これらは第6図の出力端子1oθ、10fからの出力を
調べることにより判る。それらの出力をPLLシンセザ
イザ部5に入力し、局部発振器46、−7
の発振周波数を微調することにより中間周波数がその中
心周波数よりずれていればこれを小さくするように制御
すればAFC回路が構成できる。These can be found by examining the outputs from the output terminals 1oθ and 10f in FIG. The AFC circuit can be configured by inputting these outputs to the PLL synthesizer section 5 and finely adjusting the oscillation frequency of the local oscillators 46 and -7 to reduce the deviation of the intermediate frequency from the center frequency. can.
しかしながら、上記のような構成では、AFC回路の周
波数基準はFM復調器7そのものであり、衛星放送用受
信機等に使用されるFM復調器は通常高周波、広帯域な
信号を取扱うだめその入力周波数対出力電圧の温度安定
度はあまり良好ではない。このため高い周波数精度を有
するAFC回路を実現することは困難である。特に復調
すべき信号が高い直線性を要求される映像信号等の場合
では中間周波数のずれに伴なって中間周波バンドパスフ
ィルタを通過する時に振幅及び位相歪が生じないように
することが重要である。However, in the above configuration, the frequency reference of the AFC circuit is the FM demodulator 7 itself, and the FM demodulators used in satellite broadcasting receivers usually handle high frequency and wideband signals, so their input frequency The temperature stability of the output voltage is not very good. Therefore, it is difficult to realize an AFC circuit with high frequency accuracy. Especially when the signal to be demodulated is a video signal that requires high linearity, it is important to prevent amplitude and phase distortion from occurring when passing through an intermediate frequency bandpass filter due to a shift in the intermediate frequency. be.
上記したような問題点を解決するために、第7図に示す
よう々構成のAFC回路が提案されている。以下図面を
参照しながら、本提案における人FC回路について説明
する。第7図において、入力端子1に受信信号が入力さ
れ、高周波増幅器2、周波数混合器3.中間周波増幅器
6を経て、FM復調器7に入力され、出力端子8に復調
出力が得られる。電圧制御型の局部発振器4ばその制御
電圧のシンセザイザ回路5により制御される。In order to solve the above problems, an AFC circuit having a configuration as shown in FIG. 7 has been proposed. The human FC circuit according to the present proposal will be described below with reference to the drawings. In FIG. 7, a received signal is input to an input terminal 1, a high frequency amplifier 2, a frequency mixer 3. The signal is inputted to an FM demodulator 7 through an intermediate frequency amplifier 6, and a demodulated output is obtained at an output terminal 8. A voltage controlled local oscillator 4 is controlled by a synthesizer circuit 5 whose control voltage is controlled.
制御型FEのシンセザイザ回路5はPLL周波周波数シ
ンセサイザ方式ることも可能であるし、D/Aコンバー
タ等を用いる電圧シンセサイザ方式も可能である。The control type FE synthesizer circuit 5 can be of a PLL frequency synthesizer type or a voltage synthesizer type using a D/A converter or the like.
さて、中間周波信号は分周比がそJlぞれNH9NLで
ある分周器11.12を介してそれぞれ周波数比較器1
4.15に入力さJする。周波数比較器14.15の他
方の入力端子には周波数がf8 である基準信号発振器
13の出力信号が入力されている。基準信号としては周
波数精度の高い水晶発振器出力を分周して用いれば良い
。周波数比較器14.16とi〜では、第8図に示すよ
うな入出力特性を有し、第9図の回路ブロック図のよう
な構成のテアタル型式の位相・周波数検波器を用いてい
る。第9図から判るように紙票周波数よりも分周された
中間周波信号の中心周波数が高ければ位相・周波数検波
器の出力はハイレベル(以下t+ HIIと記す)とな
り、逆に低けねばその出力はローレベル(以下゛L°“
と記す)となる。1〜かし、その出力は基質周波数成分
をも含んでいるので、これを取除くためにLPFl 6
.1了を介してそれぞれの周波数比較信号を取出してい
る。ここで正規の中間周波数をfo とすれば、次式が
成立する様にfs+NHrNLを定める。Now, the intermediate frequency signals are passed through frequency dividers 11 and 12, each having a frequency division ratio of NH9NL, to a frequency comparator 1.
4.15 is entered. The output signal of the reference signal oscillator 13 having a frequency of f8 is input to the other input terminal of the frequency comparator 14,15. As the reference signal, a frequency-divided crystal oscillator output with high frequency accuracy may be used. The frequency comparators 14, 16 and i~ use theatal type phase/frequency detectors having input/output characteristics as shown in FIG. 8 and configured as shown in the circuit block diagram of FIG. 9. As can be seen from Figure 9, if the center frequency of the divided intermediate frequency signal is higher than the paper slip frequency, the output of the phase/frequency detector will be at a high level (hereinafter referred to as t+HII); The output is low level (hereinafter "L°")
). 1 to 1, the output also includes the substrate frequency component, so in order to remove this, LPFl 6
.. Each frequency comparison signal is taken out via the 1st line. Here, if the normal intermediate frequency is fo, then fs+NHrNL is determined so that the following equation holds.
fs X NL < fo < fs X NH即ち、
中間周波数がfsXNHの時分周器11に出力される信
号の周波数ばfs と等1〜くなり、この周波数におい
て周波数比較器14が周波数弁別できるので周波数比較
出力は論理値が変化する。同様なことは中間周波数がf
sXNt、でも生ずる。故に中間周波数とそれぞれの周
波数比較信号との関係は第10図(a) 、 (b’l
に示すようになる。第1o図から判るようにそれぞれの
周波数比較器月は正規の中間周波数foからのずれの検
知限fsXNu及びfsXNbで出力論理値を変えるの
で、こねらの検知限をfo±300KHz @度に設定
l〜、周波数比較信号を用いて選局電圧のシンセザイザ
回路592、−7゜
において局部発振器4の制御電圧を微調する必要がある
かどうか、あるいは微調するどすればその方向を判別で
きるので周波数精度の高いAFCN路が実現できる。fs X NL < fo < fs X NH, that is,
The frequency fs of the signal output to the time frequency divider 11 with an intermediate frequency of fsXNH is equal to 1, and since the frequency comparator 14 can discriminate the frequency at this frequency, the logical value of the frequency comparison output changes. Similarly, the intermediate frequency is f
It also occurs in sXNt. Therefore, the relationship between the intermediate frequency and each frequency comparison signal is shown in Fig. 10 (a) and (b'l
It becomes as shown in . As can be seen from Figure 1o, each frequency comparator changes its output logic value at the detection limits fsXNu and fsXNb for deviations from the normal intermediate frequency fo, so the detection limits of the comparators are set to fo±300KHz @ degrees. ~, the frequency comparison signal can be used to determine whether or not the control voltage of the local oscillator 4 needs to be finely adjusted at −7°, or the direction in which it should be finely adjusted, which improves frequency accuracy. A high AFCN road can be achieved.
発明が解決しようとする問題点
しか17ながら、上記のような構成では第8図に示すよ
うな位相・周波数比較特性を有する位相・周波数検波器
を用いているので、衛星放送信号等のように取扱う中間
周波信号が広帯域FM信号である場合には、そのFM変
調指数がかなり大きいので分周比NH+ NL を充分
大きくすることによりFM変調指数を下げて、周波数比
較器が誤動作しないようにする必要がある。特に衛星放
送では一般に地上マイクロ波通信への妨害が生じないた
めに映像信号に加えてエネルギー拡散信号を重畳して伝
送することが行なわれており、その周波数は30 Hz
で周波数変位は2MH2p−p程度である。Although there are only 17 problems that the invention attempts to solve, the above configuration uses a phase/frequency detector having phase/frequency comparison characteristics as shown in FIG. If the intermediate frequency signal to be handled is a wideband FM signal, its FM modulation index is quite large, so it is necessary to lower the FM modulation index by making the frequency division ratio NH + NL sufficiently large to prevent the frequency comparator from malfunctioning. There is. In particular, in satellite broadcasting, in order to avoid interference with terrestrial microwave communication, an energy diffusion signal is superimposed on top of the video signal and transmitted, and the frequency is 30 Hz.
The frequency displacement is about 2MH2p-p.
故にその変調指数は約67000であるから、分周比と
しては50000程度以上必要である。Therefore, since the modulation index is approximately 67,000, the frequency division ratio must be approximately 50,000 or more.
このように分周比として相当大きな値が必要で10、。In this way, a fairly large value is required as the frequency division ratio, 10.
あるから、中間周波信号の周波数弁別の行なわれる周波
数比較器入力での中間周波信号と基準信号との周波数差
は、実際の中間周波帯での中間周波信号の中心周波数と
中間周波の周波数弁別の検知限f S X NH+ f
8 X NLとの差に比べて50000分の1程度小さ
いことになる。例えば、中間周波帯での300 KHz
の周波数差は周波数比較器入力では6Hzに変化する。Therefore, the frequency difference between the intermediate frequency signal and the reference signal at the frequency comparator input, where frequency discrimination of the intermediate frequency signal is performed, is the difference between the center frequency of the intermediate frequency signal in the actual intermediate frequency band and the frequency discrimination of the intermediate frequency. Detection limit f S X NH+ f
This is about 1/50000 smaller than the difference with 8.times.NL. For example, 300 KHz in the intermediate frequency band
The frequency difference changes to 6Hz at the frequency comparator input.
周波比較信号は6Hzの信号を積分して直流成分を取り
出すのに少なくともその周期と同程度の遅れ時間を必要
とするので正規の論理値が出力されるのには約0.17
秒の待ち時間が必要である。つまり中間周波の周波数弁
別の検知限に中間周波が近づけば近づく程、周波数比較
信号が正規の論理値になるのに要する時間が長くなり、
この様−子を第11図に示す。この図から判るようにe
i OKHzの精度で周波数比較するには1秒間の検出
待ち時間が必要であるから、例えばAFC回路の引込み
範囲を±3 MHzとし、周波数ずれの検知限をそれぞ
れ±300 KHzとi〜、局部発振器の発振周波数の
微調時制御量を200KHzとして、選局機能により任
意の信号を選択L〜終えた時に中間周波数が引込み範囲
の最大値である+3 MHzだけ正規の中間周波数より
ずれていた場合に、200 KHzづつ局部発振器の発
振周波数を1秒の間隔を取りんがらAFC回路動作によ
り中間周波信号を正規の中間周波数に引込捷せてゆくと
すれば第12図(a)、 (+))に示すような状況に
なる。The frequency comparison signal requires a delay time at least as long as the period of the 6Hz signal to extract the DC component, so it takes about 0.17 seconds for a normal logic value to be output.
A waiting time of seconds is required. In other words, the closer the intermediate frequency is to the detection limit for frequency discrimination of the intermediate frequency, the longer the time required for the frequency comparison signal to reach the normal logical value.
This situation is shown in FIG. As you can see from this figure, e
Since a detection waiting time of 1 second is required to compare frequencies with an accuracy of i OKHz, for example, the pull-in range of the AFC circuit is set to ±3 MHz, and the frequency deviation detection limit is set to ±300 KHz, i~, local oscillator. When the control amount during fine adjustment of the oscillation frequency is set to 200 KHz, and the intermediate frequency deviates from the regular intermediate frequency by +3 MHz, which is the maximum value of the pull-in range, when an arbitrary signal is selected by the channel selection function. If the oscillation frequency of the local oscillator is changed to 200 KHz at intervals of 1 second, and the intermediate frequency signal is pulled in to the regular intermediate frequency by AFC circuit operation, the result will be as shown in Fig. 12 (a), (+)). The situation will be as shown.
即ち、中間周波数の周波数すれか+3 MHzのところ
からAFC回路の機能により周波数すれが小さくなるよ
うに局部発振周波数が微調されるが、1回の周波数微調
では200 KHzの周波数シフトであるので14回の
周波数シフトを繰返して初めてAFC引込み動作が完了
となる。故にこの動作の所要時間は、
1秒×14回=14秒
となり、相当長いAFC引込み時間が必要に々るという
問題があった。In other words, the local oscillation frequency is finely adjusted by the function of the AFC circuit from the intermediate frequency frequency +3 MHz to reduce the frequency deviation, but since one frequency fine adjustment is a frequency shift of 200 KHz, it is necessary to adjust the local oscillation frequency 14 times. The AFC pull-in operation is completed only after repeating the frequency shift. Therefore, the time required for this operation is 1 second x 14 times = 14 seconds, resulting in a problem that a considerably long AFC pull-in time is required.
なお、第5図に示しだ従来例においても復調信号を基準
信号と比較して周波数ずれの検出を行なうために復調信
号をLPFで平滑し平均直流電圧を得る必要があり、衛
星放送信号等のように低周波のエネルギー拡散信号が重
畳された映像信号を1?滑化するためにはLPFの時定
数に1−相当太きくしなければ周波数すれの検出に誤り
が生ずるのである。このだめ周波教程イ度をあげ。Lう
とすJlば、周波数ずねの検出のため待ち時間を長くす
る必要があり、これに5LすAFC引込み時間が長くな
るという問題かぁ−)だ。In addition, even in the conventional example shown in Fig. 5, it is necessary to smooth the demodulated signal with an LPF to obtain an average DC voltage in order to compare the demodulated signal with a reference signal and detect a frequency deviation. A video signal on which a low-frequency energy diffusion signal is superimposed is 1? In order to achieve smoothness, the time constant of the LPF must be made thicker by 1, otherwise an error will occur in the detection of frequency deviation. Raise the level of this useless frequency teaching. If you choose L, it is necessary to increase the waiting time to detect the frequency deviation, which also increases the AFC pull-in time.
本発明は上記問題点に鑑み、選局終了時からAFC引込
み丑でに必要な時間を大幅に短縮することのできるAF
C回路を提供するととを目的、!−ニしている。。In view of the above-mentioned problems, the present invention is an AF system that can significantly shorten the time required for AFC pull-in from the end of channel selection.
The purpose is to provide C circuits! -I'm doing it. .
問題点を解決するだめの手段
この目的を達成するために本発明のAFCl路は、中間
周波信号の中心周波数が正規の中間周波数と比べて所定
値以上に周波数がず才1ているかどうかを判定してそJ
lを補正判定信号として得るとともにその周波数ず才]
が正規の中間周波数と比べて高いか低いかの方向を判定
してそれを補正方向信号と1〜て得る周波数ずJ1検出
器と、電圧側御型局部発振器の周波数制御を行なう選局
電圧のシンセサイザ回路を補正判定信号と補正方向信号
とを遅延時間設定手段の制御により入力する信号入力手
段と、この信号入力手段の出力を入力して周波数制御電
圧の微調を行なう制御電圧微調手段と、前記信号入力手
段の出力を入力して前回の記憶手続きにより記憶されて
いるそれらの論理値と入力値との差異の有無を判定する
とともにそれらの論理値を各々更新記憶する前値比較手
段と、制御電圧微調手段の出力と選局指令信号と前値比
較手段の出力とを入力して局部発振周波数の変更が完了
してから信号入力手段が入力信号のテークを読み込むま
での遅延時間の設定を行なう遅延時間設定手段と、選局
指令信号と制御電圧微調手段の出力とを入力して局部発
振器の制御電圧を発生する制御電圧発生回路とを備え、
選局指令信号による選局動作毎に補正方向信号及び補正
判定信号がそれらの正規の値に収束するのに必要な時間
の約0.1倍から0.3倍程度の遅延時間を遅延時間設
定手段に与え、前値比較手段により補正判定信号もしく
は補正判定信号の論理値が記憶しである論理値から初め
て変化した時点以降は補正判定信号及び補正方向信号が
そJlらの正規の値に収束するのに必要な時間と同等以
上の遅延時間をりオーて局部発振[+−]′1路の制御
電圧を微調する構成を備えている。Means for Solving the Problem In order to achieve this object, the AFCl circuit of the present invention determines whether the center frequency of the intermediate frequency signal differs in frequency by more than a predetermined value compared to the normal intermediate frequency. Shiso J
Obtain l as a correction judgment signal and calculate its frequency]
A frequency detector J1 determines whether the frequency is higher or lower than the regular intermediate frequency and uses it as a correction direction signal. a signal input means for inputting a correction determination signal and a correction direction signal to the synthesizer circuit under the control of a delay time setting means; a control voltage fine adjustment means for finely adjusting a frequency control voltage by inputting the output of the signal input means; Previous value comparison means inputs the output of the signal input means and determines whether there is a difference between the logical values stored by the previous storage procedure and the input value, and updates and stores each of the logical values; The output of the voltage fine adjustment means, the channel selection command signal, and the output of the previous value comparison means are inputted to set the delay time from when the change of the local oscillation frequency is completed until the signal input means reads the take of the input signal. comprising a delay time setting means, and a control voltage generation circuit that inputs a channel selection command signal and an output of the control voltage fine adjustment means to generate a control voltage for a local oscillator,
Set a delay time of about 0.1 to 0.3 times the time required for the correction direction signal and correction judgment signal to converge to their normal values for each channel selection operation by the channel selection command signal. After the correction judgment signal or the logical value of the correction judgment signal first changes from the stored logical value by the previous value comparison means, the correction judgment signal and the correction direction signal converge to their normal values. The control voltage of the local oscillation [+-]'1 path is finely adjusted by a delay time equal to or longer than the time required for the local oscillation.
作用
本発明は上記した構成により、周波数ずれ検出器により
局部発振器の発掘周波数を微調するため必要な補正判定
信号及び補正方向信号を得る。これらの信けけ遅延時間
設定手段により適当なタイiングを与えられて信号入力
手段により各々の論理値が読み込捷れる。それらの論理
値は制御電圧微調手段により制御電圧発生回路を制御し
て局部発振器制御電圧を微調するのに用いらI7る。前
値比較手段は信号入力手段により入力された補正判定信
号もしくは補正方向信号が既に記憶しであるそれらの値
と差異があるかどうかを判定し、差異が生ずれは遅延時
間設定手段の遅延時間を変更する制御を行なう。1だ入
力されだ信号を更新記憶し、次回の差異判定に供する。Operation The present invention uses the above-described configuration to obtain a correction determination signal and a correction direction signal necessary for finely adjusting the detected frequency of the local oscillator using the frequency deviation detector. Appropriate timing is given by these reliable delay time setting means, and each logic value is read and switched by the signal input means. These logical values are used by the control voltage fine adjustment means to control the control voltage generation circuit to finely adjust the local oscillator control voltage. The previous value comparison means determines whether the correction judgment signal or the correction direction signal input by the signal input means is different from those values already stored, and if a difference occurs, the delay time of the delay time setting means is determined. control to change. The signal that is input once is updated and stored, and is used for the next difference determination.
選局指令信号により選局するチャンネルを切替える度に
補正判定信号及び補正方向信けがそれらの正規の値に1
17重するのに必要な時間の約0.1倍から0.3倍程
度の遅延時間を−りえているので、AFC引込み動作に
おける周波数微調の時間間隔は本来必要な時間と比べて
短かいのでAFC引込み時間に1短縮される。周波数微
調の時間間隔を短縮i〜でいるので補IF判定信号もし
くは補市方向信りが正規の論理値にならず、周波数微調
の動作が行きすぎてし捷うが、との行きすぎ−M゛はそ
の時間短縮の度合いに比例して大きくなる。このだめ時
間短縮率0寸行きすき量を勘案し7て決める必要があり
、約0.1倍から0.3倍程度の時間短縮率であればそ
れほど大きな行きすぎ惜は生じない。Every time the channel to be selected is switched by the channel selection command signal, the correction judgment signal and correction direction signal change to their normal values by 1.
17 Since the delay time is approximately 0.1 to 0.3 times the time required for overlapping, the time interval for fine frequency adjustment in AFC pull-in operation is short compared to the originally required time. The AFC pull-in time is reduced by 1. Since the time interval of frequency fine adjustment is shortened by i~, the supplementary IF judgment signal or supplementary direction signal does not become a normal logical value, and the frequency fine adjustment operation goes too far and is interrupted.゛ increases in proportion to the degree of time reduction. It is necessary to determine this time reduction rate by taking into consideration the 0-inch clearance amount, and if the time reduction rate is about 0.1 to 0.3 times, there will not be a large margin of overshoot.
さて、遅延時間を短縮して周波数微調を高速に行なって
いるので若干の行きすき量が生じて補正判定信号もしく
は補正方向信号の論理値に変化が生ずるので、これを前
値比較手段により検出し、遅延時間設定手段における遅
延時間を補正判定信号及び補正方向信号がそれらの正規
の値に収束するのに必要な時間ど同等以l−に設定変更
するので今度は行きすぎ扇−が牛じないので中間周波数
シー4正規の中間周波数に引込寸れてゆく。Now, since the delay time is shortened and the frequency fine adjustment is performed at high speed, a slight amount of clearance occurs, causing a change in the logical value of the correction judgment signal or correction direction signal. This is detected by the previous value comparison means. Since the delay time in the delay time setting means is changed to be equal to or longer than the time required for the correction judgment signal and the correction direction signal to converge to their normal values, the overshooting will not occur this time. Therefore, the intermediate frequency C4 is gradually being pulled down to the regular intermediate frequency.
実施例
以下本発明の実施例について、図面を参照しながら説明
する。第1図は本発明の一実施例に赴けるAFCl路の
ブロック図である。第1図において、入力端子1に受信
信号が入力され、高周波増幅器2、周波数混合器3、周
波変換のだめの局部発掘器4、中間周波増幅2(6を経
て中間周波信号が出力端子22に得らJすることしt従
来例の第5図と同様である。周波数すね検出器18は従
来例の第6図の構成でも良いし、第7図のように分周器
11.12、基準信号発振器13、周波数比較器14.
16、LPF16.17の構成でも可能であるが、第7
図の揚台について説明すると、LPF16の出力とLP
Fl 7の出力との排他的論理和をとれば補正判定信号
として用いることができる。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an AFCl path in accordance with one embodiment of the present invention. In FIG. 1, a received signal is input to an input terminal 1, and an intermediate frequency signal is obtained at an output terminal 22 after passing through a high frequency amplifier 2, a frequency mixer 3, a local excavator 4 for frequency conversion, and an intermediate frequency amplifier 2 (6). The configuration is the same as that shown in FIG. 5 of the conventional example.The frequency detector 18 may have the configuration shown in FIG. 6 of the conventional example, or as shown in FIG. Oscillator 13, frequency comparator 14.
16, LPF16.17 configuration is also possible, but the 7th
To explain the platform in the figure, the output of LPF16 and the LP
If it is exclusive ORed with the output of Fl 7, it can be used as a correction determination signal.
またLPFl 6の出力がH″であれば周波数が高い方
にすねていることが判り、LPFl了の出1j、−−
力がL゛であれば周波数が低い方にずれていることが判
るので補正方向信号とすることができる。Also, if the output of LPF16 is H'', it means that the frequency is shifting toward the higher side, and if the output of LPF1 is L'', it is known that the frequency is shifting toward the lower side. It can be a correction direction signal.
シンセサイザ回路6は補正判定信号と補正方向信号及び
端子21から入る選局指令信号を入力1〜で局部発振器
4の発振周波数を制御する制御電圧を発生ずるものであ
り、その詳細は第2図のブロック図で表せる。信号入力
手段5C1制御電圧微調手段5b、前値比較手段6e、
遅延時間設定手段5dはマイクロコンピュータ回路5a
において実現される機能である。信号入力手段6Cは補
正判定信号及び補正方向信号を遅延時間設定手段5dに
より設定される適当なタイミングにおいて入力する。入
力されたそれらの信号は制御電圧微調手段6bと前値比
較手段5eに送られる。制御電圧微調手段6bはこれら
の信号をもとにして中間周波信号の中心周波数が正規の
中間周波数に収れんするように局部発掘器40制御電圧
を作る制御電圧発生回路6fに信号を与える。制御電圧
発生回路5fけPLL−4Gによる周波数シンセサイザ
回路もしくはD/Aコンバータ等による電圧シンセサイ
ザ回路にて実現できるが、選局指令信号により選局チャ
ンネルの周波数に対応するJM3部発振周波数で局部発
振器4が発振するようにiIrIr型圧を作りだし、周
波数の微調は制御電圧微調手段5bの信号による。寸だ
必要であ才1は局部発振器4の出力を入力する。遅延時
間設定手段5dけ制御電圧微調手段5bあるいは選局指
令信けにより局部発振間波数を変更してから信号入力手
段6Cにより補IF判定信号および補正方向信号を入力
するまでの遅延時間を設定する役割を果す。前値比較手
段5eは入力された補正判定信号および補正方向信号の
論理値が変化する時を検出する役割を果すためそれらの
論理値を配憶1〜ておき新[〜く入力された値と比較し
、異々っていJlげその検出出力により遅延時間設定手
段6dにおける遅延時間を変更する。The synthesizer circuit 6 generates a control voltage for controlling the oscillation frequency of the local oscillator 4 by inputting the correction judgment signal, the correction direction signal, and the tuning command signal input from the terminal 21, and its details are shown in FIG. It can be expressed as a block diagram. Signal input means 5C1 control voltage fine adjustment means 5b, previous value comparison means 6e,
The delay time setting means 5d is a microcomputer circuit 5a.
This is a function realized in . The signal input means 6C inputs the correction determination signal and the correction direction signal at an appropriate timing set by the delay time setting means 5d. These input signals are sent to the control voltage fine adjustment means 6b and the previous value comparison means 5e. The control voltage fine adjustment means 6b provides signals to a control voltage generation circuit 6f which generates a control voltage for the local excavator 40 so that the center frequency of the intermediate frequency signal converges to the regular intermediate frequency based on these signals. This can be realized by a frequency synthesizer circuit using a control voltage generation circuit 5f and a PLL-4G or a voltage synthesizer circuit using a D/A converter, etc. However, the local oscillator 4 uses a JM3 part oscillation frequency corresponding to the frequency of the selected channel by a tuning command signal. An iIrIr type pressure is generated so that the voltage oscillates, and the frequency is finely adjusted by a signal from the control voltage fine adjustment means 5b. The input signal 1 inputs the output of the local oscillator 4 as needed. The delay time setting means 5d sets the delay time from changing the inter-local oscillation wave number by the control voltage fine adjustment means 5b or by receiving a channel selection command until inputting the supplementary IF judgment signal and the correction direction signal by the signal input means 6C. play a role. The previous value comparing means 5e plays the role of detecting when the logical values of the input correction judgment signal and correction direction signal change, so it stores these logical values and compares them with the new input values. The delay time in the delay time setting means 6d is changed based on the detected output of the difference.
選局指令信号により選局するチャンネルを切替える度に
補正判定信号及び補正方向信号がそれらのiE規の値に
収束するのに必要な時間の約0.1倍から0.3倍程度
の遅延時間を遅延時間設定手段5dに力えるので、AF
C引込み動作における所背時間は従来の約0.1倍から
0.3倍に短縮される。しか【〜補正判定信号及び補正
方向信号が正規の値に収束するだけの時間をり−えてい
々いので、AFC引込み動作により中間周波数はずfl
ていたと反対の方向に行きすぎてし捷う。この状況を第
11図および第12図における諸条件で考えてみる。Each time the channel to be selected is switched by the channel selection command signal, the delay time is about 0.1 to 0.3 times the time required for the correction judgment signal and correction direction signal to converge to their iE standard values. is applied to the delay time setting means 5d, so that the AF
The time required for the C retraction operation is reduced from approximately 0.1 times to 0.3 times that of the conventional method. However, since it takes time for the correction judgment signal and the correction direction signal to converge to the normal values, the intermediate frequency is changed by the AFC pull-in operation.
I ended up going too far in the opposite direction. Let us consider this situation using the conditions shown in FIGS. 11 and 12.
第11図からs o KHzの周波数精度にて周波数比
較信号(即ち判定方向信号等)が正規の論理値となるだ
めの遅延時間は1秒であるから、選局毎に遅延時間設定
手段6dに力える遅延時間を1秒X0.1 =0.1秒
とすると、第11図より500 KHzの行きすぎ量が
生じることが判る。第12図のように+3 MHzの周
波数すねが牛じている時に局部発振器4の発振周波数の
微調時制御計が20o KHzであるとすtlば、第3
図のようにAFC引込み動作が行なわれる。第3図から
判るように17回目の周波数微調により初めて周波数比
較出力の論理値が変化するので、ここで遅延時間の設定
を本来の1秒にすると第11図より行きすぎhlはわず
か50 KHzであるから、今度は第2の周波数比較出
力をり、なから周波数ずわの補正をするへどとなり第4
図のようにして18[111[]の周周波機微でAFC
引込みが完了する。故にAFC引込みが完了する捷での
所要時間は、
0.1秒x 17−1−1秒×1−二2,7秒であるの
で従来の14秒に比べて相当少ない所要時間となる。As shown in FIG. 11, the delay time required for the frequency comparison signal (i.e., judgment direction signal, etc.) to have a normal logical value with a frequency accuracy of so KHz is 1 second. If the delay time for applying force is 1 second x 0.1 = 0.1 seconds, it can be seen from FIG. 11 that an overshoot of 500 KHz occurs. As shown in Fig. 12, if the fine adjustment time control meter for the oscillation frequency of the local oscillator 4 is 20o KHz when the +3 MHz frequency is operating, then the third
The AFC pull-in operation is performed as shown in the figure. As can be seen from Figure 3, the logical value of the frequency comparison output changes for the first time after the 17th frequency fine adjustment, so if the delay time is set to the original 1 second, as shown in Figure 11, the excessive HL is only 50 KHz. Since there is, the second frequency comparison output is used, and the fourth one is used to correct the frequency distortion.
AFC with frequency sensitivity of 18[111[] as shown in the figure.
Retraction is complete. Therefore, the time required to complete AFC retraction is 0.1 seconds x 17-1-1 seconds x 1-22.7 seconds, which is considerably less time than the conventional 14 seconds.
なお、遅延時間を0.3倍にした場合では行きすぎ量は
152 KHzであり、AFC引込み完了の所要時間は
約6秒となる。Note that when the delay time is increased by 0.3 times, the overshoot amount is 152 KHz, and the time required to complete AFC pull-in is approximately 6 seconds.
発明の効果
以」二のように本発明のAFC回路は、周波数微調の周
it>tを補正判定信号及び袖IF力向信号が本来必要
とする遅延時間より約0.1倍から0.3倍程度に選ぶ
ことにより、AFC引込みの所要時間を犬l1県に短縮
できるとともに、補正判定信号及び補正方向信号の変化
を検出した時以降は本来それらの信号が必要とする遅延
時間を与えることにより、従来例と同等の周波数精度で
AFC動作を行なうことができる。Effects of the Invention As described in 2., the AFC circuit of the present invention has a frequency fine adjustment frequency it>t that is approximately 0.1 to 0.3 times longer than the delay time originally required by the correction determination signal and the sleeve IF force direction signal. By selecting approximately double the amount, the time required for AFC pull-in can be shortened to 11 times, and after a change in the correction judgment signal and correction direction signal is detected, it is possible to provide the delay time originally required by those signals. , AFC operation can be performed with frequency accuracy equivalent to that of the conventional example.
第1図は本発明の一実施例におけるAFC回路のブロッ
ク図、第2図は第1図のシンセザイザ回路の詳細ブロッ
ク図、第3図、第4図は同本実施例におけるAFC引込
み動作を示す特性図、第6図は従来例におけるAFC回
路のブロック図、第6図は第5図の周波数ずれ検出器の
構成を示すブロック図、第7図は本発明に先だって提案
されているAFC回路のブロック図、第8図は位相・周
波数検波器の入出力特性図、第9図は第7図の周波数比
較器である位相・周波数比較器の構成を示す回路ブロッ
ク図、第10図は第7図のL P F 16゜17の出
力特性図、第11図は第7図のLPF16゜1了の出力
の遅延時間の特性図、第12図は第7図のAFC回路に
おけるAFC引込み動作を示す図である。
4・・・・・局部発振器、6・・・・・・シンセザイザ
回路、5a・・・・・マイクロコンピュータ回路、5b
・・・・・・制御電圧微調手段、6C・・・・信号入力
手段、5d・・・・・遅延時間設定手段、5e・・・・
・・前置比較手段、6f・・・・・・制御電圧発生回路
、18・・・・・・周波数ずれ検出器。
代理人の氏名 弁理士 中 尾 敏 力 ほか1名H
へ
図URoっ
第 8 図
第 9 図
第1C図FIG. 1 is a block diagram of an AFC circuit in one embodiment of the present invention, FIG. 2 is a detailed block diagram of the synthesizer circuit in FIG. 1, and FIGS. 3 and 4 show AFC pull-in operation in the same embodiment. 6 is a block diagram of a conventional AFC circuit, FIG. 6 is a block diagram showing the configuration of the frequency shift detector of FIG. 5, and FIG. 7 is a block diagram of an AFC circuit proposed prior to the present invention. Block diagram, Figure 8 is an input/output characteristic diagram of the phase/frequency detector, Figure 9 is a circuit block diagram showing the configuration of the phase/frequency comparator, which is the frequency comparator in Figure 7, and Figure 10 is the Figure 11 shows the output characteristic diagram of the LPF 16°17 shown in Figure 7. Figure 12 shows the output delay time characteristic diagram of the LPF 16°17 shown in Figure 7. Figure 12 shows the AFC pull-in operation in the AFC circuit shown in Figure 7. It is a diagram. 4...Local oscillator, 6...Synthesizer circuit, 5a...Microcomputer circuit, 5b
...Control voltage fine adjustment means, 6C...Signal input means, 5d...Delay time setting means, 5e...
. . . Pre-comparison means, 6f . . . Control voltage generation circuit, 18 . . . Frequency shift detector. Name of agent: Patent attorney Satoshi Nakao and 1 other person H
Figure 8 Figure 9 Figure 1C
Claims (1)
波数混合器を用いて周波数変換された中間周波信号から
、その中間周波信号の中心周波数が正規の中間周波数と
比べて所定値以上周波数ずれが生じているかどうかを判
定してそれを補正判定信号として得るとともにその周波
数ずれが正規の中間周波数と比べて高いか低いかの方向
を判定してそれを補正方向信号として得る周波数ずれ検
出器と、前記の補正判定信号と補正方向信号とを遅延時
間設定手段の制御により入力する信号入力手段と、上記
信号入力手段の出力を入力して周波数制御電圧の微調を
行う制御電圧微調手段と、上記信号入力手段の出力を入
力して前回の記憶手続により記憶されているそれらの論
理値と入力信号の論理値との差異の有無を判定するとと
もにそれらの信号の論理値を各々更新記憶する前値比較
手段と、上記制御電圧微調手段の出力と選局指令信号と
上記前値比較手段の出力とを入力して局部発振周波数の
変更が完了してから上記信号入力手段が入力信号の論理
値を読み込むまでの遅延時間の設定を行なう遅延時間設
定手段と、上記選局指令信号と上記制御電圧微調手段の
出力を入力して上記電圧制御型局部発振器の制御電圧を
発生する制御電圧発生回路とを有するシンセサイザ回路
とを備え、上記選局指令信号による選局動作毎に上記補
正判定信号及び上記補正方向信号がそれらの正規の値に
収束するのに必要な時間の約0.1倍から0.3倍程度
の遅延時間を上記遅延時間設定手段に与え、上記前値比
較手段により補正判定信号もしくは補正方向信号の論理
値が記憶してあるそれらの論理値から初めて変化した時
点以降は上記補正判定信号及び上記補正方向信号がそれ
らの正規の値に収束するのに必要な時間と同等以上の遅
延時間を上記遅延時間設定手段に与えて上記電圧制御型
局部発振器の制御電圧を微調するよう構成したことを特
徴とするAFC回路。If the center frequency of the intermediate frequency signal is frequency-converted using a frequency mixer that inputs the received signal and the output of the voltage-controlled local oscillator, the center frequency of the intermediate frequency signal has a frequency deviation of a predetermined value or more compared to the regular intermediate frequency. a frequency shift detector that determines whether the frequency shift has occurred and obtains it as a correction determination signal, and also determines the direction in which the frequency shift is higher or lower than the regular intermediate frequency and obtains it as a correction direction signal; a signal input means for inputting the correction determination signal and the correction direction signal under the control of the delay time setting means; a control voltage fine adjustment means for finely adjusting the frequency control voltage by inputting the output of the signal input means; and the signal input means for finely adjusting the frequency control voltage. A previous value comparison that inputs the output of the input means and determines whether there is a difference between the logical values stored by the previous storage procedure and the logical value of the input signal, and updates and stores the logical values of those signals. and the signal input means reads the logic value of the input signal after the change of the local oscillation frequency is completed by inputting the output of the control voltage fine adjustment means, the tuning command signal, and the output of the previous value comparison means. and a control voltage generation circuit that inputs the channel selection command signal and the output of the control voltage fine adjustment means to generate a control voltage for the voltage-controlled local oscillator. a synthesizer circuit, the time required for the correction determination signal and the correction direction signal to converge to their normal values for each channel selection operation based on the channel selection command signal is approximately 0.1 to 0.3 times longer. A delay time of about twice as much is given to the delay time setting means, and after the time when the logical value of the correction judgment signal or the correction direction signal changes for the first time from the stored logical value by the previous value comparison means, the correction judgment signal is and configured to finely adjust the control voltage of the voltage-controlled local oscillator by giving the delay time setting means a delay time equal to or longer than the time required for the correction direction signals to converge to their normal values. An AFC circuit featuring:
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20682585A JPS6267918A (en) | 1985-09-19 | 1985-09-19 | Afc circuit |
US06/908,897 US4709406A (en) | 1985-09-19 | 1986-09-18 | A.F.C. system for broad-band FM receiver |
CA000518492A CA1259378A (en) | 1985-09-19 | 1986-09-18 | A.f.c. system for broad-band fm receiver |
EP86112956A EP0215490B1 (en) | 1985-09-19 | 1986-09-19 | A.f.c. system for broad-band fm receiver |
DE8686112956T DE3686110T2 (en) | 1985-09-19 | 1986-09-19 | AFC ARRANGEMENT FOR BROADBAND FM RECEIVER. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20682585A JPS6267918A (en) | 1985-09-19 | 1985-09-19 | Afc circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6267918A true JPS6267918A (en) | 1987-03-27 |
JPH0342807B2 JPH0342807B2 (en) | 1991-06-28 |
Family
ID=16529699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20682585A Granted JPS6267918A (en) | 1985-09-19 | 1985-09-19 | Afc circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6267918A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01177213A (en) * | 1988-01-06 | 1989-07-13 | Seiko Epson Corp | Automatic frequency controller |
JPH02243011A (en) * | 1989-03-15 | 1990-09-27 | Nippon Hoso Kyokai <Nhk> | Afc circuit |
JPH02260912A (en) * | 1989-03-31 | 1990-10-23 | Icom Inc | Method and circuit for automatically controlling frequency |
JPH04152709A (en) * | 1990-10-16 | 1992-05-26 | Matsushita Electric Ind Co Ltd | Afc equipment |
-
1985
- 1985-09-19 JP JP20682585A patent/JPS6267918A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01177213A (en) * | 1988-01-06 | 1989-07-13 | Seiko Epson Corp | Automatic frequency controller |
JPH02243011A (en) * | 1989-03-15 | 1990-09-27 | Nippon Hoso Kyokai <Nhk> | Afc circuit |
JPH02260912A (en) * | 1989-03-31 | 1990-10-23 | Icom Inc | Method and circuit for automatically controlling frequency |
JPH04152709A (en) * | 1990-10-16 | 1992-05-26 | Matsushita Electric Ind Co Ltd | Afc equipment |
Also Published As
Publication number | Publication date |
---|---|
JPH0342807B2 (en) | 1991-06-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |