JPS6267918A - Afc circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably the required pull-in time of AFC by selecting the period of frequency minute adjustment as nearly 0.1-0.3 time of the delay time required substantially for a correction discrimination signal and a correction direction signal. CONSTITUTION:Every time a channel selected by a channel selection command signal is switched, a delay time of nearly 0.1-0.3 time of the time required for the correction discrimination signal and the correction direction signal to be converged into normal values is given and when the overshoot is caused to change the logic value of the correction discrimination signal or the correction direction signal is changed, it is detected by a pre-value comparison means 5e and the delay time in a delay time setting means 5d is subject to setting change for a time required to converge the correction discrimination signal and the correction direction signal into a normal value or over. The signal input means 5c inputs the correction discrimination signal sand the correction direction signal in a proper timing set by the delay time setting means 5d and when the center frequency of an intermediate frequency signal is to be converged to the normal intermediate frequency by giving a signal to a controlled voltage generating circuit 5f to form the control voltage of the local oscillator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an AFC (automatic frequency control) circuit that can be used in satellite broadcasting receivers and the like.

Conventional technology In a receiver having a frequency synthesizer type tuning circuit, the frequency accuracy of the local oscillator is equivalent to the accuracy of the reference oscillator of the frequency synthesizer circuit, and since a crystal oscillator is usually used as the reference oscillator, the received signal When the frequency accuracy of the intermediate frequency signal is good, the frequency accuracy of the intermediate frequency signal is sufficiently high and an AFC circuit is not necessary. (In the satellite broadcasting receiving system, the microwave band reception signal is frequency-converted into a first intermediate frequency signal in an outdoor down converter, then guided indoors by a cable, and the first intermediate frequency signal is transmitted indoors.) Generally, a second frequency conversion is performed at the receiver (to obtain a second intermediate frequency signal). Frequency conversion to the second intermediate frequency is usually performed for channel selection, and the signal of the desired channel is In such a tuning system configuration, no matter how high the frequency accuracy of the local oscillator for tuning in the indoor receiver can be made using a frequency synthesizer method, the frequency accuracy of the local oscillator in the outdoor down converter is poor. The frequency accuracy of the second intermediate frequency cannot be improved unless the frequency is good.Actually, the oscillation frequency of the local oscillator of an outdoor down converter generally has a temperature drift of several MHz.

On the other hand, the frequency accuracy of the second intermediate frequency is at worst several hundred KHz.
Even if the receiver's tuning circuit has a frequency synthesis method, an AFC circuit is essential to keep the frequency accuracy of the second intermediate frequency high.

AF to frequency synthesizer type tuning circuit like above 17
A conventional example of a C circuit is disclosed in Japanese Patent Application Laid-Open No. 56-23674.
There are some that are shown in the publication.

FIG. 5 is a block diagram showing the configuration of this conventional example.

A conventional example will be described below with reference to the drawings.

In Fig. 6, 1 is a received signal input terminal, 2 is a high frequency amplifier, and 3 is a high frequency amplifier.
is a frequency mixer, and 4 is a voltage-controlled local oscillator'&? 5.6
is a PLL synthesizer section, 6 is an intermediate frequency A-7 amplifier, 7 is an FM demodulator, 8 is a demodulated signal output terminal of the FM demodulator 7, 9 is a low-pass filter, and 10 is an intermediate frequency shift detector. .

FIG. 6 is a block diagram of the frequency shift detector 10. After smoothing the demodulated output of the FM demodulator 7 with a low-pass filter (hereinafter referred to as LPF) 9 and extracting the DC voltage component from the demodulated signal, the A constant threshold voltage vr1. Comparing with vr2. When a DC voltage component is extracted from the demodulated output of the FM signal through the LPF 9, an average voltage value of the demodulated signal is obtained, which corresponds to the average frequency of the FM signal.

Therefore, by configuring the system as shown in Fig. 6 and comparing the preset threshold voltage vrj + vr2 with the average voltage value of the demodulated output, it is possible to determine if the deviation from the center frequency of the intermediate frequency signal is within a predetermined range. If the deviation is outside a predetermined range, it can be detected whether the deviation is higher or lower than the center frequency.

These can be found by examining the outputs from the output terminals 1oθ and 10f in FIG. The AFC circuit can be configured by inputting these outputs to the PLL synthesizer section 5 and finely adjusting the oscillation frequency of the local oscillators 46 and -7 to reduce the deviation of the intermediate frequency from the center frequency. can.

However, in the above configuration, the frequency reference of the AFC circuit is the FM demodulator 7 itself, and the FM demodulators used in satellite broadcasting receivers usually handle high frequency and wideband signals, so their input frequency The temperature stability of the output voltage is not very good. Therefore, it is difficult to realize an AFC circuit with high frequency accuracy. Especially when the signal to be demodulated is a video signal that requires high linearity, it is important to prevent amplitude and phase distortion from occurring when passing through an intermediate frequency bandpass filter due to a shift in the intermediate frequency. be.

In order to solve the above problems, an AFC circuit having a configuration as shown in FIG. 7 has been proposed. The human FC circuit according to the present proposal will be described below with reference to the drawings. In FIG. 7, a received signal is input to an input terminal 1, a high frequency amplifier 2, a frequency mixer 3. The signal is inputted to an FM demodulator 7 through an intermediate frequency amplifier 6, and a demodulated output is obtained at an output terminal 8. A voltage controlled local oscillator 4 is controlled by a synthesizer circuit 5 whose control voltage is controlled.

The control type FE synthesizer circuit 5 can be of a PLL frequency synthesizer type or a voltage synthesizer type using a D/A converter or the like.

Now, the intermediate frequency signals are passed through frequency dividers 11 and 12, each having a frequency division ratio of NH9NL, to a frequency comparator 1.
4.15 is entered. The output signal of the reference signal oscillator 13 having a frequency of f8 is input to the other input terminal of the frequency comparator 14,15. As the reference signal, a frequency-divided crystal oscillator output with high frequency accuracy may be used. The frequency comparators 14, 16 and i~ use theatal type phase/frequency detectors having input/output characteristics as shown in FIG. 8 and configured as shown in the circuit block diagram of FIG. 9. As can be seen from Figure 9, if the center frequency of the divided intermediate frequency signal is higher than the paper slip frequency, the output of the phase/frequency detector will be at a high level (hereinafter referred to as t+HII); The output is low level (hereinafter "L°")
). 1 to 1, the output also includes the substrate frequency component, so in order to remove this, LPFl 6
．． Each frequency comparison signal is taken out via the 1st line. Here, if the normal intermediate frequency is fo, then fs+NHrNL is determined so that the following equation holds.

fs X NL < fo < fs X NH, that is,
The frequency fs of the signal output to the time frequency divider 11 with an intermediate frequency of fsXNH is equal to 1, and since the frequency comparator 14 can discriminate the frequency at this frequency, the logical value of the frequency comparison output changes. Similarly, the intermediate frequency is f
It also occurs in sXNt. Therefore, the relationship between the intermediate frequency and each frequency comparison signal is shown in Fig. 10 (a) and (b'l
It becomes as shown in . As can be seen from Figure 1o, each frequency comparator changes its output logic value at the detection limits fsXNu and fsXNb for deviations from the normal intermediate frequency fo, so the detection limits of the comparators are set to fo±300KHz @ degrees. ~, the frequency comparison signal can be used to determine whether or not the control voltage of the local oscillator 4 needs to be finely adjusted at −7°, or the direction in which it should be finely adjusted, which improves frequency accuracy. A high AFCN road can be achieved.

Although there are only 17 problems that the invention attempts to solve, the above configuration uses a phase/frequency detector having phase/frequency comparison characteristics as shown in FIG. If the intermediate frequency signal to be handled is a wideband FM signal, its FM modulation index is quite large, so it is necessary to lower the FM modulation index by making the frequency division ratio NH + NL sufficiently large to prevent the frequency comparator from malfunctioning. There is. In particular, in satellite broadcasting, in order to avoid interference with terrestrial microwave communication, an energy diffusion signal is superimposed on top of the video signal and transmitted, and the frequency is 30 Hz.
The frequency displacement is about 2MH2p-p.

Therefore, since the modulation index is approximately 67,000, the frequency division ratio must be approximately 50,000 or more.

In this way, a fairly large value is required as the frequency division ratio, 10.

Therefore, the frequency difference between the intermediate frequency signal and the reference signal at the frequency comparator input, where frequency discrimination of the intermediate frequency signal is performed, is the difference between the center frequency of the intermediate frequency signal in the actual intermediate frequency band and the frequency discrimination of the intermediate frequency. Detection limit f S X NH+ f
This is about 1/50000 smaller than the difference with 8.times.NL. For example, 300 KHz in the intermediate frequency band
The frequency difference changes to 6Hz at the frequency comparator input.

The frequency comparison signal requires a delay time at least as long as the period of the 6Hz signal to extract the DC component, so it takes about 0.17 seconds for a normal logic value to be output.
A waiting time of seconds is required. In other words, the closer the intermediate frequency is to the detection limit for frequency discrimination of the intermediate frequency, the longer the time required for the frequency comparison signal to reach the normal logical value.
This situation is shown in FIG. As you can see from this figure, e
Since a detection waiting time of 1 second is required to compare frequencies with an accuracy of i OKHz, for example, the pull-in range of the AFC circuit is set to ±3 MHz, and the frequency deviation detection limit is set to ±300 KHz, i~, local oscillator. When the control amount during fine adjustment of the oscillation frequency is set to 200 KHz, and the intermediate frequency deviates from the regular intermediate frequency by +3 MHz, which is the maximum value of the pull-in range, when an arbitrary signal is selected by the channel selection function. If the oscillation frequency of the local oscillator is changed to 200 KHz at intervals of 1 second, and the intermediate frequency signal is pulled in to the regular intermediate frequency by AFC circuit operation, the result will be as shown in Fig. 12 (a), (+)). The situation will be as shown.

In other words, the local oscillation frequency is finely adjusted by the function of the AFC circuit from the intermediate frequency frequency +3 MHz to reduce the frequency deviation, but since one frequency fine adjustment is a frequency shift of 200 KHz, it is necessary to adjust the local oscillation frequency 14 times. The AFC pull-in operation is completed only after repeating the frequency shift. Therefore, the time required for this operation is 1 second x 14 times = 14 seconds, resulting in a problem that a considerably long AFC pull-in time is required.

In addition, even in the conventional example shown in Fig. 5, it is necessary to smooth the demodulated signal with an LPF to obtain an average DC voltage in order to compare the demodulated signal with a reference signal and detect a frequency deviation. A video signal on which a low-frequency energy diffusion signal is superimposed is 1? In order to achieve smoothness, the time constant of the LPF must be made thicker by 1, otherwise an error will occur in the detection of frequency deviation. Raise the level of this useless frequency teaching. If you choose L, it is necessary to increase the waiting time to detect the frequency deviation, which also increases the AFC pull-in time.

In view of the above-mentioned problems, the present invention is an AF system that can significantly shorten the time required for AFC pull-in from the end of channel selection.
The purpose is to provide C circuits! -I'm doing it. .

Means for Solving the Problem In order to achieve this object, the AFCl circuit of the present invention determines whether the center frequency of the intermediate frequency signal differs in frequency by more than a predetermined value compared to the normal intermediate frequency. Shiso J
Obtain l as a correction judgment signal and calculate its frequency]
A frequency detector J1 determines whether the frequency is higher or lower than the regular intermediate frequency and uses it as a correction direction signal. a signal input means for inputting a correction determination signal and a correction direction signal to the synthesizer circuit under the control of a delay time setting means; a control voltage fine adjustment means for finely adjusting a frequency control voltage by inputting the output of the signal input means; Previous value comparison means inputs the output of the signal input means and determines whether there is a difference between the logical values stored by the previous storage procedure and the input value, and updates and stores each of the logical values; The output of the voltage fine adjustment means, the channel selection command signal, and the output of the previous value comparison means are inputted to set the delay time from when the change of the local oscillation frequency is completed until the signal input means reads the take of the input signal. comprising a delay time setting means, and a control voltage generation circuit that inputs a channel selection command signal and an output of the control voltage fine adjustment means to generate a control voltage for a local oscillator,
Set a delay time of about 0.1 to 0.3 times the time required for the correction direction signal and correction judgment signal to converge to their normal values for each channel selection operation by the channel selection command signal. After the correction judgment signal or the logical value of the correction judgment signal first changes from the stored logical value by the previous value comparison means, the correction judgment signal and the correction direction signal converge to their normal values. The control voltage of the local oscillation [+-]'1 path is finely adjusted by a delay time equal to or longer than the time required for the local oscillation.

Operation The present invention uses the above-described configuration to obtain a correction determination signal and a correction direction signal necessary for finely adjusting the detected frequency of the local oscillator using the frequency deviation detector. Appropriate timing is given by these reliable delay time setting means, and each logic value is read and switched by the signal input means. These logical values are used by the control voltage fine adjustment means to control the control voltage generation circuit to finely adjust the local oscillator control voltage. The previous value comparison means determines whether the correction judgment signal or the correction direction signal input by the signal input means is different from those values already stored, and if a difference occurs, the delay time of the delay time setting means is determined. control to change. The signal that is input once is updated and stored, and is used for the next difference determination.

Every time the channel to be selected is switched by the channel selection command signal, the correction judgment signal and correction direction signal change to their normal values by 1.
17 Since the delay time is approximately 0.1 to 0.3 times the time required for overlapping, the time interval for fine frequency adjustment in AFC pull-in operation is short compared to the originally required time. The AFC pull-in time is reduced by 1. Since the time interval of frequency fine adjustment is shortened by i~, the supplementary IF judgment signal or supplementary direction signal does not become a normal logical value, and the frequency fine adjustment operation goes too far and is interrupted.゛ increases in proportion to the degree of time reduction. It is necessary to determine this time reduction rate by taking into consideration the 0-inch clearance amount, and if the time reduction rate is about 0.1 to 0.3 times, there will not be a large margin of overshoot.

Now, since the delay time is shortened and the frequency fine adjustment is performed at high speed, a slight amount of clearance occurs, causing a change in the logical value of the correction judgment signal or correction direction signal. This is detected by the previous value comparison means. Since the delay time in the delay time setting means is changed to be equal to or longer than the time required for the correction judgment signal and the correction direction signal to converge to their normal values, the overshooting will not occur this time. Therefore, the intermediate frequency C4 is gradually being pulled down to the regular intermediate frequency.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an AFCl path in accordance with one embodiment of the present invention. In FIG. 1, a received signal is input to an input terminal 1, and an intermediate frequency signal is obtained at an output terminal 22 after passing through a high frequency amplifier 2, a frequency mixer 3, a local excavator 4 for frequency conversion, and an intermediate frequency amplifier 2 (6). The configuration is the same as that shown in FIG. 5 of the conventional example.The frequency detector 18 may have the configuration shown in FIG. 6 of the conventional example, or as shown in FIG. Oscillator 13, frequency comparator 14.
16, LPF16.17 configuration is also possible, but the 7th
To explain the platform in the figure, the output of LPF16 and the LP
If it is exclusive ORed with the output of Fl 7, it can be used as a correction determination signal.

Also, if the output of LPF16 is H'', it means that the frequency is shifting toward the higher side, and if the output of LPF1 is L'', it is known that the frequency is shifting toward the lower side. It can be a correction direction signal.

The synthesizer circuit 6 generates a control voltage for controlling the oscillation frequency of the local oscillator 4 by inputting the correction judgment signal, the correction direction signal, and the tuning command signal input from the terminal 21, and its details are shown in FIG. It can be expressed as a block diagram. Signal input means 5C1 control voltage fine adjustment means 5b, previous value comparison means 6e,
The delay time setting means 5d is a microcomputer circuit 5a.
This is a function realized in . The signal input means 6C inputs the correction determination signal and the correction direction signal at an appropriate timing set by the delay time setting means 5d. These input signals are sent to the control voltage fine adjustment means 6b and the previous value comparison means 5e. The control voltage fine adjustment means 6b provides signals to a control voltage generation circuit 6f which generates a control voltage for the local excavator 40 so that the center frequency of the intermediate frequency signal converges to the regular intermediate frequency based on these signals. This can be realized by a frequency synthesizer circuit using a control voltage generation circuit 5f and a PLL-4G or a voltage synthesizer circuit using a D/A converter, etc. However, the local oscillator 4 uses a JM3 part oscillation frequency corresponding to the frequency of the selected channel by a tuning command signal. An iIrIr type pressure is generated so that the voltage oscillates, and the frequency is finely adjusted by a signal from the control voltage fine adjustment means 5b. The input signal 1 inputs the output of the local oscillator 4 as needed. The delay time setting means 5d sets the delay time from changing the inter-local oscillation wave number by the control voltage fine adjustment means 5b or by receiving a channel selection command until inputting the supplementary IF judgment signal and the correction direction signal by the signal input means 6C. play a role. The previous value comparing means 5e plays the role of detecting when the logical values of the input correction judgment signal and correction direction signal change, so it stores these logical values and compares them with the new input values. The delay time in the delay time setting means 6d is changed based on the detected output of the difference.

Each time the channel to be selected is switched by the channel selection command signal, the delay time is about 0.1 to 0.3 times the time required for the correction judgment signal and correction direction signal to converge to their iE standard values. is applied to the delay time setting means 5d, so that the AF
The time required for the C retraction operation is reduced from approximately 0.1 times to 0.3 times that of the conventional method. However, since it takes time for the correction judgment signal and the correction direction signal to converge to the normal values, the intermediate frequency is changed by the AFC pull-in operation.
I ended up going too far in the opposite direction. Let us consider this situation using the conditions shown in FIGS. 11 and 12.

As shown in FIG. 11, the delay time required for the frequency comparison signal (i.e., judgment direction signal, etc.) to have a normal logical value with a frequency accuracy of so KHz is 1 second. If the delay time for applying force is 1 second x 0.1 = 0.1 seconds, it can be seen from FIG. 11 that an overshoot of 500 KHz occurs. As shown in Fig. 12, if the fine adjustment time control meter for the oscillation frequency of the local oscillator 4 is 20o KHz when the +3 MHz frequency is operating, then the third
The AFC pull-in operation is performed as shown in the figure. As can be seen from Figure 3, the logical value of the frequency comparison output changes for the first time after the 17th frequency fine adjustment, so if the delay time is set to the original 1 second, as shown in Figure 11, the excessive HL is only 50 KHz. Since there is, the second frequency comparison output is used, and the fourth one is used to correct the frequency distortion.
AFC with frequency sensitivity of 18[111[] as shown in the figure.
Retraction is complete. Therefore, the time required to complete AFC retraction is 0.1 seconds x 17-1-1 seconds x 1-22.7 seconds, which is considerably less time than the conventional 14 seconds.

Note that when the delay time is increased by 0.3 times, the overshoot amount is 152 KHz, and the time required to complete AFC pull-in is approximately 6 seconds.

Effects of the Invention As described in 2., the AFC circuit of the present invention has a frequency fine adjustment frequency it>t that is approximately 0.1 to 0.3 times longer than the delay time originally required by the correction determination signal and the sleeve IF force direction signal. By selecting approximately double the amount, the time required for AFC pull-in can be shortened to 11 times, and after a change in the correction judgment signal and correction direction signal is detected, it is possible to provide the delay time originally required by those signals. , AFC operation can be performed with frequency accuracy equivalent to that of the conventional example.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an AFC circuit in one embodiment of the present invention, FIG. 2 is a detailed block diagram of the synthesizer circuit in FIG. 1, and FIGS. 3 and 4 show AFC pull-in operation in the same embodiment. 6 is a block diagram of a conventional AFC circuit, FIG. 6 is a block diagram showing the configuration of the frequency shift detector of FIG. 5, and FIG. 7 is a block diagram of an AFC circuit proposed prior to the present invention. Block diagram, Figure 8 is an input/output characteristic diagram of the phase/frequency detector, Figure 9 is a circuit block diagram showing the configuration of the phase/frequency comparator, which is the frequency comparator in Figure 7, and Figure 10 is the Figure 11 shows the output characteristic diagram of the LPF 16°17 shown in Figure 7. Figure 12 shows the output delay time characteristic diagram of the LPF 16°17 shown in Figure 7. Figure 12 shows the AFC pull-in operation in the AFC circuit shown in Figure 7. It is a diagram. 4...Local oscillator, 6...Synthesizer circuit, 5a...Microcomputer circuit, 5b
...Control voltage fine adjustment means, 6C...Signal input means, 5d...Delay time setting means, 5e...
. . . Pre-comparison means, 6f . . . Control voltage generation circuit, 18 . . . Frequency shift detector. Name of agent: Patent attorney Satoshi Nakao and 1 other person H
Figure 8 Figure 9 Figure 1C

Claims (1)

[Claims] If the center frequency of the intermediate frequency signal is frequency-converted using a frequency mixer that inputs the received signal and the output of the voltage-controlled local oscillator, the center frequency of the intermediate frequency signal has a frequency deviation of a predetermined value or more compared to the regular intermediate frequency. a frequency shift detector that determines whether the frequency shift has occurred and obtains it as a correction determination signal, and also determines the direction in which the frequency shift is higher or lower than the regular intermediate frequency and obtains it as a correction direction signal; a signal input means for inputting the correction determination signal and the correction direction signal under the control of the delay time setting means; a control voltage fine adjustment means for finely adjusting the frequency control voltage by inputting the output of the signal input means; and the signal input means for finely adjusting the frequency control voltage. A previous value comparison that inputs the output of the input means and determines whether there is a difference between the logical values stored by the previous storage procedure and the logical value of the input signal, and updates and stores the logical values of those signals. and the signal input means reads the logic value of the input signal after the change of the local oscillation frequency is completed by inputting the output of the control voltage fine adjustment means, the tuning command signal, and the output of the previous value comparison means. and a control voltage generation circuit that inputs the channel selection command signal and the output of the control voltage fine adjustment means to generate a control voltage for the voltage-controlled local oscillator. a synthesizer circuit, the time required for the correction determination signal and the correction direction signal to converge to their normal values for each channel selection operation based on the channel selection command signal is approximately 0.1 to 0.3 times longer. A delay time of about twice as much is given to the delay time setting means, and after the time when the logical value of the correction judgment signal or the correction direction signal changes for the first time from the stored logical value by the previous value comparison means, the correction judgment signal is and configured to finely adjust the control voltage of the voltage-controlled local oscillator by giving the delay time setting means a delay time equal to or longer than the time required for the correction direction signals to converge to their normal values. An AFC circuit featuring: